projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] libata: prepare ata_sg_clean() for invocation from EH
[linux-2.6-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
8676ce07 51#define DRV_VERSION "2.0"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
648a88be 56 AHCI_MAX_PORTS = 32,
1da177e4
LT		 57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_USE_CLUSTERING = 0,
12fad3f9 60 AHCI_MAX_CMDS = 32,
dd410ff1 61 AHCI_CMD_SZ = 32,
12fad3f9 62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 63 AHCI_RX_FIS_SZ = 256,
a0ea7328 64 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 65 AHCI_CMD_TBL_HDR_SZ = 0x80,
66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 69 AHCI_RX_FIS_SZ,
70 AHCI_IRQ_ON_SG = (1 << 31),
71 AHCI_CMD_ATAPI = (1 << 5),
72 AHCI_CMD_WRITE = (1 << 6),
4b10e559 73 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 74 AHCI_CMD_RESET = (1 << 8),
75 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 76
77 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 79
80 board_ahci = 0,
648a88be
TH		 81 board_ahci_pi = 1,
82 board_ahci_vt8251 = 2,
83 board_ahci_ign_iferr = 3,
1da177e4
LT		 84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
0be0aa98 98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
78cd52d0
TH		 141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
4296971d 144 PORT_IRQ_PHYRDY |
78cd52d0
TH		 145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 152
153 /* PORT_CMD bits */
02eaa666 154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 158 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
0be0aa98 163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 167
168 /* hpriv->flags bits */
169 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 170
171 /* ap->flags bits */
4aeb0e32
TH		 172 AHCI_FLAG_NO_NCQ = (1 << 24),
173 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
648a88be 174 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
1da177e4
LT		 175};
176
177struct ahci_cmd_hdr {
178 u32 opts;
179 u32 status;
180 u32 tbl_addr;
181 u32 tbl_addr_hi;
182 u32 reserved[4];
183};
184
185struct ahci_sg {
186 u32 addr;
187 u32 addr_hi;
188 u32 reserved;
189 u32 flags_size;
190};
191
192struct ahci_host_priv {
193 unsigned long flags;
194 u32 cap; /* cache of HOST_CAP register */
195 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
196};
197
198struct ahci_port_priv {
199 struct ahci_cmd_hdr *cmd_slot;
200 dma_addr_t cmd_slot_dma;
201 void *cmd_tbl;
202 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 203 void *rx_fis;
204 dma_addr_t rx_fis_dma;
205};
206
207static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
208static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
209static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 210static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
7d12e780 211static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
1da177e4 212static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 213static int ahci_port_start(struct ata_port *ap);
214static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 215static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
216static void ahci_qc_prep(struct ata_queued_cmd *qc);
217static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 218static void ahci_freeze(struct ata_port *ap);
219static void ahci_thaw(struct ata_port *ap);
220static void ahci_error_handler(struct ata_port *ap);
ad616ffb 221static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 222static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
c1332875
TH		 223static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224static int ahci_port_resume(struct ata_port *ap);
225static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226static int ahci_pci_device_resume(struct pci_dev *pdev);
907f4678 227static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 228
193515d5 229static struct scsi_host_template ahci_sht = {
1da177e4
LT		 230 .module = THIS_MODULE,
231 .name = DRV_NAME,
232 .ioctl = ata_scsi_ioctl,
233 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 234 .change_queue_depth = ata_scsi_change_queue_depth,
235 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 236 .this_id = ATA_SHT_THIS_ID,
237 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 238 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
239 .emulated = ATA_SHT_EMULATED,
240 .use_clustering = AHCI_USE_CLUSTERING,
241 .proc_name = DRV_NAME,
242 .dma_boundary = AHCI_DMA_BOUNDARY,
243 .slave_configure = ata_scsi_slave_config,
ccf68c34 244 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 245 .bios_param = ata_std_bios_param,
c1332875
TH		 246 .suspend = ata_scsi_device_suspend,
247 .resume = ata_scsi_device_resume,
1da177e4
LT		 248};
249
057ace5e 250static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 251 .port_disable = ata_port_disable,
252
253 .check_status = ahci_check_status,
254 .check_altstatus = ahci_check_status,
1da177e4
LT		 255 .dev_select = ata_noop_dev_select,
256
257 .tf_read = ahci_tf_read,
258
1da177e4
LT		 259 .qc_prep = ahci_qc_prep,
260 .qc_issue = ahci_qc_issue,
261
1da177e4
LT		 262 .irq_handler = ahci_interrupt,
263 .irq_clear = ahci_irq_clear,
264
265 .scr_read = ahci_scr_read,
266 .scr_write = ahci_scr_write,
267
78cd52d0
TH		 268 .freeze = ahci_freeze,
269 .thaw = ahci_thaw,
270
271 .error_handler = ahci_error_handler,
272 .post_internal_cmd = ahci_post_internal_cmd,
273
c1332875
TH		 274 .port_suspend = ahci_port_suspend,
275 .port_resume = ahci_port_resume,
276
1da177e4
LT		 277 .port_start = ahci_port_start,
278 .port_stop = ahci_port_stop,
1da177e4
LT		 279};
280
ad616ffb
TH		 281static const struct ata_port_operations ahci_vt8251_ops = {
282 .port_disable = ata_port_disable,
283
284 .check_status = ahci_check_status,
285 .check_altstatus = ahci_check_status,
286 .dev_select = ata_noop_dev_select,
287
288 .tf_read = ahci_tf_read,
289
290 .qc_prep = ahci_qc_prep,
291 .qc_issue = ahci_qc_issue,
292
293 .irq_handler = ahci_interrupt,
294 .irq_clear = ahci_irq_clear,
295
296 .scr_read = ahci_scr_read,
297 .scr_write = ahci_scr_write,
298
299 .freeze = ahci_freeze,
300 .thaw = ahci_thaw,
301
302 .error_handler = ahci_vt8251_error_handler,
303 .post_internal_cmd = ahci_post_internal_cmd,
304
305 .port_suspend = ahci_port_suspend,
306 .port_resume = ahci_port_resume,
307
308 .port_start = ahci_port_start,
309 .port_stop = ahci_port_stop,
310};
311
98ac62de 312static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 313 /* board_ahci */
314 {
315 .sht = &ahci_sht,
cca3974e 316 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 317 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
318 ATA_FLAG_SKIP_D2H_BSY,
7da79312 319 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 320 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
321 .port_ops = &ahci_ops,
322 },
648a88be
TH		 323 /* board_ahci_pi */
324 {
325 .sht = &ahci_sht,
326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
328 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
bf2af2a2
BJ		 333 /* board_ahci_vt8251 */
334 {
335 .sht = &ahci_sht,
cca3974e 336 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 338 ATA_FLAG_SKIP_D2H_BSY |
339 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 340 .pio_mask = 0x1f, /* pio0-4 */
341 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 342 .port_ops = &ahci_vt8251_ops,
bf2af2a2 343 },
41669553
TH		 344 /* board_ahci_ign_iferr */
345 {
346 .sht = &ahci_sht,
347 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
348 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
349 ATA_FLAG_SKIP_D2H_BSY |
350 AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
354 },
1da177e4
LT		 355};
356
3b7d697d 357static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 358 /* Intel */
54bb3a94
JG		 359 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
360 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
361 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
362 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
363 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
364 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
365 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
366 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
367 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
368 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
648a88be
TH		 369 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
370 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
371 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
372 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
373 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
374 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
375 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
376 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
380 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
381 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
fe7fa31a
JG		 385
386 /* JMicron */
41669553
TH		 387 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
388 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
389 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
390 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
391 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
fe7fa31a
JG		 392
393 /* ATI */
54bb3a94
JG		 394 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
395 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
fe7fa31a
JG		 396
397 /* VIA */
54bb3a94 398 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 399
400 /* NVIDIA */
54bb3a94
JG		 401 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
895663cd
PC		 405 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
406 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
407 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
408 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 413
95916edd 414 /* SiS */
54bb3a94
JG		 415 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
416 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
417 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 418
415ae2b5
JG		 419 /* Generic, PCI class code for AHCI */
420 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 0x010601, 0xffffff, board_ahci },
422
1da177e4
LT		 423 { } /* terminate list */
424};
425
426
427static struct pci_driver ahci_pci_driver = {
428 .name = DRV_NAME,
429 .id_table = ahci_pci_tbl,
430 .probe = ahci_init_one,
c1332875
TH		 431 .suspend = ahci_pci_device_suspend,
432 .resume = ahci_pci_device_resume,
907f4678 433 .remove = ahci_remove_one,
1da177e4
LT		 434};
435
436
98fa4b60
TH		 437static inline int ahci_nr_ports(u32 cap)
438{
439 return (cap & 0x1f) + 1;
440}
441
1da177e4
LT		 442static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
443{
444 return base + 0x100 + (port * 0x80);
445}
446
ea6ba10b 447static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 448{
ea6ba10b 449 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 450}
451
1da177e4
LT		 452static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
453{
454 unsigned int sc_reg;
455
456 switch (sc_reg_in) {
457 case SCR_STATUS: sc_reg = 0; break;
458 case SCR_CONTROL: sc_reg = 1; break;
459 case SCR_ERROR: sc_reg = 2; break;
460 case SCR_ACTIVE: sc_reg = 3; break;
461 default:
462 return 0xffffffffU;
463 }
464
1e4f2a96 465 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 466}
467
468
469static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
470 u32 val)
471{
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS: sc_reg = 0; break;
476 case SCR_CONTROL: sc_reg = 1; break;
477 case SCR_ERROR: sc_reg = 2; break;
478 case SCR_ACTIVE: sc_reg = 3; break;
479 default:
480 return;
481 }
482
1e4f2a96 483 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 484}
485
9f592056 486static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 487{
7c76d1e8
TH		 488 u32 tmp;
489
d8fcd116 490 /* start DMA */
9f592056 491 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 492 tmp |= PORT_CMD_START;
493 writel(tmp, port_mmio + PORT_CMD);
494 readl(port_mmio + PORT_CMD); /* flush */
495}
496
254950cd
TH		 497static int ahci_stop_engine(void __iomem *port_mmio)
498{
499 u32 tmp;
500
501 tmp = readl(port_mmio + PORT_CMD);
502
d8fcd116 503 /* check if the HBA is idle */
254950cd
TH		 504 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
505 return 0;
506
d8fcd116 507 /* setting HBA to idle */
254950cd
TH		 508 tmp &= ~PORT_CMD_START;
509 writel(tmp, port_mmio + PORT_CMD);
510
d8fcd116 511 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 512 tmp = ata_wait_register(port_mmio + PORT_CMD,
513 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 514 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 515 return -EIO;
516
517 return 0;
518}
519
0be0aa98
TH		 520static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
521 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
522{
523 u32 tmp;
524
525 /* set FIS registers */
526 if (cap & HOST_CAP_64)
527 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
528 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
529
530 if (cap & HOST_CAP_64)
531 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
532 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
533
534 /* enable FIS reception */
535 tmp = readl(port_mmio + PORT_CMD);
536 tmp |= PORT_CMD_FIS_RX;
537 writel(tmp, port_mmio + PORT_CMD);
538
539 /* flush */
540 readl(port_mmio + PORT_CMD);
541}
542
543static int ahci_stop_fis_rx(void __iomem *port_mmio)
544{
545 u32 tmp;
546
547 /* disable FIS reception */
548 tmp = readl(port_mmio + PORT_CMD);
549 tmp &= ~PORT_CMD_FIS_RX;
550 writel(tmp, port_mmio + PORT_CMD);
551
552 /* wait for completion, spec says 500ms, give it 1000 */
553 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
554 PORT_CMD_FIS_ON, 10, 1000);
555 if (tmp & PORT_CMD_FIS_ON)
556 return -EBUSY;
557
558 return 0;
559}
560
561static void ahci_power_up(void __iomem *port_mmio, u32 cap)
562{
563 u32 cmd;
564
565 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
566
567 /* spin up device */
568 if (cap & HOST_CAP_SSS) {
569 cmd |= PORT_CMD_SPIN_UP;
570 writel(cmd, port_mmio + PORT_CMD);
571 }
572
573 /* wake up link */
574 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
575}
576
577static void ahci_power_down(void __iomem *port_mmio, u32 cap)
578{
579 u32 cmd, scontrol;
580
581 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
582
583 if (cap & HOST_CAP_SSC) {
584 /* enable transitions to slumber mode */
585 scontrol = readl(port_mmio + PORT_SCR_CTL);
586 if ((scontrol & 0x0f00) > 0x100) {
587 scontrol &= ~0xf00;
588 writel(scontrol, port_mmio + PORT_SCR_CTL);
589 }
590
591 /* put device into slumber mode */
592 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
593
594 /* wait for the transition to complete */
595 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
596 PORT_CMD_ICC_SLUMBER, 1, 50);
597 }
598
599 /* put device into listen mode */
600 if (cap & HOST_CAP_SSS) {
601 /* first set PxSCTL.DET to 0 */
602 scontrol = readl(port_mmio + PORT_SCR_CTL);
603 scontrol &= ~0xf;
604 writel(scontrol, port_mmio + PORT_SCR_CTL);
605
606 /* then set PxCMD.SUD to 0 */
607 cmd &= ~PORT_CMD_SPIN_UP;
608 writel(cmd, port_mmio + PORT_CMD);
609 }
610}
611
612static void ahci_init_port(void __iomem *port_mmio, u32 cap,
613 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
614{
615 /* power up */
616 ahci_power_up(port_mmio, cap);
617
618 /* enable FIS reception */
619 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
620
621 /* enable DMA */
622 ahci_start_engine(port_mmio);
623}
624
625static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
626{
627 int rc;
628
629 /* disable DMA */
630 rc = ahci_stop_engine(port_mmio);
631 if (rc) {
632 *emsg = "failed to stop engine";
633 return rc;
634 }
635
636 /* disable FIS reception */
637 rc = ahci_stop_fis_rx(port_mmio);
638 if (rc) {
639 *emsg = "failed stop FIS RX";
640 return rc;
641 }
642
643 /* put device into slumber mode */
644 ahci_power_down(port_mmio, cap);
645
646 return 0;
647}
648
d91542c1
TH		 649static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
650{
98fa4b60 651 u32 cap_save, impl_save, tmp;
d91542c1
TH		 652
653 cap_save = readl(mmio + HOST_CAP);
654 cap_save &= ( (1<<28) | (1<<17) );
655 cap_save |= (1 << 27);
98fa4b60 656 impl_save = readl(mmio + HOST_PORTS_IMPL);
d91542c1
TH		 657
658 /* global controller reset */
659 tmp = readl(mmio + HOST_CTL);
660 if ((tmp & HOST_RESET) == 0) {
661 writel(tmp | HOST_RESET, mmio + HOST_CTL);
662 readl(mmio + HOST_CTL); /* flush */
663 }
664
665 /* reset must complete within 1 second, or
666 * the hardware should be considered fried.
667 */
668 ssleep(1);
669
670 tmp = readl(mmio + HOST_CTL);
671 if (tmp & HOST_RESET) {
672 dev_printk(KERN_ERR, &pdev->dev,
673 "controller reset failed (0x%x)\n", tmp);
674 return -EIO;
675 }
676
98fa4b60 677 /* turn on AHCI mode */
d91542c1
TH		 678 writel(HOST_AHCI_EN, mmio + HOST_CTL);
679 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60
TH		 680
681 /* These write-once registers are normally cleared on reset.
682 * Restore BIOS values... which we HOPE were present before
683 * reset.
684 */
685 if (!impl_save) {
686 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
687 dev_printk(KERN_WARNING, &pdev->dev,
688 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
689 }
d91542c1 690 writel(cap_save, mmio + HOST_CAP);
98fa4b60 691 writel(impl_save, mmio + HOST_PORTS_IMPL);
d91542c1
TH		 692 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
693
694 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
695 u16 tmp16;
696
697 /* configure PCS */
698 pci_read_config_word(pdev, 0x92, &tmp16);
699 tmp16 |= 0xf;
700 pci_write_config_word(pdev, 0x92, tmp16);
701 }
702
703 return 0;
704}
705
706static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
648a88be
TH		 707 int n_ports, unsigned int port_flags,
708 struct ahci_host_priv *hpriv)
d91542c1
TH		 709{
710 int i, rc;
711 u32 tmp;
712
713 for (i = 0; i < n_ports; i++) {
714 void __iomem *port_mmio = ahci_port_base(mmio, i);
715 const char *emsg = NULL;
716
648a88be
TH		 717 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
718 !(hpriv->port_map & (1 << i)))
d91542c1 719 continue;
d91542c1
TH		 720
721 /* make sure port is not active */
648a88be 722 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
d91542c1
TH		 723 if (rc)
724 dev_printk(KERN_WARNING, &pdev->dev,
725 "%s (%d)\n", emsg, rc);
726
727 /* clear SError */
728 tmp = readl(port_mmio + PORT_SCR_ERR);
729 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
730 writel(tmp, port_mmio + PORT_SCR_ERR);
731
f4b5cc87 732 /* clear port IRQ */
d91542c1
TH		 733 tmp = readl(port_mmio + PORT_IRQ_STAT);
734 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
735 if (tmp)
736 writel(tmp, port_mmio + PORT_IRQ_STAT);
737
738 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 739 }
740
741 tmp = readl(mmio + HOST_CTL);
742 VPRINTK("HOST_CTL 0x%x\n", tmp);
743 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
744 tmp = readl(mmio + HOST_CTL);
745 VPRINTK("HOST_CTL 0x%x\n", tmp);
746}
747
422b7595 748static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 749{
750 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
751 struct ata_taskfile tf;
422b7595
TH		 752 u32 tmp;
753
754 tmp = readl(port_mmio + PORT_SIG);
755 tf.lbah = (tmp >> 24) & 0xff;
756 tf.lbam = (tmp >> 16) & 0xff;
757 tf.lbal = (tmp >> 8) & 0xff;
758 tf.nsect = (tmp) & 0xff;
759
760 return ata_dev_classify(&tf);
761}
762
12fad3f9
TH		 763static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
764 u32 opts)
cc9278ed 765{
12fad3f9
TH		 766 dma_addr_t cmd_tbl_dma;
767
768 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
769
770 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
771 pp->cmd_slot[tag].status = 0;
772 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
773 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 774}
775
bf2af2a2 776static int ahci_clo(struct ata_port *ap)
4658f79b 777{
bf2af2a2 778 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
cca3974e 779 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 780 u32 tmp;
781
782 if (!(hpriv->cap & HOST_CAP_CLO))
783 return -EOPNOTSUPP;
784
785 tmp = readl(port_mmio + PORT_CMD);
786 tmp |= PORT_CMD_CLO;
787 writel(tmp, port_mmio + PORT_CMD);
788
789 tmp = ata_wait_register(port_mmio + PORT_CMD,
790 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
791 if (tmp & PORT_CMD_CLO)
792 return -EIO;
793
794 return 0;
795}
796
797static int ahci_softreset(struct ata_port *ap, unsigned int *class)
798{
4658f79b 799 struct ahci_port_priv *pp = ap->private_data;
cca3974e 800 void __iomem *mmio = ap->host->mmio_base;
4658f79b
TH		 801 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
802 const u32 cmd_fis_len = 5; /* five dwords */
803 const char *reason = NULL;
804 struct ata_taskfile tf;
75fe1806 805 u32 tmp;
4658f79b
TH		 806 u8 *fis;
807 int rc;
808
809 DPRINTK("ENTER\n");
810
81952c54 811 if (ata_port_offline(ap)) {
c2a65852
TH		 812 DPRINTK("PHY reports no device\n");
813 *class = ATA_DEV_NONE;
814 return 0;
815 }
816
4658f79b 817 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 818 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 819 if (rc) {
820 reason = "failed to stop engine";
821 goto fail_restart;
822 }
823
824 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 825 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 826 rc = ahci_clo(ap);
4658f79b 827
bf2af2a2
BJ		 828 if (rc == -EOPNOTSUPP) {
829 reason = "port busy but CLO unavailable";
830 goto fail_restart;
831 } else if (rc) {
832 reason = "port busy but CLO failed";
4658f79b
TH		 833 goto fail_restart;
834 }
835 }
836
837 /* restart engine */
5457f219 838 ahci_start_engine(port_mmio);
4658f79b 839
3373efd8 840 ata_tf_init(ap->device, &tf);
4658f79b
TH		 841 fis = pp->cmd_tbl;
842
843 /* issue the first D2H Register FIS */
12fad3f9
TH		 844 ahci_fill_cmd_slot(pp, 0,
845 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 846
847 tf.ctl |= ATA_SRST;
848 ata_tf_to_fis(&tf, fis, 0);
849 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
850
851 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 852
75fe1806
TH		 853 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
854 if (tmp & 0x1) {
4658f79b
TH		 855 rc = -EIO;
856 reason = "1st FIS failed";
857 goto fail;
858 }
859
860 /* spec says at least 5us, but be generous and sleep for 1ms */
861 msleep(1);
862
863 /* issue the second D2H Register FIS */
12fad3f9 864 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 865
866 tf.ctl &= ~ATA_SRST;
867 ata_tf_to_fis(&tf, fis, 0);
868 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
869
870 writel(1, port_mmio + PORT_CMD_ISSUE);
871 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
872
873 /* spec mandates ">= 2ms" before checking status.
874 * We wait 150ms, because that was the magic delay used for
875 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
876 * between when the ATA command register is written, and then
877 * status is checked. Because waiting for "a while" before
878 * checking status is fine, post SRST, we perform this magic
879 * delay here as well.
880 */
881 msleep(150);
882
883 *class = ATA_DEV_NONE;
81952c54 884 if (ata_port_online(ap)) {
4658f79b
TH		 885 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
886 rc = -EIO;
887 reason = "device not ready";
888 goto fail;
889 }
890 *class = ahci_dev_classify(ap);
891 }
892
893 DPRINTK("EXIT, class=%u\n", *class);
894 return 0;
895
896 fail_restart:
5457f219 897 ahci_start_engine(port_mmio);
4658f79b 898 fail:
f15a1daf 899 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 900 return rc;
901}
902
2bf2cb26 903static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 904{
4296971d
TH		 905 struct ahci_port_priv *pp = ap->private_data;
906 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
907 struct ata_taskfile tf;
cca3974e 908 void __iomem *mmio = ap->host->mmio_base;
5457f219 909 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 910 int rc;
911
912 DPRINTK("ENTER\n");
1da177e4 913
5457f219 914 ahci_stop_engine(port_mmio);
4296971d
TH		 915
916 /* clear D2H reception area to properly wait for D2H FIS */
917 ata_tf_init(ap->device, &tf);
918 tf.command = 0xff;
919 ata_tf_to_fis(&tf, d2h_fis, 0);
920
2bf2cb26 921 rc = sata_std_hardreset(ap, class);
4296971d 922
5457f219 923 ahci_start_engine(port_mmio);
1da177e4 924
81952c54 925 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 926 *class = ahci_dev_classify(ap);
927 if (*class == ATA_DEV_UNKNOWN)
928 *class = ATA_DEV_NONE;
1da177e4 929
4bd00f6a
TH		 930 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
931 return rc;
932}
933
ad616ffb
TH		 934static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
935{
936 void __iomem *mmio = ap->host->mmio_base;
937 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
938 int rc;
939
940 DPRINTK("ENTER\n");
941
942 ahci_stop_engine(port_mmio);
943
944 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
945
946 /* vt8251 needs SError cleared for the port to operate */
947 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
948
949 ahci_start_engine(port_mmio);
950
951 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
952
953 /* vt8251 doesn't clear BSY on signature FIS reception,
954 * request follow-up softreset.
955 */
956 return rc ?: -EAGAIN;
957}
958
4bd00f6a
TH		 959static void ahci_postreset(struct ata_port *ap, unsigned int *class)
960{
961 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
962 u32 new_tmp, tmp;
963
964 ata_std_postreset(ap, class);
02eaa666
JG		 965
966 /* Make sure port's ATAPI bit is set appropriately */
967 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 968 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 969 new_tmp |= PORT_CMD_ATAPI;
970 else
971 new_tmp &= ~PORT_CMD_ATAPI;
972 if (new_tmp != tmp) {
973 writel(new_tmp, port_mmio + PORT_CMD);
974 readl(port_mmio + PORT_CMD); /* flush */
975 }
1da177e4
LT		 976}
977
978static u8 ahci_check_status(struct ata_port *ap)
979{
1e4f2a96 980 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 981
982 return readl(mmio + PORT_TFDATA) & 0xFF;
983}
984
1da177e4
LT		 985static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
986{
987 struct ahci_port_priv *pp = ap->private_data;
988 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
989
990 ata_tf_from_fis(d2h_fis, tf);
991}
992
12fad3f9 993static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 994{
cedc9a47
JG		 995 struct scatterlist *sg;
996 struct ahci_sg *ahci_sg;
828d09de 997 unsigned int n_sg = 0;
1da177e4
LT		 998
999 VPRINTK("ENTER\n");
1000
1001 /*
1002 * Next, the S/G list.
1003 */
12fad3f9 1004 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1005 ata_for_each_sg(sg, qc) {
1006 dma_addr_t addr = sg_dma_address(sg);
1007 u32 sg_len = sg_dma_len(sg);
1008
1009 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1010 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1011 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1012
cedc9a47 1013 ahci_sg++;
828d09de 1014 n_sg++;
1da177e4 1015 }
828d09de
JG		 1016
1017 return n_sg;
1da177e4
LT		 1018}
1019
1020static void ahci_qc_prep(struct ata_queued_cmd *qc)
1021{
a0ea7328
JG		 1022 struct ata_port *ap = qc->ap;
1023 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1024 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1025 void *cmd_tbl;
1da177e4
LT		 1026 u32 opts;
1027 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1028 unsigned int n_elem;
1da177e4 1029
1da177e4
LT		 1030 /*
1031 * Fill in command table information. First, the header,
1032 * a SATA Register - Host to Device command FIS.
1033 */
12fad3f9
TH		 1034 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1035
1036 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1037 if (is_atapi) {
12fad3f9
TH		 1038 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1039 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1040 }
1da177e4 1041
cc9278ed
TH		 1042 n_elem = 0;
1043 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1044 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1045
cc9278ed
TH		 1046 /*
1047 * Fill in command slot information.
1048 */
1049 opts = cmd_fis_len | n_elem << 16;
1050 if (qc->tf.flags & ATA_TFLAG_WRITE)
1051 opts |= AHCI_CMD_WRITE;
1052 if (is_atapi)
4b10e559 1053 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1054
12fad3f9 1055 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1056}
1057
78cd52d0 1058static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1059{
78cd52d0
TH		 1060 struct ahci_port_priv *pp = ap->private_data;
1061 struct ata_eh_info *ehi = &ap->eh_info;
1062 unsigned int err_mask = 0, action = 0;
1063 struct ata_queued_cmd *qc;
1064 u32 serror;
1da177e4 1065
78cd52d0 1066 ata_ehi_clear_desc(ehi);
1da177e4 1067
78cd52d0
TH		 1068 /* AHCI needs SError cleared; otherwise, it might lock up */
1069 serror = ahci_scr_read(ap, SCR_ERROR);
1070 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1071
78cd52d0
TH		 1072 /* analyze @irq_stat */
1073 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1074
41669553
TH		 1075 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1076 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1077 irq_stat &= ~PORT_IRQ_IF_ERR;
1078
78cd52d0
TH		 1079 if (irq_stat & PORT_IRQ_TF_ERR)
1080 err_mask |= AC_ERR_DEV;
1081
1082 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1083 err_mask |= AC_ERR_HOST_BUS;
1084 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1085 }
1086
78cd52d0
TH		 1087 if (irq_stat & PORT_IRQ_IF_ERR) {
1088 err_mask |= AC_ERR_ATA_BUS;
1089 action |= ATA_EH_SOFTRESET;
1090 ata_ehi_push_desc(ehi, ", interface fatal error");
1091 }
1da177e4 1092
78cd52d0 1093 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1094 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1095 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1096 "connection status changed" : "PHY RDY changed");
1097 }
1098
1099 if (irq_stat & PORT_IRQ_UNK_FIS) {
1100 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1101
78cd52d0
TH		 1102 err_mask |= AC_ERR_HSM;
1103 action |= ATA_EH_SOFTRESET;
1104 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1105 unk[0], unk[1], unk[2], unk[3]);
1106 }
1da177e4 1107
78cd52d0
TH		 1108 /* okay, let's hand over to EH */
1109 ehi->serror |= serror;
1110 ehi->action |= action;
b8f6153e 1111
1da177e4 1112 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1113 if (qc)
1114 qc->err_mask |= err_mask;
1115 else
1116 ehi->err_mask |= err_mask;
a72ec4ce 1117
78cd52d0
TH		 1118 if (irq_stat & PORT_IRQ_FREEZE)
1119 ata_port_freeze(ap);
1120 else
1121 ata_port_abort(ap);
1da177e4
LT		 1122}
1123
78cd52d0 1124static void ahci_host_intr(struct ata_port *ap)
1da177e4 1125{
cca3974e 1126 void __iomem *mmio = ap->host->mmio_base;
ea6ba10b 1127 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 1128 struct ata_eh_info *ehi = &ap->eh_info;
1129 u32 status, qc_active;
1130 int rc;
1da177e4
LT		 1131
1132 status = readl(port_mmio + PORT_IRQ_STAT);
1133 writel(status, port_mmio + PORT_IRQ_STAT);
1134
78cd52d0
TH		 1135 if (unlikely(status & PORT_IRQ_ERROR)) {
1136 ahci_error_intr(ap, status);
1137 return;
1da177e4
LT		 1138 }
1139
12fad3f9
TH		 1140 if (ap->sactive)
1141 qc_active = readl(port_mmio + PORT_SCR_ACT);
1142 else
1143 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1144
1145 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1146 if (rc > 0)
1147 return;
1148 if (rc < 0) {
1149 ehi->err_mask |= AC_ERR_HSM;
1150 ehi->action |= ATA_EH_SOFTRESET;
1151 ata_port_freeze(ap);
1152 return;
1da177e4
LT		 1153 }
1154
2a3917a8
TH		 1155 /* hmmm... a spurious interupt */
1156
12fad3f9 1157 /* some devices send D2H reg with I bit set during NCQ command phase */
12a87d36 1158 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
12fad3f9
TH		 1159 return;
1160
2a3917a8 1161 /* ignore interim PIO setup fis interrupts */
9bec2e38 1162 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
f1d39b29 1163 return;
2a3917a8 1164
78cd52d0
TH		 1165 if (ata_ratelimit())
1166 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 1167 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1168 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1169}
1170
1171static void ahci_irq_clear(struct ata_port *ap)
1172{
1173 /* TODO */
1174}
1175
7d12e780 1176static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1177{
cca3974e 1178 struct ata_host *host = dev_instance;
1da177e4
LT		 1179 struct ahci_host_priv *hpriv;
1180 unsigned int i, handled = 0;
ea6ba10b 1181 void __iomem *mmio;
1da177e4
LT		 1182 u32 irq_stat, irq_ack = 0;
1183
1184 VPRINTK("ENTER\n");
1185
cca3974e
JG		 1186 hpriv = host->private_data;
1187 mmio = host->mmio_base;
1da177e4
LT		 1188
1189 /* sigh. 0xffffffff is a valid return from h/w */
1190 irq_stat = readl(mmio + HOST_IRQ_STAT);
1191 irq_stat &= hpriv->port_map;
1192 if (!irq_stat)
1193 return IRQ_NONE;
1194
cca3974e 1195 spin_lock(&host->lock);
1da177e4 1196
cca3974e 1197 for (i = 0; i < host->n_ports; i++) {
1da177e4 1198 struct ata_port *ap;
1da177e4 1199
67846b30
JG		 1200 if (!(irq_stat & (1 << i)))
1201 continue;
1202
cca3974e 1203 ap = host->ports[i];
67846b30 1204 if (ap) {
78cd52d0 1205 ahci_host_intr(ap);
67846b30
JG		 1206 VPRINTK("port %u\n", i);
1207 } else {
1208 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1209 if (ata_ratelimit())
cca3974e 1210 dev_printk(KERN_WARNING, host->dev,
a9524a76 1211 "interrupt on disabled port %u\n", i);
1da177e4 1212 }
67846b30
JG		 1213
1214 irq_ack |= (1 << i);
1da177e4
LT		 1215 }
1216
1217 if (irq_ack) {
1218 writel(irq_ack, mmio + HOST_IRQ_STAT);
1219 handled = 1;
1220 }
1221
cca3974e 1222 spin_unlock(&host->lock);
1da177e4
LT		 1223
1224 VPRINTK("EXIT\n");
1225
1226 return IRQ_RETVAL(handled);
1227}
1228
9a3d9eb0 1229static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1230{
1231 struct ata_port *ap = qc->ap;
ea6ba10b 1232 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 1233
12fad3f9
TH		 1234 if (qc->tf.protocol == ATA_PROT_NCQ)
1235 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1236 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1237 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1238
1239 return 0;
1240}
1241
78cd52d0
TH		 1242static void ahci_freeze(struct ata_port *ap)
1243{
cca3974e 1244 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1245 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1246
1247 /* turn IRQ off */
1248 writel(0, port_mmio + PORT_IRQ_MASK);
1249}
1250
1251static void ahci_thaw(struct ata_port *ap)
1252{
cca3974e 1253 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1254 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1255 u32 tmp;
1256
1257 /* clear IRQ */
1258 tmp = readl(port_mmio + PORT_IRQ_STAT);
1259 writel(tmp, port_mmio + PORT_IRQ_STAT);
1260 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1261
1262 /* turn IRQ back on */
1263 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1264}
1265
1266static void ahci_error_handler(struct ata_port *ap)
1267{
cca3974e 1268 void __iomem *mmio = ap->host->mmio_base;
5457f219 1269 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1270
b51e9e5d 1271 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1272 /* restart engine */
5457f219 1273 ahci_stop_engine(port_mmio);
1274 ahci_start_engine(port_mmio);
78cd52d0
TH		 1275 }
1276
1277 /* perform recovery */
4aeb0e32 1278 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1279 ahci_postreset);
78cd52d0
TH		 1280}
1281
ad616ffb
TH		 1282static void ahci_vt8251_error_handler(struct ata_port *ap)
1283{
1284 void __iomem *mmio = ap->host->mmio_base;
1285 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1286
1287 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1288 /* restart engine */
1289 ahci_stop_engine(port_mmio);
1290 ahci_start_engine(port_mmio);
1291 }
1292
1293 /* perform recovery */
1294 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1295 ahci_postreset);
1296}
1297
78cd52d0
TH		 1298static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1299{
1300 struct ata_port *ap = qc->ap;
cca3974e 1301 void __iomem *mmio = ap->host->mmio_base;
5457f219 1302 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 1303
1304 if (qc->flags & ATA_QCFLAG_FAILED)
1305 qc->err_mask |= AC_ERR_OTHER;
1306
1307 if (qc->err_mask) {
1308 /* make DMA engine forget about the failed command */
5457f219 1309 ahci_stop_engine(port_mmio);
1310 ahci_start_engine(port_mmio);
78cd52d0
TH		 1311 }
1312}
1313
c1332875
TH		 1314static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1315{
cca3974e 1316 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1317 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1318 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1319 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1320 const char *emsg = NULL;
1321 int rc;
1322
1323 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1324 if (rc) {
1325 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1326 ahci_init_port(port_mmio, hpriv->cap,
1327 pp->cmd_slot_dma, pp->rx_fis_dma);
1328 }
1329
1330 return rc;
1331}
1332
1333static int ahci_port_resume(struct ata_port *ap)
1334{
1335 struct ahci_port_priv *pp = ap->private_data;
cca3974e
JG		 1336 struct ahci_host_priv *hpriv = ap->host->private_data;
1337 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1338 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1339
1340 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1341
1342 return 0;
1343}
1344
1345static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1346{
cca3974e
JG		 1347 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1348 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1349 u32 ctl;
1350
1351 if (mesg.event == PM_EVENT_SUSPEND) {
1352 /* AHCI spec rev1.1 section 8.3.3:
1353 * Software must disable interrupts prior to requesting a
1354 * transition of the HBA to D3 state.
1355 */
1356 ctl = readl(mmio + HOST_CTL);
1357 ctl &= ~HOST_IRQ_EN;
1358 writel(ctl, mmio + HOST_CTL);
1359 readl(mmio + HOST_CTL); /* flush */
1360 }
1361
1362 return ata_pci_device_suspend(pdev, mesg);
1363}
1364
1365static int ahci_pci_device_resume(struct pci_dev *pdev)
1366{
cca3974e
JG		 1367 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1368 struct ahci_host_priv *hpriv = host->private_data;
1369 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1370 int rc;
1371
1372 ata_pci_device_do_resume(pdev);
1373
1374 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1375 rc = ahci_reset_controller(mmio, pdev);
1376 if (rc)
1377 return rc;
1378
648a88be
TH		 1379 ahci_init_controller(mmio, pdev, host->n_ports,
1380 host->ports[0]->flags, hpriv);
c1332875
TH		 1381 }
1382
cca3974e 1383 ata_host_resume(host);
c1332875
TH		 1384
1385 return 0;
1386}
1387
254950cd
TH		 1388static int ahci_port_start(struct ata_port *ap)
1389{
cca3974e
JG		 1390 struct device *dev = ap->host->dev;
1391 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1392 struct ahci_port_priv *pp;
cca3974e 1393 void __iomem *mmio = ap->host->mmio_base;
254950cd
TH		 1394 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1395 void *mem;
1396 dma_addr_t mem_dma;
1397 int rc;
1398
1399 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1400 if (!pp)
1401 return -ENOMEM;
1402 memset(pp, 0, sizeof(*pp));
1403
1404 rc = ata_pad_alloc(ap, dev);
1405 if (rc) {
1406 kfree(pp);
1407 return rc;
1408 }
1409
1410 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1411 if (!mem) {
1412 ata_pad_free(ap, dev);
1413 kfree(pp);
1414 return -ENOMEM;
1415 }
1416 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1417
1418 /*
1419 * First item in chunk of DMA memory: 32-slot command table,
1420 * 32 bytes each in size
1421 */
1422 pp->cmd_slot = mem;
1423 pp->cmd_slot_dma = mem_dma;
1424
1425 mem += AHCI_CMD_SLOT_SZ;
1426 mem_dma += AHCI_CMD_SLOT_SZ;
1427
1428 /*
1429 * Second item: Received-FIS area
1430 */
1431 pp->rx_fis = mem;
1432 pp->rx_fis_dma = mem_dma;
1433
1434 mem += AHCI_RX_FIS_SZ;
1435 mem_dma += AHCI_RX_FIS_SZ;
1436
1437 /*
1438 * Third item: data area for storing a single command
1439 * and its scatter-gather table
1440 */
1441 pp->cmd_tbl = mem;
1442 pp->cmd_tbl_dma = mem_dma;
1443
1444 ap->private_data = pp;
1445
0be0aa98
TH		 1446 /* initialize port */
1447 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1448
1449 return 0;
1450}
1451
1452static void ahci_port_stop(struct ata_port *ap)
1453{
cca3974e
JG		 1454 struct device *dev = ap->host->dev;
1455 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1456 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1457 void __iomem *mmio = ap->host->mmio_base;
254950cd 1458 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1459 const char *emsg = NULL;
1460 int rc;
254950cd 1461
0be0aa98
TH		 1462 /* de-initialize port */
1463 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1464 if (rc)
1465 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1466
1467 ap->private_data = NULL;
1468 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1469 pp->cmd_slot, pp->cmd_slot_dma);
1470 ata_pad_free(ap, dev);
1471 kfree(pp);
1472}
1473
1da177e4
LT		 1474static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1475 unsigned int port_idx)
1476{
1477 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1478 base = ahci_port_base_ul(base, port_idx);
1479 VPRINTK("base now==0x%lx\n", base);
1480
1481 port->cmd_addr = base;
1482 port->scr_addr = base + PORT_SCR;
1483
1484 VPRINTK("EXIT\n");
1485}
1486
1487static int ahci_host_init(struct ata_probe_ent *probe_ent)
1488{
1489 struct ahci_host_priv *hpriv = probe_ent->private_data;
1490 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1491 void __iomem *mmio = probe_ent->mmio_base;
648a88be 1492 unsigned int i, cap_n_ports, using_dac;
1da177e4 1493 int rc;
1da177e4 1494
d91542c1
TH		 1495 rc = ahci_reset_controller(mmio, pdev);
1496 if (rc)
1497 return rc;
1da177e4
LT		 1498
1499 hpriv->cap = readl(mmio + HOST_CAP);
1500 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
648a88be 1501 cap_n_ports = ahci_nr_ports(hpriv->cap);
1da177e4
LT		 1502
1503 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
648a88be
TH		 1504 hpriv->cap, hpriv->port_map, cap_n_ports);
1505
1506 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1507 unsigned int n_ports = cap_n_ports;
1508 u32 port_map = hpriv->port_map;
1509 int max_port = 0;
1510
1511 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1512 if (port_map & (1 << i)) {
1513 n_ports--;
1514 port_map &= ~(1 << i);
1515 max_port = i;
1516 } else
1517 probe_ent->dummy_port_mask |= 1 << i;
1518 }
1519
1520 if (n_ports || port_map)
1521 dev_printk(KERN_WARNING, &pdev->dev,
1522 "nr_ports (%u) and implemented port map "
1523 "(0x%x) don't match\n",
1524 cap_n_ports, hpriv->port_map);
1525
1526 probe_ent->n_ports = max_port + 1;
1527 } else
1528 probe_ent->n_ports = cap_n_ports;
1da177e4
LT		 1529
1530 using_dac = hpriv->cap & HOST_CAP_64;
1531 if (using_dac &&
1532 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1533 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1534 if (rc) {
1535 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1536 if (rc) {
a9524a76
JG		 1537 dev_printk(KERN_ERR, &pdev->dev,
1538 "64-bit DMA enable failed\n");
1da177e4
LT		 1539 return rc;
1540 }
1541 }
1da177e4
LT		 1542 } else {
1543 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1544 if (rc) {
a9524a76
JG		 1545 dev_printk(KERN_ERR, &pdev->dev,
1546 "32-bit DMA enable failed\n");
1da177e4
LT		 1547 return rc;
1548 }
1549 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1550 if (rc) {
a9524a76
JG		 1551 dev_printk(KERN_ERR, &pdev->dev,
1552 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1553 return rc;
1554 }
1555 }
1556
d91542c1
TH		 1557 for (i = 0; i < probe_ent->n_ports; i++)
1558 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1da177e4 1559
648a88be
TH		 1560 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1561 probe_ent->port_flags, hpriv);
1da177e4
LT		 1562
1563 pci_set_master(pdev);
1564
1565 return 0;
1566}
1567
1da177e4
LT		 1568static void ahci_print_info(struct ata_probe_ent *probe_ent)
1569{
1570 struct ahci_host_priv *hpriv = probe_ent->private_data;
1571 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1572 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1573 u32 vers, cap, impl, speed;
1574 const char *speed_s;
1575 u16 cc;
1576 const char *scc_s;
1577
1578 vers = readl(mmio + HOST_VERSION);
1579 cap = hpriv->cap;
1580 impl = hpriv->port_map;
1581
1582 speed = (cap >> 20) & 0xf;
1583 if (speed == 1)
1584 speed_s = "1.5";
1585 else if (speed == 2)
1586 speed_s = "3";
1587 else
1588 speed_s = "?";
1589
1590 pci_read_config_word(pdev, 0x0a, &cc);
1591 if (cc == 0x0101)
1592 scc_s = "IDE";
1593 else if (cc == 0x0106)
1594 scc_s = "SATA";
1595 else if (cc == 0x0104)
1596 scc_s = "RAID";
1597 else
1598 scc_s = "unknown";
1599
a9524a76
JG		 1600 dev_printk(KERN_INFO, &pdev->dev,
1601 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1602 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1603 ,
1da177e4
LT		 1604
1605 (vers >> 24) & 0xff,
1606 (vers >> 16) & 0xff,
1607 (vers >> 8) & 0xff,
1608 vers & 0xff,
1609
1610 ((cap >> 8) & 0x1f) + 1,
1611 (cap & 0x1f) + 1,
1612 speed_s,
1613 impl,
1614 scc_s);
1615
a9524a76
JG		 1616 dev_printk(KERN_INFO, &pdev->dev,
1617 "flags: "
1da177e4
LT		 1618 "%s%s%s%s%s%s"
1619 "%s%s%s%s%s%s%s\n"
1620 ,
1da177e4
LT		 1621
1622 cap & (1 << 31) ? "64bit " : "",
1623 cap & (1 << 30) ? "ncq " : "",
1624 cap & (1 << 28) ? "ilck " : "",
1625 cap & (1 << 27) ? "stag " : "",
1626 cap & (1 << 26) ? "pm " : "",
1627 cap & (1 << 25) ? "led " : "",
1628
1629 cap & (1 << 24) ? "clo " : "",
1630 cap & (1 << 19) ? "nz " : "",
1631 cap & (1 << 18) ? "only " : "",
1632 cap & (1 << 17) ? "pmp " : "",
1633 cap & (1 << 15) ? "pio " : "",
1634 cap & (1 << 14) ? "slum " : "",
1635 cap & (1 << 13) ? "part " : ""
1636 );
1637}
1638
1639static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1640{
1641 static int printed_version;
1642 struct ata_probe_ent *probe_ent = NULL;
1643 struct ahci_host_priv *hpriv;
1644 unsigned long base;
ea6ba10b 1645 void __iomem *mmio_base;
1da177e4 1646 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1647 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1648 int rc;
1649
1650 VPRINTK("ENTER\n");
1651
12fad3f9
TH		 1652 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1653
1da177e4 1654 if (!printed_version++)
a9524a76 1655 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1656
9545b578 1657 /* JMicron-specific fixup: make sure we're in AHCI mode */
1658 /* This is protected from races with ata_jmicron by the pci probe
1659 locking */
1660 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1661 /* AHCI enable, AHCI on function 0 */
1662 pci_write_config_byte(pdev, 0x41, 0xa1);
1663 /* Function 1 is the PATA controller */
1664 if (PCI_FUNC(pdev->devfn))
1665 return -ENODEV;
1666 }
1667
1da177e4
LT		 1668 rc = pci_enable_device(pdev);
1669 if (rc)
1670 return rc;
1671
1672 rc = pci_request_regions(pdev, DRV_NAME);
1673 if (rc) {
1674 pci_dev_busy = 1;
1675 goto err_out;
1676 }
1677
907f4678
JG		 1678 if (pci_enable_msi(pdev) == 0)
1679 have_msi = 1;
1680 else {
1681 pci_intx(pdev, 1);
1682 have_msi = 0;
1683 }
1da177e4
LT		 1684
1685 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1686 if (probe_ent == NULL) {
1687 rc = -ENOMEM;
907f4678 1688 goto err_out_msi;
1da177e4
LT		 1689 }
1690
1691 memset(probe_ent, 0, sizeof(*probe_ent));
1692 probe_ent->dev = pci_dev_to_dev(pdev);
1693 INIT_LIST_HEAD(&probe_ent->node);
1694
374b1873 1695 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1696 if (mmio_base == NULL) {
1697 rc = -ENOMEM;
1698 goto err_out_free_ent;
1699 }
1700 base = (unsigned long) mmio_base;
1701
1702 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1703 if (!hpriv) {
1704 rc = -ENOMEM;
1705 goto err_out_iounmap;
1706 }
1707 memset(hpriv, 0, sizeof(*hpriv));
1708
1709 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1710 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1711 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1712 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1713 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1714
1715 probe_ent->irq = pdev->irq;
1d6f359a 1716 probe_ent->irq_flags = IRQF_SHARED;
1da177e4
LT		 1717 probe_ent->mmio_base = mmio_base;
1718 probe_ent->private_data = hpriv;
1719
4b0060f4
JG		 1720 if (have_msi)
1721 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1722
1da177e4
LT		 1723 /* initialize adapter */
1724 rc = ahci_host_init(probe_ent);
1725 if (rc)
1726 goto err_out_hpriv;
1727
cca3974e 1728 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1729 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1730 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1731
1da177e4
LT		 1732 ahci_print_info(probe_ent);
1733
1734 /* FIXME: check ata_device_add return value */
1735 ata_device_add(probe_ent);
1736 kfree(probe_ent);
1737
1738 return 0;
1739
1740err_out_hpriv:
1741 kfree(hpriv);
1742err_out_iounmap:
374b1873 1743 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1744err_out_free_ent:
1745 kfree(probe_ent);
907f4678
JG		 1746err_out_msi:
1747 if (have_msi)
1748 pci_disable_msi(pdev);
1749 else
1750 pci_intx(pdev, 0);
1da177e4
LT		 1751 pci_release_regions(pdev);
1752err_out:
1753 if (!pci_dev_busy)
1754 pci_disable_device(pdev);
1755 return rc;
1756}
1757
907f4678
JG		 1758static void ahci_remove_one (struct pci_dev *pdev)
1759{
1760 struct device *dev = pci_dev_to_dev(pdev);
cca3974e
JG		 1761 struct ata_host *host = dev_get_drvdata(dev);
1762 struct ahci_host_priv *hpriv = host->private_data;
907f4678
JG		 1763 unsigned int i;
1764 int have_msi;
1765
cca3974e
JG		 1766 for (i = 0; i < host->n_ports; i++)
1767 ata_port_detach(host->ports[i]);
907f4678 1768
4b0060f4 1769 have_msi = hpriv->flags & AHCI_FLAG_MSI;
cca3974e 1770 free_irq(host->irq, host);
907f4678 1771
cca3974e
JG		 1772 for (i = 0; i < host->n_ports; i++) {
1773 struct ata_port *ap = host->ports[i];
907f4678 1774
cca3974e
JG		 1775 ata_scsi_release(ap->scsi_host);
1776 scsi_host_put(ap->scsi_host);
907f4678
JG		 1777 }
1778
e005f01d 1779 kfree(hpriv);
cca3974e
JG		 1780 pci_iounmap(pdev, host->mmio_base);
1781 kfree(host);
ead5de99 1782
907f4678
JG		 1783 if (have_msi)
1784 pci_disable_msi(pdev);
1785 else
1786 pci_intx(pdev, 0);
1787 pci_release_regions(pdev);
907f4678
JG		 1788 pci_disable_device(pdev);
1789 dev_set_drvdata(dev, NULL);
1790}
1da177e4
LT		 1791
1792static int __init ahci_init(void)
1793{
b7887196 1794 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1795}
1796
1da177e4
LT		 1797static void __exit ahci_exit(void)
1798{
1799 pci_unregister_driver(&ahci_pci_driver);
1800}
1801
1802
1803MODULE_AUTHOR("Jeff Garzik");
1804MODULE_DESCRIPTION("AHCI SATA low-level driver");
1805MODULE_LICENSE("GPL");
1806MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1807MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1808
1809module_init(ahci_init);
1810module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)