Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "ahci" | |
8bc3fc47 | 49 | #define DRV_VERSION "2.2" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | AHCI_PCI_BAR = 5, | |
648a88be | 54 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
56 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
be5d8218 | 57 | AHCI_USE_CLUSTERING = 1, |
12fad3f9 | 58 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 59 | AHCI_CMD_SZ = 32, |
12fad3f9 | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 61 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
67 | AHCI_RX_FIS_SZ, |
68 | AHCI_IRQ_ON_SG = (1 << 31), | |
69 | AHCI_CMD_ATAPI = (1 << 5), | |
70 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
72 | AHCI_CMD_RESET = (1 << 8), |
73 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
74 | |
75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
648a88be TH |
80 | board_ahci_pi = 1, |
81 | board_ahci_vt8251 = 2, | |
82 | board_ahci_ign_iferr = 3, | |
55a61604 | 83 | board_ahci_sb600 = 4, |
1da177e4 LT |
84 | |
85 | /* global controller registers */ | |
86 | HOST_CAP = 0x00, /* host capabilities */ | |
87 | HOST_CTL = 0x04, /* global host control */ | |
88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
91 | ||
92 | /* HOST_CTL bits */ | |
93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
96 | ||
97 | /* HOST_CAP bits */ | |
0be0aa98 | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 99 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 100 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
979db803 | 101 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 102 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
103 | |
104 | /* registers for each SATA port */ | |
105 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
106 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
107 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
108 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
109 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
110 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
111 | PORT_CMD = 0x18, /* port command */ | |
112 | PORT_TFDATA = 0x20, /* taskfile data */ | |
113 | PORT_SIG = 0x24, /* device TF signature */ | |
114 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
115 | PORT_SCR = 0x28, /* SATA phy register block */ | |
116 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
117 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
118 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
119 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
120 | ||
121 | /* PORT_IRQ_{STAT,MASK} bits */ | |
122 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
123 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
124 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
125 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
126 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
127 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
128 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
129 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
130 | ||
131 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
132 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
133 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
134 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
135 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
136 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
137 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
138 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
139 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
140 | ||
78cd52d0 TH |
141 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
142 | PORT_IRQ_IF_ERR | | |
143 | PORT_IRQ_CONNECT | | |
4296971d | 144 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
145 | PORT_IRQ_UNK_FIS, |
146 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
147 | PORT_IRQ_TF_ERR | | |
148 | PORT_IRQ_HBUS_DATA_ERR, | |
149 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
150 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
151 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
152 | |
153 | /* PORT_CMD bits */ | |
02eaa666 | 154 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
155 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
156 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
157 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 158 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
159 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
160 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
161 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
162 | ||
0be0aa98 | 163 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
164 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
165 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
166 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 167 | |
bf2af2a2 | 168 | /* ap->flags bits */ |
4aeb0e32 TH |
169 | AHCI_FLAG_NO_NCQ = (1 << 24), |
170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | |
648a88be | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
55a61604 | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
c7a42156 | 173 | AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */ |
1188c0d8 TH |
174 | |
175 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
176 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
3cadbcc0 TH |
177 | ATA_FLAG_SKIP_D2H_BSY | |
178 | ATA_FLAG_ACPI_SATA, | |
1da177e4 LT |
179 | }; |
180 | ||
181 | struct ahci_cmd_hdr { | |
182 | u32 opts; | |
183 | u32 status; | |
184 | u32 tbl_addr; | |
185 | u32 tbl_addr_hi; | |
186 | u32 reserved[4]; | |
187 | }; | |
188 | ||
189 | struct ahci_sg { | |
190 | u32 addr; | |
191 | u32 addr_hi; | |
192 | u32 reserved; | |
193 | u32 flags_size; | |
194 | }; | |
195 | ||
196 | struct ahci_host_priv { | |
d447df14 TH |
197 | u32 cap; /* cap to use */ |
198 | u32 port_map; /* port map to use */ | |
199 | u32 saved_cap; /* saved initial cap */ | |
200 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
201 | }; |
202 | ||
203 | struct ahci_port_priv { | |
204 | struct ahci_cmd_hdr *cmd_slot; | |
205 | dma_addr_t cmd_slot_dma; | |
206 | void *cmd_tbl; | |
207 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
208 | void *rx_fis; |
209 | dma_addr_t rx_fis_dma; | |
0291f95f | 210 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
211 | unsigned int ncq_saw_d2h:1; |
212 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 213 | unsigned int ncq_saw_sdb:1; |
1da177e4 LT |
214 | }; |
215 | ||
216 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
217 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
218 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 219 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 220 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
221 | static int ahci_port_start(struct ata_port *ap); |
222 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
223 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
224 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
225 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
226 | static void ahci_freeze(struct ata_port *ap); |
227 | static void ahci_thaw(struct ata_port *ap); | |
228 | static void ahci_error_handler(struct ata_port *ap); | |
ad616ffb | 229 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 230 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
df69c9c5 | 231 | static int ahci_port_resume(struct ata_port *ap); |
dab632e8 JG |
232 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
233 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
234 | u32 opts); | |
438ac6d5 | 235 | #ifdef CONFIG_PM |
c1332875 | 236 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
237 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
238 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 239 | #endif |
1da177e4 | 240 | |
193515d5 | 241 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
242 | .module = THIS_MODULE, |
243 | .name = DRV_NAME, | |
244 | .ioctl = ata_scsi_ioctl, | |
245 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
246 | .change_queue_depth = ata_scsi_change_queue_depth, |
247 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
248 | .this_id = ATA_SHT_THIS_ID, |
249 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
250 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
251 | .emulated = ATA_SHT_EMULATED, | |
252 | .use_clustering = AHCI_USE_CLUSTERING, | |
253 | .proc_name = DRV_NAME, | |
254 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
255 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 256 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 257 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
258 | }; |
259 | ||
057ace5e | 260 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
261 | .port_disable = ata_port_disable, |
262 | ||
263 | .check_status = ahci_check_status, | |
264 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
265 | .dev_select = ata_noop_dev_select, |
266 | ||
267 | .tf_read = ahci_tf_read, | |
268 | ||
1da177e4 LT |
269 | .qc_prep = ahci_qc_prep, |
270 | .qc_issue = ahci_qc_issue, | |
271 | ||
1da177e4 | 272 | .irq_clear = ahci_irq_clear, |
246ce3b6 AI |
273 | .irq_on = ata_dummy_irq_on, |
274 | .irq_ack = ata_dummy_irq_ack, | |
1da177e4 LT |
275 | |
276 | .scr_read = ahci_scr_read, | |
277 | .scr_write = ahci_scr_write, | |
278 | ||
78cd52d0 TH |
279 | .freeze = ahci_freeze, |
280 | .thaw = ahci_thaw, | |
281 | ||
282 | .error_handler = ahci_error_handler, | |
283 | .post_internal_cmd = ahci_post_internal_cmd, | |
284 | ||
438ac6d5 | 285 | #ifdef CONFIG_PM |
c1332875 TH |
286 | .port_suspend = ahci_port_suspend, |
287 | .port_resume = ahci_port_resume, | |
438ac6d5 | 288 | #endif |
c1332875 | 289 | |
1da177e4 LT |
290 | .port_start = ahci_port_start, |
291 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
292 | }; |
293 | ||
ad616ffb TH |
294 | static const struct ata_port_operations ahci_vt8251_ops = { |
295 | .port_disable = ata_port_disable, | |
296 | ||
297 | .check_status = ahci_check_status, | |
298 | .check_altstatus = ahci_check_status, | |
299 | .dev_select = ata_noop_dev_select, | |
300 | ||
301 | .tf_read = ahci_tf_read, | |
302 | ||
303 | .qc_prep = ahci_qc_prep, | |
304 | .qc_issue = ahci_qc_issue, | |
305 | ||
ad616ffb | 306 | .irq_clear = ahci_irq_clear, |
246ce3b6 AI |
307 | .irq_on = ata_dummy_irq_on, |
308 | .irq_ack = ata_dummy_irq_ack, | |
ad616ffb TH |
309 | |
310 | .scr_read = ahci_scr_read, | |
311 | .scr_write = ahci_scr_write, | |
312 | ||
313 | .freeze = ahci_freeze, | |
314 | .thaw = ahci_thaw, | |
315 | ||
316 | .error_handler = ahci_vt8251_error_handler, | |
317 | .post_internal_cmd = ahci_post_internal_cmd, | |
318 | ||
438ac6d5 | 319 | #ifdef CONFIG_PM |
ad616ffb TH |
320 | .port_suspend = ahci_port_suspend, |
321 | .port_resume = ahci_port_resume, | |
438ac6d5 | 322 | #endif |
ad616ffb TH |
323 | |
324 | .port_start = ahci_port_start, | |
325 | .port_stop = ahci_port_stop, | |
326 | }; | |
327 | ||
98ac62de | 328 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
329 | /* board_ahci */ |
330 | { | |
1188c0d8 | 331 | .flags = AHCI_FLAG_COMMON, |
7da79312 | 332 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 333 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
334 | .port_ops = &ahci_ops, |
335 | }, | |
648a88be TH |
336 | /* board_ahci_pi */ |
337 | { | |
1188c0d8 | 338 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
648a88be | 339 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 340 | .udma_mask = ATA_UDMA6, |
648a88be TH |
341 | .port_ops = &ahci_ops, |
342 | }, | |
bf2af2a2 BJ |
343 | /* board_ahci_vt8251 */ |
344 | { | |
1188c0d8 TH |
345 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
346 | AHCI_FLAG_NO_NCQ, | |
bf2af2a2 | 347 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 348 | .udma_mask = ATA_UDMA6, |
ad616ffb | 349 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 350 | }, |
41669553 TH |
351 | /* board_ahci_ign_iferr */ |
352 | { | |
1188c0d8 | 353 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
41669553 | 354 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 355 | .udma_mask = ATA_UDMA6, |
41669553 TH |
356 | .port_ops = &ahci_ops, |
357 | }, | |
55a61604 CH |
358 | /* board_ahci_sb600 */ |
359 | { | |
1188c0d8 | 360 | .flags = AHCI_FLAG_COMMON | |
c7a42156 TH |
361 | AHCI_FLAG_IGN_SERR_INTERNAL | |
362 | AHCI_FLAG_32BIT_ONLY, | |
55a61604 | 363 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 364 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
365 | .port_ops = &ahci_ops, |
366 | }, | |
1da177e4 LT |
367 | }; |
368 | ||
3b7d697d | 369 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 370 | /* Intel */ |
54bb3a94 JG |
371 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
372 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
373 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
374 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
375 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 376 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
377 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
378 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
379 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
380 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
648a88be TH |
381 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
382 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ | |
383 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ | |
384 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ | |
385 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ | |
386 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ | |
387 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ | |
388 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ | |
389 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ | |
390 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ | |
391 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ | |
392 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ | |
393 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ | |
8af12cdb | 394 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
648a88be TH |
395 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
396 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ | |
397 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ | |
fe7fa31a | 398 | |
e34bb370 TH |
399 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
400 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
401 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
402 | |
403 | /* ATI */ | |
c65ec1c2 | 404 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
2bcfdde6 | 405 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */ |
fe7fa31a JG |
406 | |
407 | /* VIA */ | |
54bb3a94 | 408 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 409 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
410 | |
411 | /* NVIDIA */ | |
54bb3a94 JG |
412 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
413 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
414 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
415 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
416 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
417 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
418 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
419 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
420 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
421 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
422 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
423 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
424 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
425 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
426 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
427 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
428 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
429 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
430 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
431 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
432 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
433 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
435 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
443 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
fe7fa31a | 456 | |
95916edd | 457 | /* SiS */ |
54bb3a94 JG |
458 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
459 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
460 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 461 | |
415ae2b5 JG |
462 | /* Generic, PCI class code for AHCI */ |
463 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 464 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 465 | |
1da177e4 LT |
466 | { } /* terminate list */ |
467 | }; | |
468 | ||
469 | ||
470 | static struct pci_driver ahci_pci_driver = { | |
471 | .name = DRV_NAME, | |
472 | .id_table = ahci_pci_tbl, | |
473 | .probe = ahci_init_one, | |
24dc5f33 | 474 | .remove = ata_pci_remove_one, |
438ac6d5 | 475 | #ifdef CONFIG_PM |
c1332875 TH |
476 | .suspend = ahci_pci_device_suspend, |
477 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 478 | #endif |
1da177e4 LT |
479 | }; |
480 | ||
481 | ||
98fa4b60 TH |
482 | static inline int ahci_nr_ports(u32 cap) |
483 | { | |
484 | return (cap & 0x1f) + 1; | |
485 | } | |
486 | ||
dab632e8 JG |
487 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
488 | unsigned int port_no) | |
1da177e4 | 489 | { |
dab632e8 | 490 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 491 | |
dab632e8 JG |
492 | return mmio + 0x100 + (port_no * 0x80); |
493 | } | |
494 | ||
495 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
496 | { | |
497 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
498 | } |
499 | ||
d447df14 TH |
500 | /** |
501 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 TH |
502 | * @pdev: target PCI device |
503 | * @pi: associated ATA port info | |
504 | * @hpriv: host private area to store config values | |
d447df14 TH |
505 | * |
506 | * Some registers containing configuration info might be setup by | |
507 | * BIOS and might be cleared on reset. This function saves the | |
508 | * initial values of those registers into @hpriv such that they | |
509 | * can be restored after controller reset. | |
510 | * | |
511 | * If inconsistent, config values are fixed up by this function. | |
512 | * | |
513 | * LOCKING: | |
514 | * None. | |
515 | */ | |
4447d351 TH |
516 | static void ahci_save_initial_config(struct pci_dev *pdev, |
517 | const struct ata_port_info *pi, | |
518 | struct ahci_host_priv *hpriv) | |
d447df14 | 519 | { |
4447d351 | 520 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 521 | u32 cap, port_map; |
17199b18 | 522 | int i; |
d447df14 TH |
523 | |
524 | /* Values prefixed with saved_ are written back to host after | |
525 | * reset. Values without are used for driver operation. | |
526 | */ | |
527 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
528 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
529 | ||
c7a42156 TH |
530 | /* some chips lie about 64bit support */ |
531 | if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) { | |
532 | dev_printk(KERN_INFO, &pdev->dev, | |
533 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
534 | cap &= ~HOST_CAP_64; | |
535 | } | |
536 | ||
d447df14 TH |
537 | /* fixup zero port_map */ |
538 | if (!port_map) { | |
a3d2cc5e | 539 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
4447d351 | 540 | dev_printk(KERN_WARNING, &pdev->dev, |
d447df14 TH |
541 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); |
542 | ||
543 | /* write the fixed up value to the PI register */ | |
544 | hpriv->saved_port_map = port_map; | |
545 | } | |
546 | ||
17199b18 | 547 | /* cross check port_map and cap.n_ports */ |
4447d351 | 548 | if (pi->flags & AHCI_FLAG_HONOR_PI) { |
17199b18 TH |
549 | u32 tmp_port_map = port_map; |
550 | int n_ports = ahci_nr_ports(cap); | |
551 | ||
552 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
553 | if (tmp_port_map & (1 << i)) { | |
554 | n_ports--; | |
555 | tmp_port_map &= ~(1 << i); | |
556 | } | |
557 | } | |
558 | ||
559 | /* Whine if inconsistent. No need to update cap. | |
560 | * port_map is used to determine number of ports. | |
561 | */ | |
562 | if (n_ports || tmp_port_map) | |
4447d351 | 563 | dev_printk(KERN_WARNING, &pdev->dev, |
17199b18 TH |
564 | "nr_ports (%u) and implemented port map " |
565 | "(0x%x) don't match\n", | |
566 | ahci_nr_ports(cap), port_map); | |
567 | } else { | |
568 | /* fabricate port_map from cap.nr_ports */ | |
569 | port_map = (1 << ahci_nr_ports(cap)) - 1; | |
570 | } | |
571 | ||
d447df14 TH |
572 | /* record values to use during operation */ |
573 | hpriv->cap = cap; | |
574 | hpriv->port_map = port_map; | |
575 | } | |
576 | ||
577 | /** | |
578 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 579 | * @host: target ATA host |
d447df14 TH |
580 | * |
581 | * Restore initial config stored by ahci_save_initial_config(). | |
582 | * | |
583 | * LOCKING: | |
584 | * None. | |
585 | */ | |
4447d351 | 586 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 587 | { |
4447d351 TH |
588 | struct ahci_host_priv *hpriv = host->private_data; |
589 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
590 | ||
d447df14 TH |
591 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
592 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
593 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
594 | } | |
595 | ||
1da177e4 LT |
596 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
597 | { | |
598 | unsigned int sc_reg; | |
599 | ||
600 | switch (sc_reg_in) { | |
601 | case SCR_STATUS: sc_reg = 0; break; | |
602 | case SCR_CONTROL: sc_reg = 1; break; | |
603 | case SCR_ERROR: sc_reg = 2; break; | |
604 | case SCR_ACTIVE: sc_reg = 3; break; | |
605 | default: | |
606 | return 0xffffffffU; | |
607 | } | |
608 | ||
0d5ff566 | 609 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
610 | } |
611 | ||
612 | ||
613 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
614 | u32 val) | |
615 | { | |
616 | unsigned int sc_reg; | |
617 | ||
618 | switch (sc_reg_in) { | |
619 | case SCR_STATUS: sc_reg = 0; break; | |
620 | case SCR_CONTROL: sc_reg = 1; break; | |
621 | case SCR_ERROR: sc_reg = 2; break; | |
622 | case SCR_ACTIVE: sc_reg = 3; break; | |
623 | default: | |
624 | return; | |
625 | } | |
626 | ||
0d5ff566 | 627 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
628 | } |
629 | ||
4447d351 | 630 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 631 | { |
4447d351 | 632 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
633 | u32 tmp; |
634 | ||
d8fcd116 | 635 | /* start DMA */ |
9f592056 | 636 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
637 | tmp |= PORT_CMD_START; |
638 | writel(tmp, port_mmio + PORT_CMD); | |
639 | readl(port_mmio + PORT_CMD); /* flush */ | |
640 | } | |
641 | ||
4447d351 | 642 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 643 | { |
4447d351 | 644 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
645 | u32 tmp; |
646 | ||
647 | tmp = readl(port_mmio + PORT_CMD); | |
648 | ||
d8fcd116 | 649 | /* check if the HBA is idle */ |
254950cd TH |
650 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
651 | return 0; | |
652 | ||
d8fcd116 | 653 | /* setting HBA to idle */ |
254950cd TH |
654 | tmp &= ~PORT_CMD_START; |
655 | writel(tmp, port_mmio + PORT_CMD); | |
656 | ||
d8fcd116 | 657 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
658 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
659 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 660 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
661 | return -EIO; |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
4447d351 | 666 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 667 | { |
4447d351 TH |
668 | void __iomem *port_mmio = ahci_port_base(ap); |
669 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
670 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
671 | u32 tmp; |
672 | ||
673 | /* set FIS registers */ | |
4447d351 TH |
674 | if (hpriv->cap & HOST_CAP_64) |
675 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
676 | port_mmio + PORT_LST_ADDR_HI); | |
677 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 678 | |
4447d351 TH |
679 | if (hpriv->cap & HOST_CAP_64) |
680 | writel((pp->rx_fis_dma >> 16) >> 16, | |
681 | port_mmio + PORT_FIS_ADDR_HI); | |
682 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
683 | |
684 | /* enable FIS reception */ | |
685 | tmp = readl(port_mmio + PORT_CMD); | |
686 | tmp |= PORT_CMD_FIS_RX; | |
687 | writel(tmp, port_mmio + PORT_CMD); | |
688 | ||
689 | /* flush */ | |
690 | readl(port_mmio + PORT_CMD); | |
691 | } | |
692 | ||
4447d351 | 693 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 694 | { |
4447d351 | 695 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
696 | u32 tmp; |
697 | ||
698 | /* disable FIS reception */ | |
699 | tmp = readl(port_mmio + PORT_CMD); | |
700 | tmp &= ~PORT_CMD_FIS_RX; | |
701 | writel(tmp, port_mmio + PORT_CMD); | |
702 | ||
703 | /* wait for completion, spec says 500ms, give it 1000 */ | |
704 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
705 | PORT_CMD_FIS_ON, 10, 1000); | |
706 | if (tmp & PORT_CMD_FIS_ON) | |
707 | return -EBUSY; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
4447d351 | 712 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 713 | { |
4447d351 TH |
714 | struct ahci_host_priv *hpriv = ap->host->private_data; |
715 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
716 | u32 cmd; |
717 | ||
718 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
719 | ||
720 | /* spin up device */ | |
4447d351 | 721 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
722 | cmd |= PORT_CMD_SPIN_UP; |
723 | writel(cmd, port_mmio + PORT_CMD); | |
724 | } | |
725 | ||
726 | /* wake up link */ | |
727 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
728 | } | |
729 | ||
438ac6d5 | 730 | #ifdef CONFIG_PM |
4447d351 | 731 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 732 | { |
4447d351 TH |
733 | struct ahci_host_priv *hpriv = ap->host->private_data; |
734 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
735 | u32 cmd, scontrol; |
736 | ||
4447d351 | 737 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 738 | return; |
0be0aa98 | 739 | |
07c53dac TH |
740 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
741 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
742 | scontrol &= ~0xf; | |
743 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 744 | |
07c53dac TH |
745 | /* then set PxCMD.SUD to 0 */ |
746 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
747 | cmd &= ~PORT_CMD_SPIN_UP; | |
748 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 749 | } |
438ac6d5 | 750 | #endif |
0be0aa98 | 751 | |
df69c9c5 | 752 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 753 | { |
0be0aa98 | 754 | /* enable FIS reception */ |
4447d351 | 755 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
756 | |
757 | /* enable DMA */ | |
4447d351 | 758 | ahci_start_engine(ap); |
0be0aa98 TH |
759 | } |
760 | ||
4447d351 | 761 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
762 | { |
763 | int rc; | |
764 | ||
765 | /* disable DMA */ | |
4447d351 | 766 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
767 | if (rc) { |
768 | *emsg = "failed to stop engine"; | |
769 | return rc; | |
770 | } | |
771 | ||
772 | /* disable FIS reception */ | |
4447d351 | 773 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
774 | if (rc) { |
775 | *emsg = "failed stop FIS RX"; | |
776 | return rc; | |
777 | } | |
778 | ||
0be0aa98 TH |
779 | return 0; |
780 | } | |
781 | ||
4447d351 | 782 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 783 | { |
4447d351 TH |
784 | struct pci_dev *pdev = to_pci_dev(host->dev); |
785 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
d447df14 | 786 | u32 tmp; |
d91542c1 TH |
787 | |
788 | /* global controller reset */ | |
789 | tmp = readl(mmio + HOST_CTL); | |
790 | if ((tmp & HOST_RESET) == 0) { | |
791 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
792 | readl(mmio + HOST_CTL); /* flush */ | |
793 | } | |
794 | ||
795 | /* reset must complete within 1 second, or | |
796 | * the hardware should be considered fried. | |
797 | */ | |
798 | ssleep(1); | |
799 | ||
800 | tmp = readl(mmio + HOST_CTL); | |
801 | if (tmp & HOST_RESET) { | |
4447d351 | 802 | dev_printk(KERN_ERR, host->dev, |
d91542c1 TH |
803 | "controller reset failed (0x%x)\n", tmp); |
804 | return -EIO; | |
805 | } | |
806 | ||
98fa4b60 | 807 | /* turn on AHCI mode */ |
d91542c1 TH |
808 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
809 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 | 810 | |
d447df14 | 811 | /* some registers might be cleared on reset. restore initial values */ |
4447d351 | 812 | ahci_restore_initial_config(host); |
d91542c1 TH |
813 | |
814 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
815 | u16 tmp16; | |
816 | ||
817 | /* configure PCS */ | |
818 | pci_read_config_word(pdev, 0x92, &tmp16); | |
819 | tmp16 |= 0xf; | |
820 | pci_write_config_word(pdev, 0x92, tmp16); | |
821 | } | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
2bcd866b JG |
826 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
827 | int port_no, void __iomem *mmio, | |
828 | void __iomem *port_mmio) | |
829 | { | |
830 | const char *emsg = NULL; | |
831 | int rc; | |
832 | u32 tmp; | |
833 | ||
834 | /* make sure port is not active */ | |
835 | rc = ahci_deinit_port(ap, &emsg); | |
836 | if (rc) | |
837 | dev_printk(KERN_WARNING, &pdev->dev, | |
838 | "%s (%d)\n", emsg, rc); | |
839 | ||
840 | /* clear SError */ | |
841 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
842 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
843 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
844 | ||
845 | /* clear port IRQ */ | |
846 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
847 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
848 | if (tmp) | |
849 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
850 | ||
851 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
852 | } | |
853 | ||
4447d351 | 854 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 855 | { |
4447d351 TH |
856 | struct pci_dev *pdev = to_pci_dev(host->dev); |
857 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 858 | int i; |
d91542c1 TH |
859 | u32 tmp; |
860 | ||
4447d351 TH |
861 | for (i = 0; i < host->n_ports; i++) { |
862 | struct ata_port *ap = host->ports[i]; | |
863 | void __iomem *port_mmio = ahci_port_base(ap); | |
d91542c1 | 864 | |
4447d351 | 865 | if (ata_port_is_dummy(ap)) |
d91542c1 | 866 | continue; |
d91542c1 | 867 | |
2bcd866b | 868 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
869 | } |
870 | ||
871 | tmp = readl(mmio + HOST_CTL); | |
872 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
873 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
874 | tmp = readl(mmio + HOST_CTL); | |
875 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
876 | } | |
877 | ||
422b7595 | 878 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 879 | { |
4447d351 | 880 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 881 | struct ata_taskfile tf; |
422b7595 TH |
882 | u32 tmp; |
883 | ||
884 | tmp = readl(port_mmio + PORT_SIG); | |
885 | tf.lbah = (tmp >> 24) & 0xff; | |
886 | tf.lbam = (tmp >> 16) & 0xff; | |
887 | tf.lbal = (tmp >> 8) & 0xff; | |
888 | tf.nsect = (tmp) & 0xff; | |
889 | ||
890 | return ata_dev_classify(&tf); | |
891 | } | |
892 | ||
12fad3f9 TH |
893 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
894 | u32 opts) | |
cc9278ed | 895 | { |
12fad3f9 TH |
896 | dma_addr_t cmd_tbl_dma; |
897 | ||
898 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
899 | ||
900 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
901 | pp->cmd_slot[tag].status = 0; | |
902 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
903 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
904 | } |
905 | ||
bf2af2a2 | 906 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 907 | { |
0d5ff566 | 908 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 909 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 BJ |
910 | u32 tmp; |
911 | ||
912 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
913 | return -EOPNOTSUPP; | |
914 | ||
915 | tmp = readl(port_mmio + PORT_CMD); | |
916 | tmp |= PORT_CMD_CLO; | |
917 | writel(tmp, port_mmio + PORT_CMD); | |
918 | ||
919 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
920 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
921 | if (tmp & PORT_CMD_CLO) | |
922 | return -EIO; | |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
d4b2bab4 TH |
927 | static int ahci_softreset(struct ata_port *ap, unsigned int *class, |
928 | unsigned long deadline) | |
bf2af2a2 | 929 | { |
4658f79b | 930 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 931 | void __iomem *port_mmio = ahci_port_base(ap); |
4658f79b TH |
932 | const u32 cmd_fis_len = 5; /* five dwords */ |
933 | const char *reason = NULL; | |
934 | struct ata_taskfile tf; | |
75fe1806 | 935 | u32 tmp; |
4658f79b TH |
936 | u8 *fis; |
937 | int rc; | |
938 | ||
939 | DPRINTK("ENTER\n"); | |
940 | ||
81952c54 | 941 | if (ata_port_offline(ap)) { |
c2a65852 TH |
942 | DPRINTK("PHY reports no device\n"); |
943 | *class = ATA_DEV_NONE; | |
944 | return 0; | |
945 | } | |
946 | ||
4658f79b | 947 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
4447d351 | 948 | rc = ahci_stop_engine(ap); |
4658f79b TH |
949 | if (rc) { |
950 | reason = "failed to stop engine"; | |
951 | goto fail_restart; | |
952 | } | |
953 | ||
954 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
1244a19c | 955 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
bf2af2a2 | 956 | rc = ahci_clo(ap); |
4658f79b | 957 | |
bf2af2a2 BJ |
958 | if (rc == -EOPNOTSUPP) { |
959 | reason = "port busy but CLO unavailable"; | |
960 | goto fail_restart; | |
961 | } else if (rc) { | |
962 | reason = "port busy but CLO failed"; | |
4658f79b TH |
963 | goto fail_restart; |
964 | } | |
965 | } | |
966 | ||
967 | /* restart engine */ | |
4447d351 | 968 | ahci_start_engine(ap); |
4658f79b | 969 | |
3373efd8 | 970 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
971 | fis = pp->cmd_tbl; |
972 | ||
973 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
974 | ahci_fill_cmd_slot(pp, 0, |
975 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
976 | |
977 | tf.ctl |= ATA_SRST; | |
978 | ata_tf_to_fis(&tf, fis, 0); | |
979 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
980 | ||
981 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 982 | |
75fe1806 TH |
983 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
984 | if (tmp & 0x1) { | |
4658f79b TH |
985 | rc = -EIO; |
986 | reason = "1st FIS failed"; | |
987 | goto fail; | |
988 | } | |
989 | ||
990 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
991 | msleep(1); | |
992 | ||
993 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 994 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
995 | |
996 | tf.ctl &= ~ATA_SRST; | |
997 | ata_tf_to_fis(&tf, fis, 0); | |
998 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
999 | ||
1000 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1001 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1002 | ||
1003 | /* spec mandates ">= 2ms" before checking status. | |
1004 | * We wait 150ms, because that was the magic delay used for | |
1005 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
1006 | * between when the ATA command register is written, and then | |
1007 | * status is checked. Because waiting for "a while" before | |
1008 | * checking status is fine, post SRST, we perform this magic | |
1009 | * delay here as well. | |
1010 | */ | |
1011 | msleep(150); | |
1012 | ||
9b89391c TH |
1013 | rc = ata_wait_ready(ap, deadline); |
1014 | /* link occupied, -ENODEV too is an error */ | |
1015 | if (rc) { | |
1016 | reason = "device not ready"; | |
1017 | goto fail; | |
4658f79b | 1018 | } |
9b89391c | 1019 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1020 | |
1021 | DPRINTK("EXIT, class=%u\n", *class); | |
1022 | return 0; | |
1023 | ||
1024 | fail_restart: | |
4447d351 | 1025 | ahci_start_engine(ap); |
4658f79b | 1026 | fail: |
f15a1daf | 1027 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1028 | return rc; |
1029 | } | |
1030 | ||
d4b2bab4 TH |
1031 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class, |
1032 | unsigned long deadline) | |
422b7595 | 1033 | { |
4296971d TH |
1034 | struct ahci_port_priv *pp = ap->private_data; |
1035 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1036 | struct ata_taskfile tf; | |
4bd00f6a TH |
1037 | int rc; |
1038 | ||
1039 | DPRINTK("ENTER\n"); | |
1da177e4 | 1040 | |
4447d351 | 1041 | ahci_stop_engine(ap); |
4296971d TH |
1042 | |
1043 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1044 | ata_tf_init(ap->device, &tf); | |
dfd7a3db | 1045 | tf.command = 0x80; |
4296971d TH |
1046 | ata_tf_to_fis(&tf, d2h_fis, 0); |
1047 | ||
d4b2bab4 | 1048 | rc = sata_std_hardreset(ap, class, deadline); |
4296971d | 1049 | |
4447d351 | 1050 | ahci_start_engine(ap); |
1da177e4 | 1051 | |
81952c54 | 1052 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
1053 | *class = ahci_dev_classify(ap); |
1054 | if (*class == ATA_DEV_UNKNOWN) | |
1055 | *class = ATA_DEV_NONE; | |
1da177e4 | 1056 | |
4bd00f6a TH |
1057 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1058 | return rc; | |
1059 | } | |
1060 | ||
d4b2bab4 TH |
1061 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class, |
1062 | unsigned long deadline) | |
ad616ffb | 1063 | { |
ad616ffb TH |
1064 | int rc; |
1065 | ||
1066 | DPRINTK("ENTER\n"); | |
1067 | ||
4447d351 | 1068 | ahci_stop_engine(ap); |
ad616ffb | 1069 | |
d4b2bab4 TH |
1070 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context), |
1071 | deadline); | |
ad616ffb TH |
1072 | |
1073 | /* vt8251 needs SError cleared for the port to operate */ | |
1074 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); | |
1075 | ||
4447d351 | 1076 | ahci_start_engine(ap); |
ad616ffb TH |
1077 | |
1078 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1079 | ||
1080 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1081 | * request follow-up softreset. | |
1082 | */ | |
1083 | return rc ?: -EAGAIN; | |
1084 | } | |
1085 | ||
4bd00f6a TH |
1086 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
1087 | { | |
4447d351 | 1088 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1089 | u32 new_tmp, tmp; |
1090 | ||
1091 | ata_std_postreset(ap, class); | |
02eaa666 JG |
1092 | |
1093 | /* Make sure port's ATAPI bit is set appropriately */ | |
1094 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1095 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1096 | new_tmp |= PORT_CMD_ATAPI; |
1097 | else | |
1098 | new_tmp &= ~PORT_CMD_ATAPI; | |
1099 | if (new_tmp != tmp) { | |
1100 | writel(new_tmp, port_mmio + PORT_CMD); | |
1101 | readl(port_mmio + PORT_CMD); /* flush */ | |
1102 | } | |
1da177e4 LT |
1103 | } |
1104 | ||
1105 | static u8 ahci_check_status(struct ata_port *ap) | |
1106 | { | |
0d5ff566 | 1107 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1108 | |
1109 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1110 | } | |
1111 | ||
1da177e4 LT |
1112 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1113 | { | |
1114 | struct ahci_port_priv *pp = ap->private_data; | |
1115 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1116 | ||
1117 | ata_tf_from_fis(d2h_fis, tf); | |
1118 | } | |
1119 | ||
12fad3f9 | 1120 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1121 | { |
cedc9a47 JG |
1122 | struct scatterlist *sg; |
1123 | struct ahci_sg *ahci_sg; | |
828d09de | 1124 | unsigned int n_sg = 0; |
1da177e4 LT |
1125 | |
1126 | VPRINTK("ENTER\n"); | |
1127 | ||
1128 | /* | |
1129 | * Next, the S/G list. | |
1130 | */ | |
12fad3f9 | 1131 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1132 | ata_for_each_sg(sg, qc) { |
1133 | dma_addr_t addr = sg_dma_address(sg); | |
1134 | u32 sg_len = sg_dma_len(sg); | |
1135 | ||
1136 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1137 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1138 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1139 | |
cedc9a47 | 1140 | ahci_sg++; |
828d09de | 1141 | n_sg++; |
1da177e4 | 1142 | } |
828d09de JG |
1143 | |
1144 | return n_sg; | |
1da177e4 LT |
1145 | } |
1146 | ||
1147 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1148 | { | |
a0ea7328 JG |
1149 | struct ata_port *ap = qc->ap; |
1150 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1151 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1152 | void *cmd_tbl; |
1da177e4 LT |
1153 | u32 opts; |
1154 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1155 | unsigned int n_elem; |
1da177e4 | 1156 | |
1da177e4 LT |
1157 | /* |
1158 | * Fill in command table information. First, the header, | |
1159 | * a SATA Register - Host to Device command FIS. | |
1160 | */ | |
12fad3f9 TH |
1161 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1162 | ||
1163 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 1164 | if (is_atapi) { |
12fad3f9 TH |
1165 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1166 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1167 | } |
1da177e4 | 1168 | |
cc9278ed TH |
1169 | n_elem = 0; |
1170 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1171 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1172 | |
cc9278ed TH |
1173 | /* |
1174 | * Fill in command slot information. | |
1175 | */ | |
1176 | opts = cmd_fis_len | n_elem << 16; | |
1177 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1178 | opts |= AHCI_CMD_WRITE; | |
1179 | if (is_atapi) | |
4b10e559 | 1180 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1181 | |
12fad3f9 | 1182 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1183 | } |
1184 | ||
78cd52d0 | 1185 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1186 | { |
78cd52d0 TH |
1187 | struct ahci_port_priv *pp = ap->private_data; |
1188 | struct ata_eh_info *ehi = &ap->eh_info; | |
1189 | unsigned int err_mask = 0, action = 0; | |
1190 | struct ata_queued_cmd *qc; | |
1191 | u32 serror; | |
1da177e4 | 1192 | |
78cd52d0 | 1193 | ata_ehi_clear_desc(ehi); |
1da177e4 | 1194 | |
78cd52d0 TH |
1195 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
1196 | serror = ahci_scr_read(ap, SCR_ERROR); | |
1197 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 1198 | |
78cd52d0 TH |
1199 | /* analyze @irq_stat */ |
1200 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
1201 | ||
41669553 TH |
1202 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
1203 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) | |
1204 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1205 | ||
55a61604 | 1206 | if (irq_stat & PORT_IRQ_TF_ERR) { |
78cd52d0 | 1207 | err_mask |= AC_ERR_DEV; |
55a61604 CH |
1208 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
1209 | serror &= ~SERR_INTERNAL; | |
1210 | } | |
78cd52d0 TH |
1211 | |
1212 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1213 | err_mask |= AC_ERR_HOST_BUS; | |
1214 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
1215 | } |
1216 | ||
78cd52d0 TH |
1217 | if (irq_stat & PORT_IRQ_IF_ERR) { |
1218 | err_mask |= AC_ERR_ATA_BUS; | |
1219 | action |= ATA_EH_SOFTRESET; | |
1220 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
1221 | } | |
1da177e4 | 1222 | |
78cd52d0 | 1223 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 1224 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
1225 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
1226 | "connection status changed" : "PHY RDY changed"); | |
1227 | } | |
1228 | ||
1229 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1230 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 1231 | |
78cd52d0 TH |
1232 | err_mask |= AC_ERR_HSM; |
1233 | action |= ATA_EH_SOFTRESET; | |
1234 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
1235 | unk[0], unk[1], unk[2], unk[3]); | |
1236 | } | |
1da177e4 | 1237 | |
78cd52d0 TH |
1238 | /* okay, let's hand over to EH */ |
1239 | ehi->serror |= serror; | |
1240 | ehi->action |= action; | |
b8f6153e | 1241 | |
1da177e4 | 1242 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1243 | if (qc) |
1244 | qc->err_mask |= err_mask; | |
1245 | else | |
1246 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1247 | |
78cd52d0 TH |
1248 | if (irq_stat & PORT_IRQ_FREEZE) |
1249 | ata_port_freeze(ap); | |
1250 | else | |
1251 | ata_port_abort(ap); | |
1da177e4 LT |
1252 | } |
1253 | ||
df69c9c5 | 1254 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1255 | { |
4447d351 | 1256 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
12fad3f9 | 1257 | struct ata_eh_info *ehi = &ap->eh_info; |
0291f95f | 1258 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1259 | u32 status, qc_active; |
0291f95f | 1260 | int rc, known_irq = 0; |
1da177e4 LT |
1261 | |
1262 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1263 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1264 | ||
78cd52d0 TH |
1265 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1266 | ahci_error_intr(ap, status); | |
1267 | return; | |
1da177e4 LT |
1268 | } |
1269 | ||
12fad3f9 TH |
1270 | if (ap->sactive) |
1271 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1272 | else | |
1273 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1274 | ||
1275 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1276 | if (rc > 0) | |
1277 | return; | |
1278 | if (rc < 0) { | |
1279 | ehi->err_mask |= AC_ERR_HSM; | |
1280 | ehi->action |= ATA_EH_SOFTRESET; | |
1281 | ata_port_freeze(ap); | |
1282 | return; | |
1da177e4 LT |
1283 | } |
1284 | ||
2a3917a8 TH |
1285 | /* hmmm... a spurious interupt */ |
1286 | ||
0291f95f TH |
1287 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1288 | * implementation for non-NCQ commands. | |
1289 | */ | |
1290 | if (!ap->sactive) | |
12fad3f9 TH |
1291 | return; |
1292 | ||
0291f95f TH |
1293 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1294 | if (!pp->ncq_saw_d2h) | |
1295 | ata_port_printk(ap, KERN_INFO, | |
1296 | "D2H reg with I during NCQ, " | |
1297 | "this message won't be printed again\n"); | |
1298 | pp->ncq_saw_d2h = 1; | |
1299 | known_irq = 1; | |
1300 | } | |
1301 | ||
1302 | if (status & PORT_IRQ_DMAS_FIS) { | |
1303 | if (!pp->ncq_saw_dmas) | |
1304 | ata_port_printk(ap, KERN_INFO, | |
1305 | "DMAS FIS during NCQ, " | |
1306 | "this message won't be printed again\n"); | |
1307 | pp->ncq_saw_dmas = 1; | |
1308 | known_irq = 1; | |
1309 | } | |
1310 | ||
a2bbd0c9 | 1311 | if (status & PORT_IRQ_SDB_FIS) { |
04d4f7a1 | 1312 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
0291f95f | 1313 | |
afb2d552 TH |
1314 | if (le32_to_cpu(f[1])) { |
1315 | /* SDB FIS containing spurious completions | |
1316 | * might be dangerous, whine and fail commands | |
1317 | * with HSM violation. EH will turn off NCQ | |
1318 | * after several such failures. | |
1319 | */ | |
1320 | ata_ehi_push_desc(ehi, | |
1321 | "spurious completions during NCQ " | |
1322 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", | |
1323 | readl(port_mmio + PORT_CMD_ISSUE), | |
1324 | readl(port_mmio + PORT_SCR_ACT), | |
1325 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1326 | ehi->err_mask |= AC_ERR_HSM; | |
1327 | ehi->action |= ATA_EH_SOFTRESET; | |
1328 | ata_port_freeze(ap); | |
1329 | } else { | |
1330 | if (!pp->ncq_saw_sdb) | |
1331 | ata_port_printk(ap, KERN_INFO, | |
1332 | "spurious SDB FIS %08x:%08x during NCQ, " | |
1333 | "this message won't be printed again\n", | |
1334 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1335 | pp->ncq_saw_sdb = 1; | |
1336 | } | |
0291f95f TH |
1337 | known_irq = 1; |
1338 | } | |
2a3917a8 | 1339 | |
0291f95f | 1340 | if (!known_irq) |
78cd52d0 | 1341 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1342 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
12fad3f9 | 1343 | status, ap->active_tag, ap->sactive); |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | static void ahci_irq_clear(struct ata_port *ap) | |
1347 | { | |
1348 | /* TODO */ | |
1349 | } | |
1350 | ||
7d12e780 | 1351 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1352 | { |
cca3974e | 1353 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1354 | struct ahci_host_priv *hpriv; |
1355 | unsigned int i, handled = 0; | |
ea6ba10b | 1356 | void __iomem *mmio; |
1da177e4 LT |
1357 | u32 irq_stat, irq_ack = 0; |
1358 | ||
1359 | VPRINTK("ENTER\n"); | |
1360 | ||
cca3974e | 1361 | hpriv = host->private_data; |
0d5ff566 | 1362 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1363 | |
1364 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1365 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1366 | irq_stat &= hpriv->port_map; | |
1367 | if (!irq_stat) | |
1368 | return IRQ_NONE; | |
1369 | ||
cca3974e | 1370 | spin_lock(&host->lock); |
1da177e4 | 1371 | |
cca3974e | 1372 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1373 | struct ata_port *ap; |
1da177e4 | 1374 | |
67846b30 JG |
1375 | if (!(irq_stat & (1 << i))) |
1376 | continue; | |
1377 | ||
cca3974e | 1378 | ap = host->ports[i]; |
67846b30 | 1379 | if (ap) { |
df69c9c5 | 1380 | ahci_port_intr(ap); |
67846b30 JG |
1381 | VPRINTK("port %u\n", i); |
1382 | } else { | |
1383 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1384 | if (ata_ratelimit()) |
cca3974e | 1385 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1386 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1387 | } |
67846b30 JG |
1388 | |
1389 | irq_ack |= (1 << i); | |
1da177e4 LT |
1390 | } |
1391 | ||
1392 | if (irq_ack) { | |
1393 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1394 | handled = 1; | |
1395 | } | |
1396 | ||
cca3974e | 1397 | spin_unlock(&host->lock); |
1da177e4 LT |
1398 | |
1399 | VPRINTK("EXIT\n"); | |
1400 | ||
1401 | return IRQ_RETVAL(handled); | |
1402 | } | |
1403 | ||
9a3d9eb0 | 1404 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1405 | { |
1406 | struct ata_port *ap = qc->ap; | |
4447d351 | 1407 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1408 | |
12fad3f9 TH |
1409 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1410 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1411 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1412 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
78cd52d0 TH |
1417 | static void ahci_freeze(struct ata_port *ap) |
1418 | { | |
4447d351 | 1419 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1420 | |
1421 | /* turn IRQ off */ | |
1422 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1423 | } | |
1424 | ||
1425 | static void ahci_thaw(struct ata_port *ap) | |
1426 | { | |
0d5ff566 | 1427 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1428 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1429 | u32 tmp; |
1430 | ||
1431 | /* clear IRQ */ | |
1432 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1433 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1434 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 TH |
1435 | |
1436 | /* turn IRQ back on */ | |
1437 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1438 | } | |
1439 | ||
1440 | static void ahci_error_handler(struct ata_port *ap) | |
1441 | { | |
b51e9e5d | 1442 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1443 | /* restart engine */ |
4447d351 TH |
1444 | ahci_stop_engine(ap); |
1445 | ahci_start_engine(ap); | |
78cd52d0 TH |
1446 | } |
1447 | ||
1448 | /* perform recovery */ | |
4aeb0e32 | 1449 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1450 | ahci_postreset); |
78cd52d0 TH |
1451 | } |
1452 | ||
ad616ffb TH |
1453 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1454 | { | |
ad616ffb TH |
1455 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
1456 | /* restart engine */ | |
4447d351 TH |
1457 | ahci_stop_engine(ap); |
1458 | ahci_start_engine(ap); | |
ad616ffb TH |
1459 | } |
1460 | ||
1461 | /* perform recovery */ | |
1462 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1463 | ahci_postreset); | |
1464 | } | |
1465 | ||
78cd52d0 TH |
1466 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1467 | { | |
1468 | struct ata_port *ap = qc->ap; | |
1469 | ||
a51d644a | 1470 | if (qc->flags & ATA_QCFLAG_FAILED) { |
78cd52d0 | 1471 | /* make DMA engine forget about the failed command */ |
4447d351 TH |
1472 | ahci_stop_engine(ap); |
1473 | ahci_start_engine(ap); | |
78cd52d0 TH |
1474 | } |
1475 | } | |
1476 | ||
438ac6d5 | 1477 | #ifdef CONFIG_PM |
c1332875 TH |
1478 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1479 | { | |
c1332875 TH |
1480 | const char *emsg = NULL; |
1481 | int rc; | |
1482 | ||
4447d351 | 1483 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1484 | if (rc == 0) |
4447d351 | 1485 | ahci_power_down(ap); |
8e16f941 | 1486 | else { |
c1332875 | 1487 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1488 | ahci_start_port(ap); |
c1332875 TH |
1489 | } |
1490 | ||
1491 | return rc; | |
1492 | } | |
1493 | ||
1494 | static int ahci_port_resume(struct ata_port *ap) | |
1495 | { | |
4447d351 | 1496 | ahci_power_up(ap); |
df69c9c5 | 1497 | ahci_start_port(ap); |
c1332875 TH |
1498 | |
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1503 | { | |
cca3974e | 1504 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1505 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1506 | u32 ctl; |
1507 | ||
1508 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1509 | /* AHCI spec rev1.1 section 8.3.3: | |
1510 | * Software must disable interrupts prior to requesting a | |
1511 | * transition of the HBA to D3 state. | |
1512 | */ | |
1513 | ctl = readl(mmio + HOST_CTL); | |
1514 | ctl &= ~HOST_IRQ_EN; | |
1515 | writel(ctl, mmio + HOST_CTL); | |
1516 | readl(mmio + HOST_CTL); /* flush */ | |
1517 | } | |
1518 | ||
1519 | return ata_pci_device_suspend(pdev, mesg); | |
1520 | } | |
1521 | ||
1522 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1523 | { | |
cca3974e | 1524 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1525 | int rc; |
1526 | ||
553c4aa6 TH |
1527 | rc = ata_pci_device_do_resume(pdev); |
1528 | if (rc) | |
1529 | return rc; | |
c1332875 TH |
1530 | |
1531 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1532 | rc = ahci_reset_controller(host); |
c1332875 TH |
1533 | if (rc) |
1534 | return rc; | |
1535 | ||
4447d351 | 1536 | ahci_init_controller(host); |
c1332875 TH |
1537 | } |
1538 | ||
cca3974e | 1539 | ata_host_resume(host); |
c1332875 TH |
1540 | |
1541 | return 0; | |
1542 | } | |
438ac6d5 | 1543 | #endif |
c1332875 | 1544 | |
254950cd TH |
1545 | static int ahci_port_start(struct ata_port *ap) |
1546 | { | |
cca3974e | 1547 | struct device *dev = ap->host->dev; |
254950cd | 1548 | struct ahci_port_priv *pp; |
254950cd TH |
1549 | void *mem; |
1550 | dma_addr_t mem_dma; | |
1551 | int rc; | |
1552 | ||
24dc5f33 | 1553 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1554 | if (!pp) |
1555 | return -ENOMEM; | |
254950cd TH |
1556 | |
1557 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1558 | if (rc) |
254950cd | 1559 | return rc; |
254950cd | 1560 | |
24dc5f33 TH |
1561 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1562 | GFP_KERNEL); | |
1563 | if (!mem) | |
254950cd | 1564 | return -ENOMEM; |
254950cd TH |
1565 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1566 | ||
1567 | /* | |
1568 | * First item in chunk of DMA memory: 32-slot command table, | |
1569 | * 32 bytes each in size | |
1570 | */ | |
1571 | pp->cmd_slot = mem; | |
1572 | pp->cmd_slot_dma = mem_dma; | |
1573 | ||
1574 | mem += AHCI_CMD_SLOT_SZ; | |
1575 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1576 | ||
1577 | /* | |
1578 | * Second item: Received-FIS area | |
1579 | */ | |
1580 | pp->rx_fis = mem; | |
1581 | pp->rx_fis_dma = mem_dma; | |
1582 | ||
1583 | mem += AHCI_RX_FIS_SZ; | |
1584 | mem_dma += AHCI_RX_FIS_SZ; | |
1585 | ||
1586 | /* | |
1587 | * Third item: data area for storing a single command | |
1588 | * and its scatter-gather table | |
1589 | */ | |
1590 | pp->cmd_tbl = mem; | |
1591 | pp->cmd_tbl_dma = mem_dma; | |
1592 | ||
1593 | ap->private_data = pp; | |
1594 | ||
df69c9c5 JG |
1595 | /* engage engines, captain */ |
1596 | return ahci_port_resume(ap); | |
254950cd TH |
1597 | } |
1598 | ||
1599 | static void ahci_port_stop(struct ata_port *ap) | |
1600 | { | |
0be0aa98 TH |
1601 | const char *emsg = NULL; |
1602 | int rc; | |
254950cd | 1603 | |
0be0aa98 | 1604 | /* de-initialize port */ |
4447d351 | 1605 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
1606 | if (rc) |
1607 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1608 | } |
1609 | ||
4447d351 | 1610 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 1611 | { |
1da177e4 | 1612 | int rc; |
1da177e4 | 1613 | |
1da177e4 LT |
1614 | if (using_dac && |
1615 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1616 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1617 | if (rc) { | |
1618 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1619 | if (rc) { | |
a9524a76 JG |
1620 | dev_printk(KERN_ERR, &pdev->dev, |
1621 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1622 | return rc; |
1623 | } | |
1624 | } | |
1da177e4 LT |
1625 | } else { |
1626 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1627 | if (rc) { | |
a9524a76 JG |
1628 | dev_printk(KERN_ERR, &pdev->dev, |
1629 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1630 | return rc; |
1631 | } | |
1632 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1633 | if (rc) { | |
a9524a76 JG |
1634 | dev_printk(KERN_ERR, &pdev->dev, |
1635 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1636 | return rc; |
1637 | } | |
1638 | } | |
1da177e4 LT |
1639 | return 0; |
1640 | } | |
1641 | ||
4447d351 | 1642 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 1643 | { |
4447d351 TH |
1644 | struct ahci_host_priv *hpriv = host->private_data; |
1645 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1646 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
1647 | u32 vers, cap, impl, speed; |
1648 | const char *speed_s; | |
1649 | u16 cc; | |
1650 | const char *scc_s; | |
1651 | ||
1652 | vers = readl(mmio + HOST_VERSION); | |
1653 | cap = hpriv->cap; | |
1654 | impl = hpriv->port_map; | |
1655 | ||
1656 | speed = (cap >> 20) & 0xf; | |
1657 | if (speed == 1) | |
1658 | speed_s = "1.5"; | |
1659 | else if (speed == 2) | |
1660 | speed_s = "3"; | |
1661 | else | |
1662 | speed_s = "?"; | |
1663 | ||
1664 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 1665 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 1666 | scc_s = "IDE"; |
c9f89475 | 1667 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 1668 | scc_s = "SATA"; |
c9f89475 | 1669 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
1670 | scc_s = "RAID"; |
1671 | else | |
1672 | scc_s = "unknown"; | |
1673 | ||
a9524a76 JG |
1674 | dev_printk(KERN_INFO, &pdev->dev, |
1675 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1676 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1677 | , | |
1da177e4 LT |
1678 | |
1679 | (vers >> 24) & 0xff, | |
1680 | (vers >> 16) & 0xff, | |
1681 | (vers >> 8) & 0xff, | |
1682 | vers & 0xff, | |
1683 | ||
1684 | ((cap >> 8) & 0x1f) + 1, | |
1685 | (cap & 0x1f) + 1, | |
1686 | speed_s, | |
1687 | impl, | |
1688 | scc_s); | |
1689 | ||
a9524a76 JG |
1690 | dev_printk(KERN_INFO, &pdev->dev, |
1691 | "flags: " | |
1da177e4 LT |
1692 | "%s%s%s%s%s%s" |
1693 | "%s%s%s%s%s%s%s\n" | |
1694 | , | |
1da177e4 LT |
1695 | |
1696 | cap & (1 << 31) ? "64bit " : "", | |
1697 | cap & (1 << 30) ? "ncq " : "", | |
1698 | cap & (1 << 28) ? "ilck " : "", | |
1699 | cap & (1 << 27) ? "stag " : "", | |
1700 | cap & (1 << 26) ? "pm " : "", | |
1701 | cap & (1 << 25) ? "led " : "", | |
1702 | ||
1703 | cap & (1 << 24) ? "clo " : "", | |
1704 | cap & (1 << 19) ? "nz " : "", | |
1705 | cap & (1 << 18) ? "only " : "", | |
1706 | cap & (1 << 17) ? "pmp " : "", | |
1707 | cap & (1 << 15) ? "pio " : "", | |
1708 | cap & (1 << 14) ? "slum " : "", | |
1709 | cap & (1 << 13) ? "part " : "" | |
1710 | ); | |
1711 | } | |
1712 | ||
24dc5f33 | 1713 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1714 | { |
1715 | static int printed_version; | |
4447d351 TH |
1716 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
1717 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 1718 | struct device *dev = &pdev->dev; |
1da177e4 | 1719 | struct ahci_host_priv *hpriv; |
4447d351 TH |
1720 | struct ata_host *host; |
1721 | int i, rc; | |
1da177e4 LT |
1722 | |
1723 | VPRINTK("ENTER\n"); | |
1724 | ||
12fad3f9 TH |
1725 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1726 | ||
1da177e4 | 1727 | if (!printed_version++) |
a9524a76 | 1728 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1729 | |
4447d351 | 1730 | /* acquire resources */ |
24dc5f33 | 1731 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1732 | if (rc) |
1733 | return rc; | |
1734 | ||
0d5ff566 TH |
1735 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1736 | if (rc == -EBUSY) | |
24dc5f33 | 1737 | pcim_pin_device(pdev); |
0d5ff566 | 1738 | if (rc) |
24dc5f33 | 1739 | return rc; |
1da177e4 | 1740 | |
24dc5f33 | 1741 | if (pci_enable_msi(pdev)) |
907f4678 | 1742 | pci_intx(pdev, 1); |
1da177e4 | 1743 | |
24dc5f33 TH |
1744 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1745 | if (!hpriv) | |
1746 | return -ENOMEM; | |
1da177e4 | 1747 | |
4447d351 TH |
1748 | /* save initial config */ |
1749 | ahci_save_initial_config(pdev, &pi, hpriv); | |
1da177e4 | 1750 | |
4447d351 TH |
1751 | /* prepare host */ |
1752 | if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ)) | |
1753 | pi.flags |= ATA_FLAG_NCQ; | |
1da177e4 | 1754 | |
4447d351 TH |
1755 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
1756 | if (!host) | |
1757 | return -ENOMEM; | |
1758 | host->iomap = pcim_iomap_table(pdev); | |
1759 | host->private_data = hpriv; | |
1760 | ||
1761 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
1762 | struct ata_port *ap = host->ports[i]; |
1763 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 1764 | |
dab632e8 JG |
1765 | /* standard SATA port setup */ |
1766 | if (hpriv->port_map & (1 << i)) { | |
4447d351 TH |
1767 | ap->ioaddr.cmd_addr = port_mmio; |
1768 | ap->ioaddr.scr_addr = port_mmio + PORT_SCR; | |
dab632e8 JG |
1769 | } |
1770 | ||
1771 | /* disabled/not-implemented port */ | |
1772 | else | |
1773 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 1774 | } |
d447df14 | 1775 | |
4447d351 TH |
1776 | /* initialize adapter */ |
1777 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1778 | if (rc) |
24dc5f33 | 1779 | return rc; |
1da177e4 | 1780 | |
4447d351 TH |
1781 | rc = ahci_reset_controller(host); |
1782 | if (rc) | |
1783 | return rc; | |
1da177e4 | 1784 | |
4447d351 TH |
1785 | ahci_init_controller(host); |
1786 | ahci_print_info(host); | |
1da177e4 | 1787 | |
4447d351 TH |
1788 | pci_set_master(pdev); |
1789 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
1790 | &ahci_sht); | |
907f4678 | 1791 | } |
1da177e4 LT |
1792 | |
1793 | static int __init ahci_init(void) | |
1794 | { | |
b7887196 | 1795 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
1796 | } |
1797 | ||
1da177e4 LT |
1798 | static void __exit ahci_exit(void) |
1799 | { | |
1800 | pci_unregister_driver(&ahci_pci_driver); | |
1801 | } | |
1802 | ||
1803 | ||
1804 | MODULE_AUTHOR("Jeff Garzik"); | |
1805 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1806 | MODULE_LICENSE("GPL"); | |
1807 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1808 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1809 | |
1810 | module_init(ahci_init); | |
1811 | module_exit(ahci_exit); |