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libata: Assign OF node to the SCSI device
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ahci.c - AHCI SATA support
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * AHCI hardware documentation:
1da177e4 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
1da177e4
LT		 22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
87507cfd 25#include <linux/dma-mapping.h>
a9524a76 26#include <linux/device.h>
edc93052 27#include <linux/dmi.h>
5a0e3ad6 28#include <linux/gfp.h>
ee2aad42 29#include <linux/msi.h>
1da177e4 30#include <scsi/scsi_host.h>
193515d5 31#include <scsi/scsi_cmnd.h>
1da177e4 32#include <linux/libata.h>
aecec8b6
CH		 33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 35#include "ahci.h"
1da177e4
LT		 36
37#define DRV_NAME "ahci"
7d50b60b 38#define DRV_VERSION "3.0"
1da177e4 39
1da177e4 40enum {
318893e1 41 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 42 AHCI_PCI_BAR_CAVIUM = 0,
e49bd683 43 AHCI_PCI_BAR_LOONGSON = 0,
7f9c9f8e 44 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 46 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 47};
48
49enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
ebb82e3c 53 board_ahci_mobile,
66a7cbc3 54 board_ahci_nomsi,
67809f85 55 board_ahci_noncq,
441577ef 56 board_ahci_nosntf,
5f173107 57 board_ahci_yes_fbs,
1da177e4 58
441577ef 59 /* board IDs for specific chipsets in alphabetical order */
7d523bdc 60 board_ahci_al,
dbfe8ef5 61 board_ahci_avn,
441577ef 62 board_ahci_mcp65,
83f2b963
TH		 63 board_ahci_mcp77,
64 board_ahci_mcp89,
441577ef
TH		 65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
c312ef17
DW		 70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
441577ef
TH		 76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 84static void ahci_remove_one(struct pci_dev *dev);
10a663a1 85static void ahci_shutdown_one(struct pci_dev *dev);
a1efdaba
TH		 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
dbfe8ef5
DW		 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
cb85696d
JL		 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
02e53293
MW		 94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
438ac6d5 100#endif
02e53293 101#endif /* CONFIG_PM */
ad616ffb 102
fad16e7a
TH		 103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
029cfd6b
TH		 107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
a1efdaba 109 .hardreset = ahci_vt8251_hardreset,
029cfd6b 110};
edc93052 111
029cfd6b
TH		 112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 115};
116
dbfe8ef5
DW		 117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
98ac62de 122static const struct ata_port_info ahci_port_info[] = {
441577ef 123 /* by features */
facb8fa6 124 [board_ahci] = {
1188c0d8 125 .flags = AHCI_FLAG_COMMON,
14bdef98 126 .pio_mask = ATA_PIO4,
469248ab 127 .udma_mask = ATA_UDMA6,
1da177e4
LT		 128 .port_ops = &ahci_ops,
129 },
facb8fa6 130 [board_ahci_ign_iferr] = {
441577ef 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 132 .flags = AHCI_FLAG_COMMON,
14bdef98 133 .pio_mask = ATA_PIO4,
469248ab 134 .udma_mask = ATA_UDMA6,
441577ef 135 .port_ops = &ahci_ops,
bf2af2a2 136 },
ebb82e3c
HG		 137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
66a7cbc3
TH		 144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
67809f85
LK		 151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
facb8fa6 158 [board_ahci_nosntf] = {
441577ef 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
41669553
TH		 163 .port_ops = &ahci_ops,
164 },
facb8fa6 165 [board_ahci_yes_fbs] = {
5f173107
TH		 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
441577ef 172 /* by chipsets */
7d523bdc
HH		 173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
dbfe8ef5
DW		 180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
facb8fa6 186 [board_ahci_mcp65] = {
83f2b963
TH		 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
ae01b249 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
facb8fa6 194 [board_ahci_mcp77] = {
83f2b963
TH		 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
facb8fa6 201 [board_ahci_mcp89] = {
83f2b963 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 203 .flags = AHCI_FLAG_COMMON,
14bdef98 204 .pio_mask = ATA_PIO4,
469248ab 205 .udma_mask = ATA_UDMA6,
441577ef 206 .port_ops = &ahci_ops,
55a61604 207 },
facb8fa6 208 [board_ahci_mv] = {
417a1a6d 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 212 .pio_mask = ATA_PIO4,
cd70c266
JG		 213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
facb8fa6 216 [board_ahci_sb600] = {
441577ef
TH		 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 220 .flags = AHCI_FLAG_COMMON,
14bdef98 221 .pio_mask = ATA_PIO4,
e39fc8c9 222 .udma_mask = ATA_UDMA6,
345347c5 223 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 224 },
facb8fa6 225 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
345347c5 230 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 231 },
facb8fa6 232 [board_ahci_vt8251] = {
441577ef 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
441577ef 237 .port_ops = &ahci_vt8251_ops,
1b677afd 238 },
c312ef17
DW		 239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
1da177e4
LT		 245};
246
3b7d697d 247static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 248 /* Intel */
54bb3a94
JG		 249 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
250 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
251 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
252 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
253 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 254 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 255 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
256 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 259 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 260 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 261 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
263 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
265 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
ebb82e3c
HG		 269 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
270 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
7a234aff 274 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
ebb82e3c 275 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
d4155e6f
JG		 276 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
277 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 278 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 279 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 280 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 281 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
282 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 283 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 284 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ebb82e3c 285 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
adcb5308 286 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ebb82e3c 287 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
c1f57d9b 288 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
c312ef17
DW		 289 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
5623cab8 309 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ebb82e3c 310 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
5623cab8 311 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ebb82e3c 312 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
5623cab8
SH		 313 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
314 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 315 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
316 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
317 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 318 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 319 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea 320 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ebb82e3c 321 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
181e3cea
SH		 322 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
323 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ebb82e3c 325 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
2cab7a4c 326 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66 327 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ebb82e3c 328 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
ea4ace66 329 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ebb82e3c 330 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 331 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ebb82e3c 332 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 333 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ebb82e3c
HG		 334 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
335 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
336 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
338 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
4544e403 343 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
29e674dd
SH		 344 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 352 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 360 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
361 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 362 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
363 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
364 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
365 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
366 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
367 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
368 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 370 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
ebb82e3c
HG		 371 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
372 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
373 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
374 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
1b071a09 375 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ebb82e3c 376 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
1b071a09 377 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ebb82e3c 378 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 379 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ebb82e3c 380 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 381 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ebb82e3c
HG		 382 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
383 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
384 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
385 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
c5967b79 386 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ebb82e3c 387 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
690000b9 388 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 389 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ebb82e3c 390 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
690000b9 391 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 392 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 393 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 394 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 395 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 396 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 397 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 398 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
399 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 400 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 401 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 402 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
f919dde0 404 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
32d25454 405 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
ebb82e3c
HG		 406 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
407 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
408 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
409 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
ba445791 410 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
fe7fa31a 411
e34bb370
TH		 412 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
413 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
414 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 415 /* JMicron 362B and 362C have an AHCI function with IDE class code */
416 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
417 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 418 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 419
420 /* ATI */
c65ec1c2 421 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 422 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
423 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
424 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
426 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
427 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 428
7d523bdc
HH		 429 /* Amazon's Annapurna Labs support */
430 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
431 .class = PCI_CLASS_STORAGE_SATA_AHCI,
432 .class_mask = 0xffffff,
433 board_ahci_al },
e2dd90b1 434 /* AMD */
5deab536 435 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 436 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 437 /* AMD is using RAID class only for ahci controllers */
438 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
439 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
440
fe7fa31a 441 /* VIA */
54bb3a94 442 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 443 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 444
445 /* NVIDIA */
e297d99e
TH		 446 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 454 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
484 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
508 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
519 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
520 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
521 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 530
95916edd 531 /* SiS */
20e2de4a
TH		 532 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
533 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
534 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 535
318893e1
AR		 536 /* ST Microelectronics */
537 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
538
cd70c266
JG		 539 /* Marvell */
540 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 541 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 543 .class = PCI_CLASS_STORAGE_SATA_AHCI,
544 .class_mask = 0xffffff,
5f173107 545 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 547 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 548 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
549 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
550 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 552 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 554 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 556 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 558 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
560 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
562 .driver_data = board_ahci_yes_fbs },
69fd3157 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 564 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
566 .driver_data = board_ahci_yes_fbs },
28b2182d
HG		 567 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
d2518365 570 .driver_data = board_ahci_yes_fbs },
cd70c266 571
c77a036b
MN		 572 /* Promise */
573 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 574 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 575
c9703765 576 /* Asmedia */
7b4f6eca
AC		 577 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
578 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
579 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
580 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 581 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
582 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 583
67809f85 584 /*
66a7cbc3
TH		 585 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
586 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 587 */
66a7cbc3 588 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 589 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 590
7f9c9f8e
HD		 591 /* Enmotus */
592 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
593
e49bd683
TY		 594 /* Loongson */
595 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
596
415ae2b5
JG		 597 /* Generic, PCI class code for AHCI */
598 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 599 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 600
1da177e4
LT		 601 { } /* terminate list */
602};
603
f1d848f9
MW		 604static const struct dev_pm_ops ahci_pci_pm_ops = {
605 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 606 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
607 ahci_pci_device_runtime_resume, NULL)
f1d848f9 608};
1da177e4
LT		 609
610static struct pci_driver ahci_pci_driver = {
611 .name = DRV_NAME,
612 .id_table = ahci_pci_tbl,
613 .probe = ahci_init_one,
02e53293 614 .remove = ahci_remove_one,
10a663a1 615 .shutdown = ahci_shutdown_one,
f1d848f9
MW		 616 .driver = {
617 .pm = &ahci_pci_pm_ops,
618 },
365cfa1e 619};
1da177e4 620
5219d653 621#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 622static int marvell_enable;
623#else
624static int marvell_enable = 1;
625#endif
626module_param(marvell_enable, int, 0644);
627MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 628
b1a9585c 629static int mobile_lpm_policy = -1;
ebb82e3c
HG		 630module_param(mobile_lpm_policy, int, 0644);
631MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
1da177e4 632
365cfa1e
AV		 633static void ahci_pci_save_initial_config(struct pci_dev *pdev,
634 struct ahci_host_priv *hpriv)
635{
365cfa1e
AV		 636 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
637 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 638 hpriv->force_port_map = 1;
1da177e4
LT		 639 }
640
365cfa1e
AV		 641 /*
642 * Temporary Marvell 6145 hack: PATA port presence
643 * is asserted through the standard AHCI port
644 * presence register, as bit 4 (counting from 0)
d28f87aa 645 */
365cfa1e
AV		 646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
647 if (pdev->device == 0x6121)
9a23c1d6 648 hpriv->mask_port_map = 0x3;
365cfa1e 649 else
9a23c1d6 650 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 651 dev_info(&pdev->dev,
652 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
653 }
1da177e4 654
725c7b57 655 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 656}
657
365cfa1e 658static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 659{
365cfa1e
AV		 660 struct ahci_host_priv *hpriv = host->private_data;
661 struct pci_dev *pdev = to_pci_dev(host->dev);
662 void __iomem *port_mmio;
78cd52d0 663 u32 tmp;
365cfa1e 664 int mv;
78cd52d0 665
365cfa1e
AV		 666 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
667 if (pdev->device == 0x6121)
668 mv = 2;
669 else
670 mv = 4;
671 port_mmio = __ahci_port_base(host, mv);
78cd52d0 672
365cfa1e 673 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 674
365cfa1e
AV		 675 /* clear port IRQ */
676 tmp = readl(port_mmio + PORT_IRQ_STAT);
677 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
678 if (tmp)
679 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 680 }
681
365cfa1e 682 ahci_init_controller(host);
edc93052
TH		 683}
684
365cfa1e
AV		 685static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
686 unsigned long deadline)
d6ef3153 687{
365cfa1e 688 struct ata_port *ap = link->ap;
039ece38 689 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 690 bool online;
d6ef3153
SH		 691 int rc;
692
365cfa1e 693 DPRINTK("ENTER\n");
d6ef3153 694
fa89f53b 695 hpriv->stop_engine(ap);
d6ef3153 696
365cfa1e
AV		 697 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
698 deadline, &online, NULL);
d6ef3153 699
039ece38 700 hpriv->start_engine(ap);
d6ef3153 701
365cfa1e 702 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 703
365cfa1e
AV		 704 /* vt8251 doesn't clear BSY on signature FIS reception,
705 * request follow-up softreset.
706 */
707 return online ? -EAGAIN : rc;
7d50b60b
TH		 708}
709
365cfa1e
AV		 710static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
711 unsigned long deadline)
7d50b60b 712{
365cfa1e 713 struct ata_port *ap = link->ap;
1c954a4d 714 struct ahci_port_priv *pp = ap->private_data;
039ece38 715 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 716 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
717 struct ata_taskfile tf;
718 bool online;
719 int rc;
7d50b60b 720
fa89f53b 721 hpriv->stop_engine(ap);
028a2596 722
365cfa1e
AV		 723 /* clear D2H reception area to properly wait for D2H FIS */
724 ata_tf_init(link->device, &tf);
9bbb1b0e 725 tf.command = ATA_BUSY;
365cfa1e 726 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 727
365cfa1e
AV		 728 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
729 deadline, &online, NULL);
028a2596 730
039ece38 731 hpriv->start_engine(ap);
c1332875 732
365cfa1e
AV		 733 /* The pseudo configuration device on SIMG4726 attached to
734 * ASUS P5W-DH Deluxe doesn't send signature FIS after
735 * hardreset if no device is attached to the first downstream
736 * port && the pseudo device locks up on SRST w/ PMP==0. To
737 * work around this, wait for !BSY only briefly. If BSY isn't
738 * cleared, perform CLO and proceed to IDENTIFY (achieved by
739 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
740 *
741 * Wait for two seconds. Devices attached to downstream port
742 * which can't process the following IDENTIFY after this will
743 * have to be reset again. For most cases, this should
744 * suffice while making probing snappish enough.
745 */
746 if (online) {
747 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
748 ahci_check_ready);
749 if (rc)
750 ahci_kick_engine(ap);
c1332875 751 }
c1332875
TH		 752 return rc;
753}
754
dbfe8ef5
DW		 755/*
756 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
757 *
758 * It has been observed with some SSDs that the timing of events in the
759 * link synchronization phase can leave the port in a state that can not
760 * be recovered by a SATA-hard-reset alone. The failing signature is
761 * SStatus.DET stuck at 1 ("Device presence detected but Phy
762 * communication not established"). It was found that unloading and
763 * reloading the driver when this problem occurs allows the drive
764 * connection to be recovered (DET advanced to 0x3). The critical
765 * component of reloading the driver is that the port state machines are
766 * reset by bouncing "port enable" in the AHCI PCS configuration
767 * register. So, reproduce that effect by bouncing a port whenever we
768 * see DET==1 after a reset.
769 */
770static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
771 unsigned long deadline)
772{
773 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
774 struct ata_port *ap = link->ap;
775 struct ahci_port_priv *pp = ap->private_data;
776 struct ahci_host_priv *hpriv = ap->host->private_data;
777 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
778 unsigned long tmo = deadline - jiffies;
779 struct ata_taskfile tf;
780 bool online;
781 int rc, i;
782
783 DPRINTK("ENTER\n");
784
fa89f53b 785 hpriv->stop_engine(ap);
dbfe8ef5
DW		 786
787 for (i = 0; i < 2; i++) {
788 u16 val;
789 u32 sstatus;
790 int port = ap->port_no;
791 struct ata_host *host = ap->host;
792 struct pci_dev *pdev = to_pci_dev(host->dev);
793
794 /* clear D2H reception area to properly wait for D2H FIS */
795 ata_tf_init(link->device, &tf);
796 tf.command = ATA_BUSY;
797 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
798
799 rc = sata_link_hardreset(link, timing, deadline, &online,
800 ahci_check_ready);
801
802 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
803 (sstatus & 0xf) != 1)
804 break;
805
806 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
807 port);
808
809 pci_read_config_word(pdev, 0x92, &val);
810 val &= ~(1 << port);
811 pci_write_config_word(pdev, 0x92, val);
812 ata_msleep(ap, 1000);
813 val |= 1 << port;
814 pci_write_config_word(pdev, 0x92, val);
815 deadline += tmo;
816 }
817
818 hpriv->start_engine(ap);
819
820 if (online)
821 *class = ahci_dev_classify(ap);
822
823 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
824 return rc;
825}
826
827
02e53293
MW		 828#ifdef CONFIG_PM
829static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 830{
9b10ae86 831 struct ahci_host_priv *hpriv = host->private_data;
d8993349 832 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 833 u32 ctl;
834
f1d848f9
MW		 835 /* AHCI spec rev1.1 section 8.3.3:
836 * Software must disable interrupts prior to requesting a
837 * transition of the HBA to D3 state.
838 */
839 ctl = readl(mmio + HOST_CTL);
840 ctl &= ~HOST_IRQ_EN;
841 writel(ctl, mmio + HOST_CTL);
842 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 843}
844
845static int ahci_pci_device_runtime_suspend(struct device *dev)
846{
847 struct pci_dev *pdev = to_pci_dev(dev);
848 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 849
02e53293
MW		 850 ahci_pci_disable_interrupts(host);
851 return 0;
852}
853
854static int ahci_pci_device_runtime_resume(struct device *dev)
855{
856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct ata_host *host = pci_get_drvdata(pdev);
858 int rc;
859
c312ef17 860 rc = ahci_reset_controller(host);
02e53293
MW		 861 if (rc)
862 return rc;
863 ahci_pci_init_controller(host);
864 return 0;
865}
866
867#ifdef CONFIG_PM_SLEEP
868static int ahci_pci_device_suspend(struct device *dev)
869{
870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct ata_host *host = pci_get_drvdata(pdev);
872 struct ahci_host_priv *hpriv = host->private_data;
873
874 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
875 dev_err(&pdev->dev,
876 "BIOS update required for suspend/resume\n");
877 return -EIO;
878 }
879
880 ahci_pci_disable_interrupts(host);
f1d848f9 881 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 882}
883
f1d848f9 884static int ahci_pci_device_resume(struct device *dev)
c1332875 885{
f1d848f9 886 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 887 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 888 int rc;
889
cb85696d
JL		 890 /* Apple BIOS helpfully mangles the registers on resume */
891 if (is_mcp89_apple(pdev))
892 ahci_mcp89_apple_enable(pdev);
893
c1332875 894 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
c312ef17 895 rc = ahci_reset_controller(host);
c1332875
TH		 896 if (rc)
897 return rc;
898
781d6550 899 ahci_pci_init_controller(host);
c1332875
TH		 900 }
901
cca3974e 902 ata_host_resume(host);
c1332875
TH		 903
904 return 0;
905}
438ac6d5 906#endif
c1332875 907
02e53293
MW		 908#endif /* CONFIG_PM */
909
4447d351 910static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 911{
b1716871 912 const int dma_bits = using_dac ? 64 : 32;
1da177e4 913 int rc;
1da177e4 914
318893e1
AR		 915 /*
916 * If the device fixup already set the dma_mask to some non-standard
917 * value, don't extend it here. This happens on STA2X11, for example.
b1716871
CH		 918 *
919 * XXX: manipulating the DMA mask from platform code is completely
a7ba70f1 920 * bogus, platform code should use dev->bus_dma_limit instead..
318893e1
AR		 921 */
922 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
923 return 0;
924
b1716871
CH		 925 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
926 if (rc)
927 dev_err(&pdev->dev, "DMA enable failed\n");
928 return rc;
1da177e4
LT		 929}
930
439fcaec
AV		 931static void ahci_pci_print_info(struct ata_host *host)
932{
933 struct pci_dev *pdev = to_pci_dev(host->dev);
934 u16 cc;
935 const char *scc_s;
936
937 pci_read_config_word(pdev, 0x0a, &cc);
938 if (cc == PCI_CLASS_STORAGE_IDE)
939 scc_s = "IDE";
940 else if (cc == PCI_CLASS_STORAGE_SATA)
941 scc_s = "SATA";
942 else if (cc == PCI_CLASS_STORAGE_RAID)
943 scc_s = "RAID";
944 else
945 scc_s = "unknown";
946
947 ahci_print_info(host, scc_s);
948}
949
edc93052
TH		 950/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
951 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
952 * support PMP and the 4726 either directly exports the device
953 * attached to the first downstream port or acts as a hardware storage
954 * controller and emulate a single ATA device (can be RAID 0/1 or some
955 * other configuration).
956 *
957 * When there's no device attached to the first downstream port of the
958 * 4726, "Config Disk" appears, which is a pseudo ATA device to
959 * configure the 4726. However, ATA emulation of the device is very
960 * lame. It doesn't send signature D2H Reg FIS after the initial
961 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
962 *
963 * The following function works around the problem by always using
964 * hardreset on the port and not depending on receiving signature FIS
965 * afterward. If signature FIS isn't received soon, ATA class is
966 * assumed without follow-up softreset.
967 */
968static void ahci_p5wdh_workaround(struct ata_host *host)
969{
1bd06867 970 static const struct dmi_system_id sysids[] = {
edc93052
TH		 971 {
972 .ident = "P5W DH Deluxe",
973 .matches = {
974 DMI_MATCH(DMI_SYS_VENDOR,
975 "ASUSTEK COMPUTER INC"),
976 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
977 },
978 },
979 { }
980 };
981 struct pci_dev *pdev = to_pci_dev(host->dev);
982
983 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
984 dmi_check_system(sysids)) {
985 struct ata_port *ap = host->ports[1];
986
a44fec1f
JP		 987 dev_info(&pdev->dev,
988 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 989
990 ap->ops = &ahci_p5wdh_ops;
991 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
992 }
993}
994
cb85696d
JL		 995/*
996 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
997 * booting in BIOS compatibility mode. We restore the registers but not ID.
998 */
999static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1000{
1001 u32 val;
1002
1003 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1004
1005 pci_read_config_dword(pdev, 0xf8, &val);
1006 val |= 1 << 0x1b;
1007 /* the following changes the device ID, but appears not to affect function */
1008 /* val = (val & ~0xf0000000) | 0x80000000; */
1009 pci_write_config_dword(pdev, 0xf8, val);
1010
1011 pci_read_config_dword(pdev, 0x54c, &val);
1012 val |= 1 << 0xc;
1013 pci_write_config_dword(pdev, 0x54c, val);
1014
1015 pci_read_config_dword(pdev, 0x4a4, &val);
1016 val &= 0xff;
1017 val |= 0x01060100;
1018 pci_write_config_dword(pdev, 0x4a4, val);
1019
1020 pci_read_config_dword(pdev, 0x54c, &val);
1021 val &= ~(1 << 0xc);
1022 pci_write_config_dword(pdev, 0x54c, val);
1023
1024 pci_read_config_dword(pdev, 0xf8, &val);
1025 val &= ~(1 << 0x1b);
1026 pci_write_config_dword(pdev, 0xf8, val);
1027}
1028
1029static bool is_mcp89_apple(struct pci_dev *pdev)
1030{
1031 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1032 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1033 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1034 pdev->subsystem_device == 0xcb89;
1035}
1036
2fcad9d2
TH		 1037/* only some SB600 ahci controllers can do 64bit DMA */
1038static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1039{
1040 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1041 /*
1042 * The oldest version known to be broken is 0901 and
1043 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1044 * Enable 64bit DMA on 1501 and anything newer.
1045 *
03d783bf
TH		 1046 * Please read bko#9412 for more info.
1047 */
58a09b38
SH		 1048 {
1049 .ident = "ASUS M2A-VM",
1050 .matches = {
1051 DMI_MATCH(DMI_BOARD_VENDOR,
1052 "ASUSTeK Computer INC."),
1053 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1054 },
03d783bf 1055 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1056 },
e65cc194
MN		 1057 /*
1058 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1059 * support 64bit DMA.
1060 *
1061 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1062 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1063 * This spelling mistake was fixed in BIOS version 1.5, so
1064 * 1.5 and later have the Manufacturer as
1065 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1066 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1067 *
1068 * BIOS versions earlier than 1.9 had a Board Product Name
1069 * DMI field of "MS-7376". This was changed to be
1070 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1071 * match on DMI_BOARD_NAME of "MS-7376".
1072 */
1073 {
1074 .ident = "MSI K9A2 Platinum",
1075 .matches = {
1076 DMI_MATCH(DMI_BOARD_VENDOR,
1077 "MICRO-STAR INTER"),
1078 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1079 },
1080 },
ff0173c1
MN		 1081 /*
1082 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1083 * 64bit DMA.
1084 *
1085 * This board also had the typo mentioned above in the
1086 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1087 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1088 */
1089 {
1090 .ident = "MSI K9AGM2",
1091 .matches = {
1092 DMI_MATCH(DMI_BOARD_VENDOR,
1093 "MICRO-STAR INTER"),
1094 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1095 },
1096 },
3c4aa91f
MN		 1097 /*
1098 * All BIOS versions for the Asus M3A support 64bit DMA.
1099 * (all release versions from 0301 to 1206 were tested)
1100 */
1101 {
1102 .ident = "ASUS M3A",
1103 .matches = {
1104 DMI_MATCH(DMI_BOARD_VENDOR,
1105 "ASUSTeK Computer INC."),
1106 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1107 },
1108 },
58a09b38
SH		 1109 { }
1110 };
03d783bf 1111 const struct dmi_system_id *match;
2fcad9d2
TH		 1112 int year, month, date;
1113 char buf[9];
58a09b38 1114
03d783bf 1115 match = dmi_first_match(sysids);
58a09b38 1116 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1117 !match)
58a09b38
SH		 1118 return false;
1119
e65cc194
MN		 1120 if (!match->driver_data)
1121 goto enable_64bit;
1122
2fcad9d2
TH		 1123 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1124 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1125
e65cc194
MN		 1126 if (strcmp(buf, match->driver_data) >= 0)
1127 goto enable_64bit;
1128 else {
a44fec1f
JP		 1129 dev_warn(&pdev->dev,
1130 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1131 match->ident);
2fcad9d2
TH		 1132 return false;
1133 }
e65cc194
MN		 1134
1135enable_64bit:
a44fec1f 1136 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1137 return true;
58a09b38
SH		 1138}
1139
1fd68434
RW		 1140static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1141{
1142 static const struct dmi_system_id broken_systems[] = {
1143 {
1144 .ident = "HP Compaq nx6310",
1145 .matches = {
1146 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1147 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1148 },
1149 /* PCI slot number of the controller */
1150 .driver_data = (void *)0x1FUL,
1151 },
d2f9c061
MR		 1152 {
1153 .ident = "HP Compaq 6720s",
1154 .matches = {
1155 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1157 },
1158 /* PCI slot number of the controller */
1159 .driver_data = (void *)0x1FUL,
1160 },
1fd68434
RW		 1161
1162 { } /* terminate list */
1163 };
1164 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1165
1166 if (dmi) {
1167 unsigned long slot = (unsigned long)dmi->driver_data;
1168 /* apply the quirk only to on-board controllers */
1169 return slot == PCI_SLOT(pdev->devfn);
1170 }
1171
1172 return false;
1173}
1174
9b10ae86
TH		 1175static bool ahci_broken_suspend(struct pci_dev *pdev)
1176{
1177 static const struct dmi_system_id sysids[] = {
1178 /*
1179 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1180 * to the harddisk doesn't become online after
1181 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1182 *
1183 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1184 *
1185 * Use dates instead of versions to match as HP is
1186 * apparently recycling both product and version
1187 * strings.
1188 *
1189 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1190 */
1191 {
1192 .ident = "dv4",
1193 .matches = {
1194 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1195 DMI_MATCH(DMI_PRODUCT_NAME,
1196 "HP Pavilion dv4 Notebook PC"),
1197 },
9deb3431 1198 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1199 },
1200 {
1201 .ident = "dv5",
1202 .matches = {
1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1204 DMI_MATCH(DMI_PRODUCT_NAME,
1205 "HP Pavilion dv5 Notebook PC"),
1206 },
9deb3431 1207 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1208 },
1209 {
1210 .ident = "dv6",
1211 .matches = {
1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1213 DMI_MATCH(DMI_PRODUCT_NAME,
1214 "HP Pavilion dv6 Notebook PC"),
1215 },
9deb3431 1216 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1217 },
1218 {
1219 .ident = "HDX18",
1220 .matches = {
1221 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1222 DMI_MATCH(DMI_PRODUCT_NAME,
1223 "HP HDX18 Notebook PC"),
1224 },
9deb3431 1225 .driver_data = "20090430", /* F.23 */
9b10ae86 1226 },
cedc9bf9
TH		 1227 /*
1228 * Acer eMachines G725 has the same problem. BIOS
1229 * V1.03 is known to be broken. V3.04 is known to
25985edc 1230 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1231 * that we don't have much idea about. For now,
1232 * blacklist anything older than V3.04.
9deb3431
TH		 1233 *
1234 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1235 */
1236 {
1237 .ident = "G725",
1238 .matches = {
1239 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1240 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1241 },
9deb3431 1242 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1243 },
9b10ae86
TH		 1244 { } /* terminate list */
1245 };
1246 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1247 int year, month, date;
1248 char buf[9];
9b10ae86
TH		 1249
1250 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1251 return false;
1252
9deb3431
TH		 1253 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1254 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1255
9deb3431 1256 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1257}
1258
240630e6
HG		 1259static bool ahci_broken_lpm(struct pci_dev *pdev)
1260{
1261 static const struct dmi_system_id sysids[] = {
1262 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1263 {
1264 .matches = {
1265 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1266 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1267 },
1268 .driver_data = "20180406", /* 1.31 */
1269 },
1270 {
1271 .matches = {
1272 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1273 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1274 },
1275 .driver_data = "20180420", /* 1.28 */
1276 },
1277 {
1278 .matches = {
1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1281 },
1282 .driver_data = "20180315", /* 1.33 */
1283 },
1284 {
1285 .matches = {
1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1288 },
1289 /*
1290 * Note date based on release notes, 2.35 has been
1291 * reported to be good, but I've been unable to get
1292 * a hold of the reporter to get the DMI BIOS date.
1293 * TODO: fix this.
1294 */
1295 .driver_data = "20180310", /* 2.35 */
1296 },
1297 { } /* terminate list */
1298 };
1299 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1300 int year, month, date;
1301 char buf[9];
1302
1303 if (!dmi)
1304 return false;
1305
1306 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1307 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1308
1309 return strcmp(buf, dmi->driver_data) < 0;
1310}
1311
5594639a
TH		 1312static bool ahci_broken_online(struct pci_dev *pdev)
1313{
1314#define ENCODE_BUSDEVFN(bus, slot, func) \
1315 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1316 static const struct dmi_system_id sysids[] = {
1317 /*
1318 * There are several gigabyte boards which use
1319 * SIMG5723s configured as hardware RAID. Certain
1320 * 5723 firmware revisions shipped there keep the link
1321 * online but fail to answer properly to SRST or
1322 * IDENTIFY when no device is attached downstream
1323 * causing libata to retry quite a few times leading
1324 * to excessive detection delay.
1325 *
1326 * As these firmwares respond to the second reset try
1327 * with invalid device signature, considering unknown
1328 * sig as offline works around the problem acceptably.
1329 */
1330 {
1331 .ident = "EP45-DQ6",
1332 .matches = {
1333 DMI_MATCH(DMI_BOARD_VENDOR,
1334 "Gigabyte Technology Co., Ltd."),
1335 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1336 },
1337 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1338 },
1339 {
1340 .ident = "EP45-DS5",
1341 .matches = {
1342 DMI_MATCH(DMI_BOARD_VENDOR,
1343 "Gigabyte Technology Co., Ltd."),
1344 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1345 },
1346 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1347 },
1348 { } /* terminate list */
1349 };
1350#undef ENCODE_BUSDEVFN
1351 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1352 unsigned int val;
1353
1354 if (!dmi)
1355 return false;
1356
1357 val = (unsigned long)dmi->driver_data;
1358
1359 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1360}
1361
0cf4a7d6
JP		 1362static bool ahci_broken_devslp(struct pci_dev *pdev)
1363{
1364 /* device with broken DEVSLP but still showing SDS capability */
1365 static const struct pci_device_id ids[] = {
1366 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1367 {}
1368 };
1369
1370 return pci_match_id(ids, pdev);
1371}
1372
8e513217 1373#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1374static void ahci_gtf_filter_workaround(struct ata_host *host)
1375{
1376 static const struct dmi_system_id sysids[] = {
1377 /*
1378 * Aspire 3810T issues a bunch of SATA enable commands
1379 * via _GTF including an invalid one and one which is
1380 * rejected by the device. Among the successful ones
1381 * is FPDMA non-zero offset enable which when enabled
1382 * only on the drive side leads to NCQ command
1383 * failures. Filter it out.
1384 */
1385 {
1386 .ident = "Aspire 3810T",
1387 .matches = {
1388 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1389 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1390 },
1391 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1392 },
1393 { }
1394 };
1395 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1396 unsigned int filter;
1397 int i;
1398
1399 if (!dmi)
1400 return;
1401
1402 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1403 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1404 filter, dmi->ident);
f80ae7e4
TH		 1405
1406 for (i = 0; i < host->n_ports; i++) {
1407 struct ata_port *ap = host->ports[i];
1408 struct ata_link *link;
1409 struct ata_device *dev;
1410
1411 ata_for_each_link(link, ap, EDGE)
1412 ata_for_each_dev(dev, link, ALL)
1413 dev->gtf_filter |= filter;
1414 }
1415}
8e513217
MT		 1416#else
1417static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1418{}
1419#endif
f80ae7e4 1420
8bfd1743
SC		 1421/*
1422 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1423 * as DUMMY, or detected but eventually get a "link down" and never get up
1424 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1425 * port_map may hold a value of 0x00.
1426 *
1427 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1428 * and can significantly reduce the occurrence of the problem.
1429 *
1430 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1431 */
1432static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1433 struct pci_dev *pdev)
1434{
1435 static const struct dmi_system_id sysids[] = {
1436 {
1437 .ident = "Acer Switch Alpha 12",
1438 .matches = {
1439 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1440 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1441 },
1442 },
1443 { }
1444 };
1445
1446 if (dmi_check_system(sysids)) {
1447 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1448 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1449 hpriv->port_map = 0x7;
1450 hpriv->cap = 0xC734FF02;
1451 }
1452 }
1453}
1454
d243bed3
TC		 1455#ifdef CONFIG_ARM64
1456/*
1457 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1458 * Workaround is to make sure all pending IRQs are served before leaving
1459 * handler.
1460 */
1461static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1462{
1463 struct ata_host *host = dev_instance;
1464 struct ahci_host_priv *hpriv;
1465 unsigned int rc = 0;
1466 void __iomem *mmio;
1467 u32 irq_stat, irq_masked;
1468 unsigned int handled = 1;
1469
1470 VPRINTK("ENTER\n");
1471 hpriv = host->private_data;
1472 mmio = hpriv->mmio;
1473 irq_stat = readl(mmio + HOST_IRQ_STAT);
1474 if (!irq_stat)
1475 return IRQ_NONE;
1476
1477 do {
1478 irq_masked = irq_stat & hpriv->port_map;
1479 spin_lock(&host->lock);
1480 rc = ahci_handle_port_intr(host, irq_masked);
1481 if (!rc)
1482 handled = 0;
1483 writel(irq_stat, mmio + HOST_IRQ_STAT);
1484 irq_stat = readl(mmio + HOST_IRQ_STAT);
1485 spin_unlock(&host->lock);
1486 } while (irq_stat);
1487 VPRINTK("EXIT\n");
1488
1489 return IRQ_RETVAL(handled);
1490}
1491#endif
1492
aecec8b6
CH		 1493static void ahci_remap_check(struct pci_dev *pdev, int bar,
1494 struct ahci_host_priv *hpriv)
1495{
1496 int i, count = 0;
1497 u32 cap;
1498
1499 /*
1500 * Check if this device might have remapped nvme devices.
1501 */
1502 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1503 pci_resource_len(pdev, bar) < SZ_512K ||
1504 bar != AHCI_PCI_BAR_STANDARD ||
1505 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1506 return;
1507
1508 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1509 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1510 if ((cap & (1 << i)) == 0)
1511 continue;
1512 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1513 != PCI_CLASS_STORAGE_EXPRESS)
1514 continue;
1515
1516 /* We've found a remapped device */
1517 count++;
1518 }
1519
1520 if (!count)
1521 return;
1522
1523 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
f723fa4e
CH		 1524 dev_warn(&pdev->dev,
1525 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1526
1527 /*
1528 * Don't rely on the msi-x capability in the remap case,
1529 * share the legacy interrupt across ahci and remapped devices.
1530 */
1531 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1532}
1533
0b9e2988 1534static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1535{
0b9e2988 1536 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1537}
1538
a1c82311
RR		 1539static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1540 struct ahci_host_priv *hpriv)
5ca72c4f 1541{
0b9e2988 1542 int nvec;
5ca72c4f 1543
7b92b4f6 1544 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1545 return -ENODEV;
7b92b4f6 1546
7b92b4f6
AG		 1547 /*
1548 * If number of MSIs is less than number of ports then Sharing Last
1549 * Message mode could be enforced. In this case assume that advantage
1550 * of multipe MSIs is negated and use single MSI mode instead.
1551 */
17a51f12
CH		 1552 if (n_ports > 1) {
1553 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1554 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1555 if (nvec > 0) {
1556 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1557 hpriv->get_irq_vector = ahci_get_irq_vector;
1558 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1559 return nvec;
1560 }
5ca72c4f 1561
17a51f12
CH		 1562 /*
1563 * Fallback to single MSI mode if the controller
1564 * enforced MRSM mode.
1565 */
1566 printk(KERN_INFO
1567 "ahci: MRSM is on, fallback to single MSI\n");
1568 pci_free_irq_vectors(pdev);
1569 }
a478b097 1570 }
d684a90d 1571
0b9e2988
CH		 1572 /*
1573 * If the host is not capable of supporting per-port vectors, fall
1574 * back to single MSI before finally attempting single MSI-X.
1575 */
1576 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1577 if (nvec == 1)
ee2aad42 1578 return nvec;
0b9e2988 1579 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1580}
1581
b1a9585c
SP		 1582static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1583 struct ahci_host_priv *hpriv)
1584{
1585 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1586
1587
1588 /* Ignore processing for non mobile platforms */
1589 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1590 return;
1591
1592 /* user modified policy via module param */
1593 if (mobile_lpm_policy != -1) {
1594 policy = mobile_lpm_policy;
1595 goto update_policy;
1596 }
1597
1598#ifdef CONFIG_ACPI
1599 if (policy > ATA_LPM_MED_POWER &&
1600 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1601 if (hpriv->cap & HOST_CAP_PART)
1602 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1603 else if (hpriv->cap & HOST_CAP_SSC)
1604 policy = ATA_LPM_MIN_POWER;
1605 }
1606#endif
1607
1608update_policy:
1609 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1610 ap->target_lpm_policy = policy;
1611}
1612
c312ef17
DW		 1613static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1614{
1615 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1616 u16 tmp16;
1617
1618 /*
1619 * Only apply the 6-port PCS quirk for known legacy platforms.
1620 */
1621 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1622 return;
09d6ac8d
DW		 1623
1624 /* Skip applying the quirk on Denverton and beyond */
1625 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
c312ef17
DW		 1626 return;
1627
1628 /*
1629 * port_map is determined from PORTS_IMPL PCI register which is
1630 * implemented as write or write-once register. If the register
1631 * isn't programmed, ahci automatically generates it from number
1632 * of ports, which is good enough for PCS programming. It is
1633 * otherwise expected that platform firmware enables the ports
1634 * before the OS boots.
1635 */
1636 pci_read_config_word(pdev, PCS_6, &tmp16);
1637 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1638 tmp16 |= hpriv->port_map;
1639 pci_write_config_word(pdev, PCS_6, tmp16);
1640 }
1641}
1642
24dc5f33 1643static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1644{
e297d99e
TH		 1645 unsigned int board_id = ent->driver_data;
1646 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1647 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1648 struct device *dev = &pdev->dev;
1da177e4 1649 struct ahci_host_priv *hpriv;
4447d351 1650 struct ata_host *host;
c3ebd6a9 1651 int n_ports, i, rc;
318893e1 1652 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1653
1654 VPRINTK("ENTER\n");
1655
b429dd59 1656 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1657
06296a1e 1658 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1659
5b66c829
AC		 1660 /* The AHCI driver can only drive the SATA ports, the PATA driver
1661 can drive them all so if both drivers are selected make sure
1662 AHCI stays out of the way */
1663 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1664 return -ENODEV;
1665
cb85696d
JL		 1666 /* Apple BIOS on MCP89 prevents us using AHCI */
1667 if (is_mcp89_apple(pdev))
1668 ahci_mcp89_apple_enable(pdev);
c6353b45 1669
7a02267e
MN		 1670 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1671 * At the moment, we can only use the AHCI mode. Let the users know
1672 * that for SAS drives they're out of luck.
1673 */
1674 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1675 dev_info(&pdev->dev,
1676 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1677
b7ae128d 1678 /* Some devices use non-standard BARs */
318893e1
AR		 1679 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1680 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1681 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1682 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1683 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1684 if (pdev->device == 0xa01c)
1685 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1686 if (pdev->device == 0xa084)
1687 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
e49bd683
TY		 1688 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1689 if (pdev->device == 0x7a08)
1690 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
b1314e3f 1691 }
318893e1 1692
4447d351 1693 /* acquire resources */
24dc5f33 1694 rc = pcim_enable_device(pdev);
1da177e4
LT		 1695 if (rc)
1696 return rc;
1697
c4f7792c
TH		 1698 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1699 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1700 u8 map;
1701
1702 /* ICH6s share the same PCI ID for both piix and ahci
1703 * modes. Enabling ahci mode while MAP indicates
1704 * combined mode is a bad idea. Yield to ata_piix.
1705 */
1706 pci_read_config_byte(pdev, ICH_MAP, &map);
1707 if (map & 0x3) {
a44fec1f
JP		 1708 dev_info(&pdev->dev,
1709 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1710 return -ENODEV;
1711 }
1712 }
1713
6fec8871
PB		 1714 /* AHCI controllers often implement SFF compatible interface.
1715 * Grab all PCI BARs just in case.
1716 */
1717 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1718 if (rc == -EBUSY)
1719 pcim_pin_device(pdev);
1720 if (rc)
1721 return rc;
1722
24dc5f33
TH		 1723 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1724 if (!hpriv)
1725 return -ENOMEM;
417a1a6d
TH		 1726 hpriv->flags |= (unsigned long)pi.private_data;
1727
e297d99e
TH		 1728 /* MCP65 revision A1 and A2 can't do MSI */
1729 if (board_id == board_ahci_mcp65 &&
1730 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1731 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1732
e427fe04
SH		 1733 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1734 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1735 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1736
2fcad9d2
TH		 1737 /* only some SB600s can do 64bit DMA */
1738 if (ahci_sb600_enable_64bit(pdev))
1739 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1740
318893e1 1741 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1742
aecec8b6
CH		 1743 /* detect remapped nvme devices */
1744 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1745
0cf4a7d6
JP		 1746 /* must set flag prior to save config in order to take effect */
1747 if (ahci_broken_devslp(pdev))
1748 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1749
d243bed3
TC		 1750#ifdef CONFIG_ARM64
1751 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1752 hpriv->irq_handler = ahci_thunderx_irq_handler;
1753#endif
1754
4447d351 1755 /* save initial config */
394d6e53 1756 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1757
c312ef17
DW		 1758 /*
1759 * If platform firmware failed to enable ports, try to enable
1760 * them here.
1761 */
1762 ahci_intel_pcs_quirk(pdev, hpriv);
1763
4447d351 1764 /* prepare host */
453d3131
RH		 1765 if (hpriv->cap & HOST_CAP_NCQ) {
1766 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1767 /*
1768 * Auto-activate optimization is supposed to be
1769 * supported on all AHCI controllers indicating NCQ
1770 * capability, but it seems to be broken on some
1771 * chipsets including NVIDIAs.
1772 */
1773 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1774 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1775
1776 /*
1777 * All AHCI controllers should be forward-compatible
1778 * with the new auxiliary field. This code should be
1779 * conditionalized if any buggy AHCI controllers are
1780 * encountered.
1781 */
1782 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1783 }
1da177e4 1784
7d50b60b
TH		 1785 if (hpriv->cap & HOST_CAP_PMP)
1786 pi.flags |= ATA_FLAG_PMP;
1787
0cbb0e77 1788 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1789
1fd68434
RW		 1790 if (ahci_broken_system_poweroff(pdev)) {
1791 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1792 dev_info(&pdev->dev,
1793 "quirky BIOS, skipping spindown on poweroff\n");
1794 }
1795
240630e6
HG		 1796 if (ahci_broken_lpm(pdev)) {
1797 pi.flags |= ATA_FLAG_NO_LPM;
1798 dev_warn(&pdev->dev,
1799 "BIOS update required for Link Power Management support\n");
1800 }
1801
9b10ae86
TH		 1802 if (ahci_broken_suspend(pdev)) {
1803 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1804 dev_warn(&pdev->dev,
1805 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1806 }
1807
5594639a
TH		 1808 if (ahci_broken_online(pdev)) {
1809 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1810 dev_info(&pdev->dev,
1811 "online status unreliable, applying workaround\n");
1812 }
1813
8bfd1743
SC		 1814
1815 /* Acer SA5-271 workaround modifies private_data */
1816 acer_sa5_271_workaround(hpriv, pdev);
1817
837f5f8f
TH		 1818 /* CAP.NP sometimes indicate the index of the last enabled
1819 * port, at other times, that of the last possible port, so
1820 * determining the maximum port number requires looking at
1821 * both CAP.NP and port_map.
1822 */
1823 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1824
1825 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1826 if (!host)
1827 return -ENOMEM;
4447d351 1828 host->private_data = hpriv;
0b9e2988
CH		 1829
1830 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1831 /* legacy intx interrupts */
1832 pci_intx(pdev, 1);
1833 }
0ce57f8a 1834 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1835
f3d7f23f 1836 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1837 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1838 else
d2782d96 1839 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1840
18f7ba4c
KCA		 1841 if (pi.flags & ATA_FLAG_EM)
1842 ahci_reset_em(host);
1843
4447d351 1844 for (i = 0; i < host->n_ports; i++) {
dab632e8 1845 struct ata_port *ap = host->ports[i];
4447d351 1846
318893e1
AR		 1847 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1848 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1849 0x100 + ap->port_no * 0x80, "port");
1850
18f7ba4c
KCA		 1851 /* set enclosure management message type */
1852 if (ap->flags & ATA_FLAG_EM)
008dbd61 1853 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c 1854
b1a9585c 1855 ahci_update_initial_lpm_policy(ap, hpriv);
18f7ba4c 1856
dab632e8 1857 /* disabled/not-implemented port */
350756f6 1858 if (!(hpriv->port_map & (1 << i)))
dab632e8 1859 ap->ops = &ata_dummy_port_ops;
4447d351 1860 }
d447df14 1861
edc93052
TH		 1862 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1863 ahci_p5wdh_workaround(host);
1864
f80ae7e4
TH		 1865 /* apply gtf filter quirk */
1866 ahci_gtf_filter_workaround(host);
1867
4447d351
TH		 1868 /* initialize adapter */
1869 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1870 if (rc)
24dc5f33 1871 return rc;
1da177e4 1872
c312ef17 1873 rc = ahci_reset_controller(host);
4447d351
TH		 1874 if (rc)
1875 return rc;
1da177e4 1876
781d6550 1877 ahci_pci_init_controller(host);
439fcaec 1878 ahci_pci_print_info(host);
1da177e4 1879
4447d351 1880 pci_set_master(pdev);
5ca72c4f 1881
02e53293
MW		 1882 rc = ahci_host_activate(host, &ahci_sht);
1883 if (rc)
1884 return rc;
1885
1886 pm_runtime_put_noidle(&pdev->dev);
1887 return 0;
1888}
1889
10a663a1
PK		 1890static void ahci_shutdown_one(struct pci_dev *pdev)
1891{
1892 ata_pci_shutdown_one(pdev);
1893}
1894
02e53293
MW		 1895static void ahci_remove_one(struct pci_dev *pdev)
1896{
1897 pm_runtime_get_noresume(&pdev->dev);
1898 ata_pci_remove_one(pdev);
907f4678 1899}
1da177e4 1900
2fc75da0 1901module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1902
1903MODULE_AUTHOR("Jeff Garzik");
1904MODULE_DESCRIPTION("AHCI SATA low-level driver");
1905MODULE_LICENSE("GPL");
1906MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1907MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)