projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix common misspellings
[linux-2.6-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
bd17243a
SH		 107static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111};
112
417a1a6d
TH		 113#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
98ac62de 115static const struct ata_port_info ahci_port_info[] = {
441577ef 116 /* by features */
4da646b7 117 [board_ahci] =
1da177e4 118 {
1188c0d8 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
1da177e4
LT		 122 .port_ops = &ahci_ops,
123 },
441577ef 124 [board_ahci_ign_iferr] =
bf2af2a2 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
441577ef 130 .port_ops = &ahci_ops,
bf2af2a2 131 },
441577ef 132 [board_ahci_nosntf] =
41669553 133 {
441577ef 134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 135 .flags = AHCI_FLAG_COMMON,
14bdef98 136 .pio_mask = ATA_PIO4,
469248ab 137 .udma_mask = ATA_UDMA6,
41669553
TH		 138 .port_ops = &ahci_ops,
139 },
5f173107
TH		 140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
441577ef
TH		 148 /* by chipsets */
149 [board_ahci_mcp65] =
55a61604 150 {
83f2b963
TH		 151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 169 .flags = AHCI_FLAG_COMMON,
14bdef98 170 .pio_mask = ATA_PIO4,
469248ab 171 .udma_mask = ATA_UDMA6,
441577ef 172 .port_ops = &ahci_ops,
55a61604 173 },
4da646b7 174 [board_ahci_mv] =
cd70c266 175 {
417a1a6d 176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 179 .pio_mask = ATA_PIO4,
cd70c266
JG		 180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
441577ef 183 [board_ahci_sb600] =
e39fc8c9 184 {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
bd17243a 191 .port_ops = &ahci_sb600_ops,
e39fc8c9 192 },
441577ef 193 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_sb600_ops,
aa431dd3 200 },
441577ef 201 [board_ahci_vt8251] =
1b677afd 202 {
441577ef 203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
441577ef 207 .port_ops = &ahci_vt8251_ops,
1b677afd 208 },
1da177e4
LT		 209};
210
3b7d697d 211static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 212 /* Intel */
54bb3a94
JG		 213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
fe7fa31a 264
e34bb370
TH		 265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 268
269 /* ATI */
c65ec1c2 270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 277
e2dd90b1 278 /* AMD */
5deab536 279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283
fe7fa31a 284 /* VIA */
54bb3a94 285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 287
288 /* NVIDIA */
e297d99e
TH		 289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 373
95916edd 374 /* SiS */
20e2de4a
TH		 375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 378
cd70c266
JG		 379 /* Marvell */
380 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 381 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 382 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 383 .class = PCI_CLASS_STORAGE_SATA_AHCI,
384 .class_mask = 0xffffff,
5f173107 385 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 386 { PCI_DEVICE(0x1b4b, 0x9125),
387 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 388 { PCI_DEVICE(0x1b4b, 0x91a3),
389 .driver_data = board_ahci_yes_fbs },
cd70c266 390
c77a036b
MN		 391 /* Promise */
392 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
393
415ae2b5
JG		 394 /* Generic, PCI class code for AHCI */
395 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 396 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 397
1da177e4
LT		 398 { } /* terminate list */
399};
400
401
402static struct pci_driver ahci_pci_driver = {
403 .name = DRV_NAME,
404 .id_table = ahci_pci_tbl,
405 .probe = ahci_init_one,
24dc5f33 406 .remove = ata_pci_remove_one,
438ac6d5 407#ifdef CONFIG_PM
c1332875 408 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 409 .resume = ahci_pci_device_resume,
410#endif
411};
1da177e4 412
365cfa1e
AV		 413#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
414static int marvell_enable;
415#else
416static int marvell_enable = 1;
417#endif
418module_param(marvell_enable, int, 0644);
419MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 420
1da177e4 421
365cfa1e
AV		 422static void ahci_pci_save_initial_config(struct pci_dev *pdev,
423 struct ahci_host_priv *hpriv)
424{
425 unsigned int force_port_map = 0;
426 unsigned int mask_port_map = 0;
67846b30 427
365cfa1e
AV		 428 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
429 dev_info(&pdev->dev, "JMB361 has only one port\n");
430 force_port_map = 1;
1da177e4
LT		 431 }
432
365cfa1e
AV		 433 /*
434 * Temporary Marvell 6145 hack: PATA port presence
435 * is asserted through the standard AHCI port
436 * presence register, as bit 4 (counting from 0)
d28f87aa 437 */
365cfa1e
AV		 438 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
439 if (pdev->device == 0x6121)
440 mask_port_map = 0x3;
441 else
442 mask_port_map = 0xf;
443 dev_info(&pdev->dev,
444 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
445 }
1da177e4 446
365cfa1e
AV		 447 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
448 mask_port_map);
1da177e4
LT		 449}
450
365cfa1e 451static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 452{
365cfa1e 453 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 454
365cfa1e 455 ahci_reset_controller(host);
1da177e4 456
365cfa1e
AV		 457 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
458 struct ahci_host_priv *hpriv = host->private_data;
459 u16 tmp16;
d6ef3153 460
365cfa1e
AV		 461 /* configure PCS */
462 pci_read_config_word(pdev, 0x92, &tmp16);
463 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
464 tmp16 |= hpriv->port_map;
465 pci_write_config_word(pdev, 0x92, tmp16);
466 }
d6ef3153
SH		 467 }
468
1da177e4
LT		 469 return 0;
470}
471
365cfa1e 472static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 473{
365cfa1e
AV		 474 struct ahci_host_priv *hpriv = host->private_data;
475 struct pci_dev *pdev = to_pci_dev(host->dev);
476 void __iomem *port_mmio;
78cd52d0 477 u32 tmp;
365cfa1e 478 int mv;
78cd52d0 479
365cfa1e
AV		 480 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
481 if (pdev->device == 0x6121)
482 mv = 2;
483 else
484 mv = 4;
485 port_mmio = __ahci_port_base(host, mv);
78cd52d0 486
365cfa1e 487 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 488
365cfa1e
AV		 489 /* clear port IRQ */
490 tmp = readl(port_mmio + PORT_IRQ_STAT);
491 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
492 if (tmp)
493 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 494 }
495
365cfa1e 496 ahci_init_controller(host);
edc93052
TH		 497}
498
365cfa1e 499static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 500{
365cfa1e
AV		 501 void __iomem *port_mmio = ahci_port_base(link->ap);
502 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
503 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
504
505 /*
506 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
507 * which can save timeout delay.
508 */
509 if (irq_status & PORT_IRQ_BAD_PMP)
510 return -EIO;
78cd52d0 511
365cfa1e 512 return ata_check_ready(status);
78cd52d0
TH		 513}
514
365cfa1e
AV		 515static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
516 unsigned long deadline)
d6ef3153 517{
365cfa1e 518 struct ata_port *ap = link->ap;
d6ef3153 519 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 520 int pmp = sata_srst_pmp(link);
d6ef3153 521 int rc;
365cfa1e 522 u32 irq_sts;
d6ef3153 523
365cfa1e 524 DPRINTK("ENTER\n");
d6ef3153 525
365cfa1e
AV		 526 rc = ahci_do_softreset(link, class, pmp, deadline,
527 ahci_sb600_check_ready);
d6ef3153 528
365cfa1e
AV		 529 /*
530 * Soft reset fails on some ATI chips with IPMS set when PMP
531 * is enabled but SATA HDD/ODD is connected to SATA port,
532 * do soft reset again to port 0.
533 */
534 if (rc == -EIO) {
535 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
536 if (irq_sts & PORT_IRQ_BAD_PMP) {
537 ata_link_printk(link, KERN_WARNING,
538 "applying SB600 PMP SRST workaround "
539 "and retrying\n");
540 rc = ahci_do_softreset(link, class, 0, deadline,
541 ahci_check_ready);
542 }
543 }
d6ef3153 544
365cfa1e 545 return rc;
d6ef3153
SH		 546}
547
365cfa1e
AV		 548static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline)
d6ef3153 550{
365cfa1e
AV		 551 struct ata_port *ap = link->ap;
552 bool online;
d6ef3153
SH		 553 int rc;
554
365cfa1e 555 DPRINTK("ENTER\n");
d6ef3153 556
365cfa1e 557 ahci_stop_engine(ap);
d6ef3153 558
365cfa1e
AV		 559 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
560 deadline, &online, NULL);
d6ef3153
SH		 561
562 ahci_start_engine(ap);
d6ef3153 563
365cfa1e 564 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 565
365cfa1e
AV		 566 /* vt8251 doesn't clear BSY on signature FIS reception,
567 * request follow-up softreset.
568 */
569 return online ? -EAGAIN : rc;
7d50b60b
TH		 570}
571
365cfa1e
AV		 572static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline)
7d50b60b 574{
365cfa1e 575 struct ata_port *ap = link->ap;
1c954a4d 576 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 577 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
578 struct ata_taskfile tf;
579 bool online;
580 int rc;
7d50b60b 581
365cfa1e 582 ahci_stop_engine(ap);
028a2596 583
365cfa1e
AV		 584 /* clear D2H reception area to properly wait for D2H FIS */
585 ata_tf_init(link->device, &tf);
586 tf.command = 0x80;
587 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 588
365cfa1e
AV		 589 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
590 deadline, &online, NULL);
028a2596 591
365cfa1e 592 ahci_start_engine(ap);
c1332875 593
365cfa1e
AV		 594 /* The pseudo configuration device on SIMG4726 attached to
595 * ASUS P5W-DH Deluxe doesn't send signature FIS after
596 * hardreset if no device is attached to the first downstream
597 * port && the pseudo device locks up on SRST w/ PMP==0. To
598 * work around this, wait for !BSY only briefly. If BSY isn't
599 * cleared, perform CLO and proceed to IDENTIFY (achieved by
600 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
601 *
602 * Wait for two seconds. Devices attached to downstream port
603 * which can't process the following IDENTIFY after this will
604 * have to be reset again. For most cases, this should
605 * suffice while making probing snappish enough.
606 */
607 if (online) {
608 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
609 ahci_check_ready);
610 if (rc)
611 ahci_kick_engine(ap);
c1332875 612 }
c1332875
TH		 613 return rc;
614}
615
365cfa1e 616#ifdef CONFIG_PM
c1332875
TH		 617static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
618{
cca3974e 619 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 620 struct ahci_host_priv *hpriv = host->private_data;
d8993349 621 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 622 u32 ctl;
623
9b10ae86
TH		 624 if (mesg.event & PM_EVENT_SUSPEND &&
625 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
626 dev_printk(KERN_ERR, &pdev->dev,
627 "BIOS update required for suspend/resume\n");
628 return -EIO;
629 }
630
3a2d5b70 631 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 632 /* AHCI spec rev1.1 section 8.3.3:
633 * Software must disable interrupts prior to requesting a
634 * transition of the HBA to D3 state.
635 */
636 ctl = readl(mmio + HOST_CTL);
637 ctl &= ~HOST_IRQ_EN;
638 writel(ctl, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
640 }
641
642 return ata_pci_device_suspend(pdev, mesg);
643}
644
645static int ahci_pci_device_resume(struct pci_dev *pdev)
646{
cca3974e 647 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 648 int rc;
649
553c4aa6
TH		 650 rc = ata_pci_device_do_resume(pdev);
651 if (rc)
652 return rc;
c1332875
TH		 653
654 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 655 rc = ahci_pci_reset_controller(host);
c1332875
TH		 656 if (rc)
657 return rc;
658
781d6550 659 ahci_pci_init_controller(host);
c1332875
TH		 660 }
661
cca3974e 662 ata_host_resume(host);
c1332875
TH		 663
664 return 0;
665}
438ac6d5 666#endif
c1332875 667
4447d351 668static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 669{
1da177e4 670 int rc;
1da177e4 671
1da177e4 672 if (using_dac &&
6a35528a
YH		 673 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
674 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 675 if (rc) {
284901a9 676 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 677 if (rc) {
a9524a76
JG		 678 dev_printk(KERN_ERR, &pdev->dev,
679 "64-bit DMA enable failed\n");
1da177e4
LT		 680 return rc;
681 }
682 }
1da177e4 683 } else {
284901a9 684 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 685 if (rc) {
a9524a76
JG		 686 dev_printk(KERN_ERR, &pdev->dev,
687 "32-bit DMA enable failed\n");
1da177e4
LT		 688 return rc;
689 }
284901a9 690 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 691 if (rc) {
a9524a76
JG		 692 dev_printk(KERN_ERR, &pdev->dev,
693 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 694 return rc;
695 }
696 }
1da177e4
LT		 697 return 0;
698}
699
439fcaec
AV		 700static void ahci_pci_print_info(struct ata_host *host)
701{
702 struct pci_dev *pdev = to_pci_dev(host->dev);
703 u16 cc;
704 const char *scc_s;
705
706 pci_read_config_word(pdev, 0x0a, &cc);
707 if (cc == PCI_CLASS_STORAGE_IDE)
708 scc_s = "IDE";
709 else if (cc == PCI_CLASS_STORAGE_SATA)
710 scc_s = "SATA";
711 else if (cc == PCI_CLASS_STORAGE_RAID)
712 scc_s = "RAID";
713 else
714 scc_s = "unknown";
715
716 ahci_print_info(host, scc_s);
717}
718
edc93052
TH		 719/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
720 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
721 * support PMP and the 4726 either directly exports the device
722 * attached to the first downstream port or acts as a hardware storage
723 * controller and emulate a single ATA device (can be RAID 0/1 or some
724 * other configuration).
725 *
726 * When there's no device attached to the first downstream port of the
727 * 4726, "Config Disk" appears, which is a pseudo ATA device to
728 * configure the 4726. However, ATA emulation of the device is very
729 * lame. It doesn't send signature D2H Reg FIS after the initial
730 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
731 *
732 * The following function works around the problem by always using
733 * hardreset on the port and not depending on receiving signature FIS
734 * afterward. If signature FIS isn't received soon, ATA class is
735 * assumed without follow-up softreset.
736 */
737static void ahci_p5wdh_workaround(struct ata_host *host)
738{
739 static struct dmi_system_id sysids[] = {
740 {
741 .ident = "P5W DH Deluxe",
742 .matches = {
743 DMI_MATCH(DMI_SYS_VENDOR,
744 "ASUSTEK COMPUTER INC"),
745 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
746 },
747 },
748 { }
749 };
750 struct pci_dev *pdev = to_pci_dev(host->dev);
751
752 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
753 dmi_check_system(sysids)) {
754 struct ata_port *ap = host->ports[1];
755
756 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
757 "Deluxe on-board SIMG4726 workaround\n");
758
759 ap->ops = &ahci_p5wdh_ops;
760 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
761 }
762}
763
2fcad9d2
TH		 764/* only some SB600 ahci controllers can do 64bit DMA */
765static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 766{
767 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 768 /*
769 * The oldest version known to be broken is 0901 and
770 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 771 * Enable 64bit DMA on 1501 and anything newer.
772 *
03d783bf
TH		 773 * Please read bko#9412 for more info.
774 */
58a09b38
SH		 775 {
776 .ident = "ASUS M2A-VM",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR,
779 "ASUSTeK Computer INC."),
780 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
781 },
03d783bf 782 .driver_data = "20071026", /* yyyymmdd */
58a09b38 783 },
e65cc194
MN		 784 /*
785 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
786 * support 64bit DMA.
787 *
788 * BIOS versions earlier than 1.5 had the Manufacturer DMI
789 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
790 * This spelling mistake was fixed in BIOS version 1.5, so
791 * 1.5 and later have the Manufacturer as
792 * "MICRO-STAR INTERNATIONAL CO.,LTD".
793 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
794 *
795 * BIOS versions earlier than 1.9 had a Board Product Name
796 * DMI field of "MS-7376". This was changed to be
797 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
798 * match on DMI_BOARD_NAME of "MS-7376".
799 */
800 {
801 .ident = "MSI K9A2 Platinum",
802 .matches = {
803 DMI_MATCH(DMI_BOARD_VENDOR,
804 "MICRO-STAR INTER"),
805 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
806 },
807 },
58a09b38
SH		 808 { }
809 };
03d783bf 810 const struct dmi_system_id *match;
2fcad9d2
TH		 811 int year, month, date;
812 char buf[9];
58a09b38 813
03d783bf 814 match = dmi_first_match(sysids);
58a09b38 815 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 816 !match)
58a09b38
SH		 817 return false;
818
e65cc194
MN		 819 if (!match->driver_data)
820 goto enable_64bit;
821
2fcad9d2
TH		 822 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
823 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 824
e65cc194
MN		 825 if (strcmp(buf, match->driver_data) >= 0)
826 goto enable_64bit;
827 else {
03d783bf
TH		 828 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
829 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 830 return false;
831 }
e65cc194
MN		 832
833enable_64bit:
834 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
835 match->ident);
836 return true;
58a09b38
SH		 837}
838
1fd68434
RW		 839static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
840{
841 static const struct dmi_system_id broken_systems[] = {
842 {
843 .ident = "HP Compaq nx6310",
844 .matches = {
845 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
846 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
847 },
848 /* PCI slot number of the controller */
849 .driver_data = (void *)0x1FUL,
850 },
d2f9c061
MR		 851 {
852 .ident = "HP Compaq 6720s",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
855 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
856 },
857 /* PCI slot number of the controller */
858 .driver_data = (void *)0x1FUL,
859 },
1fd68434
RW		 860
861 { } /* terminate list */
862 };
863 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
864
865 if (dmi) {
866 unsigned long slot = (unsigned long)dmi->driver_data;
867 /* apply the quirk only to on-board controllers */
868 return slot == PCI_SLOT(pdev->devfn);
869 }
870
871 return false;
872}
873
9b10ae86
TH		 874static bool ahci_broken_suspend(struct pci_dev *pdev)
875{
876 static const struct dmi_system_id sysids[] = {
877 /*
878 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
879 * to the harddisk doesn't become online after
880 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 881 *
882 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
883 *
884 * Use dates instead of versions to match as HP is
885 * apparently recycling both product and version
886 * strings.
887 *
888 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 889 */
890 {
891 .ident = "dv4",
892 .matches = {
893 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
894 DMI_MATCH(DMI_PRODUCT_NAME,
895 "HP Pavilion dv4 Notebook PC"),
896 },
9deb3431 897 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 898 },
899 {
900 .ident = "dv5",
901 .matches = {
902 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
903 DMI_MATCH(DMI_PRODUCT_NAME,
904 "HP Pavilion dv5 Notebook PC"),
905 },
9deb3431 906 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 907 },
908 {
909 .ident = "dv6",
910 .matches = {
911 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
912 DMI_MATCH(DMI_PRODUCT_NAME,
913 "HP Pavilion dv6 Notebook PC"),
914 },
9deb3431 915 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 916 },
917 {
918 .ident = "HDX18",
919 .matches = {
920 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
921 DMI_MATCH(DMI_PRODUCT_NAME,
922 "HP HDX18 Notebook PC"),
923 },
9deb3431 924 .driver_data = "20090430", /* F.23 */
9b10ae86 925 },
cedc9bf9
TH		 926 /*
927 * Acer eMachines G725 has the same problem. BIOS
928 * V1.03 is known to be broken. V3.04 is known to
25985edc 929 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 930 * that we don't have much idea about. For now,
931 * blacklist anything older than V3.04.
9deb3431
TH		 932 *
933 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 934 */
935 {
936 .ident = "G725",
937 .matches = {
938 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
939 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
940 },
9deb3431 941 .driver_data = "20091216", /* V3.04 */
cedc9bf9 942 },
9b10ae86
TH		 943 { } /* terminate list */
944 };
945 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 946 int year, month, date;
947 char buf[9];
9b10ae86
TH		 948
949 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
950 return false;
951
9deb3431
TH		 952 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
953 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 954
9deb3431 955 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 956}
957
5594639a
TH		 958static bool ahci_broken_online(struct pci_dev *pdev)
959{
960#define ENCODE_BUSDEVFN(bus, slot, func) \
961 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
962 static const struct dmi_system_id sysids[] = {
963 /*
964 * There are several gigabyte boards which use
965 * SIMG5723s configured as hardware RAID. Certain
966 * 5723 firmware revisions shipped there keep the link
967 * online but fail to answer properly to SRST or
968 * IDENTIFY when no device is attached downstream
969 * causing libata to retry quite a few times leading
970 * to excessive detection delay.
971 *
972 * As these firmwares respond to the second reset try
973 * with invalid device signature, considering unknown
974 * sig as offline works around the problem acceptably.
975 */
976 {
977 .ident = "EP45-DQ6",
978 .matches = {
979 DMI_MATCH(DMI_BOARD_VENDOR,
980 "Gigabyte Technology Co., Ltd."),
981 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
982 },
983 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
984 },
985 {
986 .ident = "EP45-DS5",
987 .matches = {
988 DMI_MATCH(DMI_BOARD_VENDOR,
989 "Gigabyte Technology Co., Ltd."),
990 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
991 },
992 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
993 },
994 { } /* terminate list */
995 };
996#undef ENCODE_BUSDEVFN
997 const struct dmi_system_id *dmi = dmi_first_match(sysids);
998 unsigned int val;
999
1000 if (!dmi)
1001 return false;
1002
1003 val = (unsigned long)dmi->driver_data;
1004
1005 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1006}
1007
8e513217 1008#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1009static void ahci_gtf_filter_workaround(struct ata_host *host)
1010{
1011 static const struct dmi_system_id sysids[] = {
1012 /*
1013 * Aspire 3810T issues a bunch of SATA enable commands
1014 * via _GTF including an invalid one and one which is
1015 * rejected by the device. Among the successful ones
1016 * is FPDMA non-zero offset enable which when enabled
1017 * only on the drive side leads to NCQ command
1018 * failures. Filter it out.
1019 */
1020 {
1021 .ident = "Aspire 3810T",
1022 .matches = {
1023 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1024 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1025 },
1026 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1027 },
1028 { }
1029 };
1030 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1031 unsigned int filter;
1032 int i;
1033
1034 if (!dmi)
1035 return;
1036
1037 filter = (unsigned long)dmi->driver_data;
1038 dev_printk(KERN_INFO, host->dev,
1039 "applying extra ACPI _GTF filter 0x%x for %s\n",
1040 filter, dmi->ident);
1041
1042 for (i = 0; i < host->n_ports; i++) {
1043 struct ata_port *ap = host->ports[i];
1044 struct ata_link *link;
1045 struct ata_device *dev;
1046
1047 ata_for_each_link(link, ap, EDGE)
1048 ata_for_each_dev(dev, link, ALL)
1049 dev->gtf_filter |= filter;
1050 }
1051}
8e513217
MT		 1052#else
1053static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1054{}
1055#endif
f80ae7e4 1056
24dc5f33 1057static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1058{
1059 static int printed_version;
e297d99e
TH		 1060 unsigned int board_id = ent->driver_data;
1061 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1062 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1063 struct device *dev = &pdev->dev;
1da177e4 1064 struct ahci_host_priv *hpriv;
4447d351 1065 struct ata_host *host;
837f5f8f 1066 int n_ports, i, rc;
1da177e4
LT		 1067
1068 VPRINTK("ENTER\n");
1069
b429dd59 1070 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1071
1da177e4 1072 if (!printed_version++)
a9524a76 1073 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1074
5b66c829
AC		 1075 /* The AHCI driver can only drive the SATA ports, the PATA driver
1076 can drive them all so if both drivers are selected make sure
1077 AHCI stays out of the way */
1078 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1079 return -ENODEV;
1080
c6353b45
TH		 1081 /*
1082 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1083 * ahci, use ata_generic instead.
1084 */
1085 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1086 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1087 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1088 pdev->subsystem_device == 0xcb89)
1089 return -ENODEV;
1090
7a02267e
MN		 1091 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1092 * At the moment, we can only use the AHCI mode. Let the users know
1093 * that for SAS drives they're out of luck.
1094 */
1095 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1096 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1097 "can only drive SATA devices with this driver\n");
1098
4447d351 1099 /* acquire resources */
24dc5f33 1100 rc = pcim_enable_device(pdev);
1da177e4
LT		 1101 if (rc)
1102 return rc;
1103
dea55137
TH		 1104 /* AHCI controllers often implement SFF compatible interface.
1105 * Grab all PCI BARs just in case.
1106 */
1107 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1108 if (rc == -EBUSY)
24dc5f33 1109 pcim_pin_device(pdev);
0d5ff566 1110 if (rc)
24dc5f33 1111 return rc;
1da177e4 1112
c4f7792c
TH		 1113 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1114 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1115 u8 map;
1116
1117 /* ICH6s share the same PCI ID for both piix and ahci
1118 * modes. Enabling ahci mode while MAP indicates
1119 * combined mode is a bad idea. Yield to ata_piix.
1120 */
1121 pci_read_config_byte(pdev, ICH_MAP, &map);
1122 if (map & 0x3) {
1123 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1124 "combined mode, can't enable AHCI mode\n");
1125 return -ENODEV;
1126 }
1127 }
1128
24dc5f33
TH		 1129 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1130 if (!hpriv)
1131 return -ENOMEM;
417a1a6d
TH		 1132 hpriv->flags |= (unsigned long)pi.private_data;
1133
e297d99e
TH		 1134 /* MCP65 revision A1 and A2 can't do MSI */
1135 if (board_id == board_ahci_mcp65 &&
1136 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1137 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1138
e427fe04
SH		 1139 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1140 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1141 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1142
2fcad9d2
TH		 1143 /* only some SB600s can do 64bit DMA */
1144 if (ahci_sb600_enable_64bit(pdev))
1145 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1146
31b239ad
TH		 1147 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1148 pci_intx(pdev, 1);
1da177e4 1149
d8993349
AV		 1150 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1151
4447d351 1152 /* save initial config */
394d6e53 1153 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1154
4447d351 1155 /* prepare host */
453d3131
RH		 1156 if (hpriv->cap & HOST_CAP_NCQ) {
1157 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1158 /*
1159 * Auto-activate optimization is supposed to be
1160 * supported on all AHCI controllers indicating NCQ
1161 * capability, but it seems to be broken on some
1162 * chipsets including NVIDIAs.
1163 */
1164 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1165 pi.flags |= ATA_FLAG_FPDMA_AA;
1166 }
1da177e4 1167
7d50b60b
TH		 1168 if (hpriv->cap & HOST_CAP_PMP)
1169 pi.flags |= ATA_FLAG_PMP;
1170
0cbb0e77 1171 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1172
1fd68434
RW		 1173 if (ahci_broken_system_poweroff(pdev)) {
1174 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1175 dev_info(&pdev->dev,
1176 "quirky BIOS, skipping spindown on poweroff\n");
1177 }
1178
9b10ae86
TH		 1179 if (ahci_broken_suspend(pdev)) {
1180 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1181 dev_printk(KERN_WARNING, &pdev->dev,
1182 "BIOS update required for suspend/resume\n");
1183 }
1184
5594639a
TH		 1185 if (ahci_broken_online(pdev)) {
1186 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1187 dev_info(&pdev->dev,
1188 "online status unreliable, applying workaround\n");
1189 }
1190
837f5f8f
TH		 1191 /* CAP.NP sometimes indicate the index of the last enabled
1192 * port, at other times, that of the last possible port, so
1193 * determining the maximum port number requires looking at
1194 * both CAP.NP and port_map.
1195 */
1196 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1197
1198 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1199 if (!host)
1200 return -ENOMEM;
4447d351
TH		 1201 host->private_data = hpriv;
1202
f3d7f23f 1203 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1204 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1205 else
1206 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1207
18f7ba4c
KCA		 1208 if (pi.flags & ATA_FLAG_EM)
1209 ahci_reset_em(host);
1210
4447d351 1211 for (i = 0; i < host->n_ports; i++) {
dab632e8 1212 struct ata_port *ap = host->ports[i];
4447d351 1213
cbcdd875
TH		 1214 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1215 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1216 0x100 + ap->port_no * 0x80, "port");
1217
18f7ba4c
KCA		 1218 /* set enclosure management message type */
1219 if (ap->flags & ATA_FLAG_EM)
008dbd61 1220 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1221
1222
dab632e8 1223 /* disabled/not-implemented port */
350756f6 1224 if (!(hpriv->port_map & (1 << i)))
dab632e8 1225 ap->ops = &ata_dummy_port_ops;
4447d351 1226 }
d447df14 1227
edc93052
TH		 1228 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1229 ahci_p5wdh_workaround(host);
1230
f80ae7e4
TH		 1231 /* apply gtf filter quirk */
1232 ahci_gtf_filter_workaround(host);
1233
4447d351
TH		 1234 /* initialize adapter */
1235 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1236 if (rc)
24dc5f33 1237 return rc;
1da177e4 1238
3303040d 1239 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1240 if (rc)
1241 return rc;
1da177e4 1242
781d6550 1243 ahci_pci_init_controller(host);
439fcaec 1244 ahci_pci_print_info(host);
1da177e4 1245
4447d351
TH		 1246 pci_set_master(pdev);
1247 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1248 &ahci_sht);
907f4678 1249}
1da177e4
LT		 1250
1251static int __init ahci_init(void)
1252{
b7887196 1253 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1254}
1255
1da177e4
LT		 1256static void __exit ahci_exit(void)
1257{
1258 pci_unregister_driver(&ahci_pci_driver);
1259}
1260
1261
1262MODULE_AUTHOR("Jeff Garzik");
1263MODULE_DESCRIPTION("AHCI SATA low-level driver");
1264MODULE_LICENSE("GPL");
1265MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1266MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1267
1268module_init(ahci_init);
1269module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)