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Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
[linux-2.6-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
417a1a6d
TH		 106#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
107
98ac62de 108static const struct ata_port_info ahci_port_info[] = {
441577ef 109 /* by features */
4da646b7 110 [board_ahci] =
1da177e4 111 {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
441577ef 117 [board_ahci_ign_iferr] =
bf2af2a2 118 {
441577ef 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 120 .flags = AHCI_FLAG_COMMON,
14bdef98 121 .pio_mask = ATA_PIO4,
469248ab 122 .udma_mask = ATA_UDMA6,
441577ef 123 .port_ops = &ahci_ops,
bf2af2a2 124 },
441577ef 125 [board_ahci_nosntf] =
41669553 126 {
441577ef 127 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 128 .flags = AHCI_FLAG_COMMON,
14bdef98 129 .pio_mask = ATA_PIO4,
469248ab 130 .udma_mask = ATA_UDMA6,
41669553
TH		 131 .port_ops = &ahci_ops,
132 },
5f173107
TH		 133 [board_ahci_yes_fbs] =
134 {
135 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
140 },
441577ef
TH		 141 /* by chipsets */
142 [board_ahci_mcp65] =
55a61604 143 {
83f2b963
TH		 144 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
145 AHCI_HFLAG_YES_NCQ),
ae01b249 146 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_mcp77] =
152 {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_mcp89] =
160 {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 162 .flags = AHCI_FLAG_COMMON,
14bdef98 163 .pio_mask = ATA_PIO4,
469248ab 164 .udma_mask = ATA_UDMA6,
441577ef 165 .port_ops = &ahci_ops,
55a61604 166 },
4da646b7 167 [board_ahci_mv] =
cd70c266 168 {
417a1a6d 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 172 .pio_mask = ATA_PIO4,
cd70c266
JG		 173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
441577ef 176 [board_ahci_sb600] =
e39fc8c9 177 {
441577ef
TH		 178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 181 .flags = AHCI_FLAG_COMMON,
14bdef98 182 .pio_mask = ATA_PIO4,
e39fc8c9 183 .udma_mask = ATA_UDMA6,
345347c5 184 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 185 },
441577ef 186 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 187 {
441577ef 188 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
345347c5 192 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 193 },
441577ef 194 [board_ahci_vt8251] =
1b677afd 195 {
441577ef 196 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
441577ef 200 .port_ops = &ahci_vt8251_ops,
1b677afd 201 },
1da177e4
LT		 202};
203
3b7d697d 204static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 205 /* Intel */
54bb3a94
JG		 206 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
207 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
208 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
209 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
210 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 211 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 212 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 216 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 217 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 218 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 233 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 235 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 236 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 237 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 238 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 240 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 241 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 242 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 243 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 244 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 245 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 246 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 252 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
253 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 255 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 256 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 257 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 263 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
fe7fa31a 264
e34bb370
TH		 265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 268
269 /* ATI */
c65ec1c2 270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 277
e2dd90b1 278 /* AMD */
5deab536 279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283
fe7fa31a 284 /* VIA */
54bb3a94 285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 287
288 /* NVIDIA */
e297d99e
TH		 289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 373
95916edd 374 /* SiS */
20e2de4a
TH		 375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 378
318893e1
AR		 379 /* ST Microelectronics */
380 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
381
cd70c266
JG		 382 /* Marvell */
383 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 384 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 385 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 386 .class = PCI_CLASS_STORAGE_SATA_AHCI,
387 .class_mask = 0xffffff,
5f173107 388 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 389 { PCI_DEVICE(0x1b4b, 0x9125),
390 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 391 { PCI_DEVICE(0x1b4b, 0x91a3),
392 .driver_data = board_ahci_yes_fbs },
cd70c266 393
c77a036b
MN		 394 /* Promise */
395 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
396
c9703765
KYL		 397 /* Asmedia */
398 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
399
415ae2b5
JG		 400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 403
1da177e4
LT		 404 { } /* terminate list */
405};
406
407
408static struct pci_driver ahci_pci_driver = {
409 .name = DRV_NAME,
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
24dc5f33 412 .remove = ata_pci_remove_one,
438ac6d5 413#ifdef CONFIG_PM
c1332875 414 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 415 .resume = ahci_pci_device_resume,
416#endif
417};
1da177e4 418
365cfa1e
AV		 419#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420static int marvell_enable;
421#else
422static int marvell_enable = 1;
423#endif
424module_param(marvell_enable, int, 0644);
425MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 426
1da177e4 427
365cfa1e
AV		 428static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
430{
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
67846b30 433
365cfa1e
AV		 434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
436 force_port_map = 1;
1da177e4
LT		 437 }
438
365cfa1e
AV		 439 /*
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
d28f87aa 443 */
365cfa1e
AV		 444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
446 mask_port_map = 0x3;
447 else
448 mask_port_map = 0xf;
449 dev_info(&pdev->dev,
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
451 }
1da177e4 452
365cfa1e
AV		 453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
454 mask_port_map);
1da177e4
LT		 455}
456
365cfa1e 457static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 458{
365cfa1e 459 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 460
365cfa1e 461 ahci_reset_controller(host);
1da177e4 462
365cfa1e
AV		 463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
464 struct ahci_host_priv *hpriv = host->private_data;
465 u16 tmp16;
d6ef3153 466
365cfa1e
AV		 467 /* configure PCS */
468 pci_read_config_word(pdev, 0x92, &tmp16);
469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
472 }
d6ef3153
SH		 473 }
474
1da177e4
LT		 475 return 0;
476}
477
365cfa1e 478static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 479{
365cfa1e
AV		 480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
78cd52d0 483 u32 tmp;
365cfa1e 484 int mv;
78cd52d0 485
365cfa1e
AV		 486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
487 if (pdev->device == 0x6121)
488 mv = 2;
489 else
490 mv = 4;
491 port_mmio = __ahci_port_base(host, mv);
78cd52d0 492
365cfa1e 493 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 494
365cfa1e
AV		 495 /* clear port IRQ */
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
498 if (tmp)
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 500 }
501
365cfa1e 502 ahci_init_controller(host);
edc93052
TH		 503}
504
365cfa1e
AV		 505static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
506 unsigned long deadline)
d6ef3153 507{
365cfa1e
AV		 508 struct ata_port *ap = link->ap;
509 bool online;
d6ef3153
SH		 510 int rc;
511
365cfa1e 512 DPRINTK("ENTER\n");
d6ef3153 513
365cfa1e 514 ahci_stop_engine(ap);
d6ef3153 515
365cfa1e
AV		 516 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
517 deadline, &online, NULL);
d6ef3153
SH		 518
519 ahci_start_engine(ap);
d6ef3153 520
365cfa1e 521 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 522
365cfa1e
AV		 523 /* vt8251 doesn't clear BSY on signature FIS reception,
524 * request follow-up softreset.
525 */
526 return online ? -EAGAIN : rc;
7d50b60b
TH		 527}
528
365cfa1e
AV		 529static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
530 unsigned long deadline)
7d50b60b 531{
365cfa1e 532 struct ata_port *ap = link->ap;
1c954a4d 533 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
535 struct ata_taskfile tf;
536 bool online;
537 int rc;
7d50b60b 538
365cfa1e 539 ahci_stop_engine(ap);
028a2596 540
365cfa1e
AV		 541 /* clear D2H reception area to properly wait for D2H FIS */
542 ata_tf_init(link->device, &tf);
543 tf.command = 0x80;
544 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 545
365cfa1e
AV		 546 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
547 deadline, &online, NULL);
028a2596 548
365cfa1e 549 ahci_start_engine(ap);
c1332875 550
365cfa1e
AV		 551 /* The pseudo configuration device on SIMG4726 attached to
552 * ASUS P5W-DH Deluxe doesn't send signature FIS after
553 * hardreset if no device is attached to the first downstream
554 * port && the pseudo device locks up on SRST w/ PMP==0. To
555 * work around this, wait for !BSY only briefly. If BSY isn't
556 * cleared, perform CLO and proceed to IDENTIFY (achieved by
557 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
558 *
559 * Wait for two seconds. Devices attached to downstream port
560 * which can't process the following IDENTIFY after this will
561 * have to be reset again. For most cases, this should
562 * suffice while making probing snappish enough.
563 */
564 if (online) {
565 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
566 ahci_check_ready);
567 if (rc)
568 ahci_kick_engine(ap);
c1332875 569 }
c1332875
TH		 570 return rc;
571}
572
365cfa1e 573#ifdef CONFIG_PM
c1332875
TH		 574static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
575{
cca3974e 576 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 577 struct ahci_host_priv *hpriv = host->private_data;
d8993349 578 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 579 u32 ctl;
580
9b10ae86
TH		 581 if (mesg.event & PM_EVENT_SUSPEND &&
582 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 583 dev_err(&pdev->dev,
584 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 585 return -EIO;
586 }
587
3a2d5b70 588 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 589 /* AHCI spec rev1.1 section 8.3.3:
590 * Software must disable interrupts prior to requesting a
591 * transition of the HBA to D3 state.
592 */
593 ctl = readl(mmio + HOST_CTL);
594 ctl &= ~HOST_IRQ_EN;
595 writel(ctl, mmio + HOST_CTL);
596 readl(mmio + HOST_CTL); /* flush */
597 }
598
599 return ata_pci_device_suspend(pdev, mesg);
600}
601
602static int ahci_pci_device_resume(struct pci_dev *pdev)
603{
cca3974e 604 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 605 int rc;
606
553c4aa6
TH		 607 rc = ata_pci_device_do_resume(pdev);
608 if (rc)
609 return rc;
c1332875
TH		 610
611 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 612 rc = ahci_pci_reset_controller(host);
c1332875
TH		 613 if (rc)
614 return rc;
615
781d6550 616 ahci_pci_init_controller(host);
c1332875
TH		 617 }
618
cca3974e 619 ata_host_resume(host);
c1332875
TH		 620
621 return 0;
622}
438ac6d5 623#endif
c1332875 624
4447d351 625static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 626{
1da177e4 627 int rc;
1da177e4 628
318893e1
AR		 629 /*
630 * If the device fixup already set the dma_mask to some non-standard
631 * value, don't extend it here. This happens on STA2X11, for example.
632 */
633 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
634 return 0;
635
1da177e4 636 if (using_dac &&
6a35528a
YH		 637 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
638 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 639 if (rc) {
284901a9 640 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 641 if (rc) {
a44fec1f
JP		 642 dev_err(&pdev->dev,
643 "64-bit DMA enable failed\n");
1da177e4
LT		 644 return rc;
645 }
646 }
1da177e4 647 } else {
284901a9 648 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 649 if (rc) {
a44fec1f 650 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 651 return rc;
652 }
284901a9 653 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 654 if (rc) {
a44fec1f
JP		 655 dev_err(&pdev->dev,
656 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 657 return rc;
658 }
659 }
1da177e4
LT		 660 return 0;
661}
662
439fcaec
AV		 663static void ahci_pci_print_info(struct ata_host *host)
664{
665 struct pci_dev *pdev = to_pci_dev(host->dev);
666 u16 cc;
667 const char *scc_s;
668
669 pci_read_config_word(pdev, 0x0a, &cc);
670 if (cc == PCI_CLASS_STORAGE_IDE)
671 scc_s = "IDE";
672 else if (cc == PCI_CLASS_STORAGE_SATA)
673 scc_s = "SATA";
674 else if (cc == PCI_CLASS_STORAGE_RAID)
675 scc_s = "RAID";
676 else
677 scc_s = "unknown";
678
679 ahci_print_info(host, scc_s);
680}
681
edc93052
TH		 682/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
683 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
684 * support PMP and the 4726 either directly exports the device
685 * attached to the first downstream port or acts as a hardware storage
686 * controller and emulate a single ATA device (can be RAID 0/1 or some
687 * other configuration).
688 *
689 * When there's no device attached to the first downstream port of the
690 * 4726, "Config Disk" appears, which is a pseudo ATA device to
691 * configure the 4726. However, ATA emulation of the device is very
692 * lame. It doesn't send signature D2H Reg FIS after the initial
693 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
694 *
695 * The following function works around the problem by always using
696 * hardreset on the port and not depending on receiving signature FIS
697 * afterward. If signature FIS isn't received soon, ATA class is
698 * assumed without follow-up softreset.
699 */
700static void ahci_p5wdh_workaround(struct ata_host *host)
701{
702 static struct dmi_system_id sysids[] = {
703 {
704 .ident = "P5W DH Deluxe",
705 .matches = {
706 DMI_MATCH(DMI_SYS_VENDOR,
707 "ASUSTEK COMPUTER INC"),
708 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
709 },
710 },
711 { }
712 };
713 struct pci_dev *pdev = to_pci_dev(host->dev);
714
715 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
716 dmi_check_system(sysids)) {
717 struct ata_port *ap = host->ports[1];
718
a44fec1f
JP		 719 dev_info(&pdev->dev,
720 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 721
722 ap->ops = &ahci_p5wdh_ops;
723 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
724 }
725}
726
2fcad9d2
TH		 727/* only some SB600 ahci controllers can do 64bit DMA */
728static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 729{
730 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 731 /*
732 * The oldest version known to be broken is 0901 and
733 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 734 * Enable 64bit DMA on 1501 and anything newer.
735 *
03d783bf
TH		 736 * Please read bko#9412 for more info.
737 */
58a09b38
SH		 738 {
739 .ident = "ASUS M2A-VM",
740 .matches = {
741 DMI_MATCH(DMI_BOARD_VENDOR,
742 "ASUSTeK Computer INC."),
743 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
744 },
03d783bf 745 .driver_data = "20071026", /* yyyymmdd */
58a09b38 746 },
e65cc194
MN		 747 /*
748 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
749 * support 64bit DMA.
750 *
751 * BIOS versions earlier than 1.5 had the Manufacturer DMI
752 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
753 * This spelling mistake was fixed in BIOS version 1.5, so
754 * 1.5 and later have the Manufacturer as
755 * "MICRO-STAR INTERNATIONAL CO.,LTD".
756 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
757 *
758 * BIOS versions earlier than 1.9 had a Board Product Name
759 * DMI field of "MS-7376". This was changed to be
760 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
761 * match on DMI_BOARD_NAME of "MS-7376".
762 */
763 {
764 .ident = "MSI K9A2 Platinum",
765 .matches = {
766 DMI_MATCH(DMI_BOARD_VENDOR,
767 "MICRO-STAR INTER"),
768 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
769 },
770 },
3c4aa91f
MN		 771 /*
772 * All BIOS versions for the Asus M3A support 64bit DMA.
773 * (all release versions from 0301 to 1206 were tested)
774 */
775 {
776 .ident = "ASUS M3A",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR,
779 "ASUSTeK Computer INC."),
780 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
781 },
782 },
58a09b38
SH		 783 { }
784 };
03d783bf 785 const struct dmi_system_id *match;
2fcad9d2
TH		 786 int year, month, date;
787 char buf[9];
58a09b38 788
03d783bf 789 match = dmi_first_match(sysids);
58a09b38 790 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 791 !match)
58a09b38
SH		 792 return false;
793
e65cc194
MN		 794 if (!match->driver_data)
795 goto enable_64bit;
796
2fcad9d2
TH		 797 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
798 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 799
e65cc194
MN		 800 if (strcmp(buf, match->driver_data) >= 0)
801 goto enable_64bit;
802 else {
a44fec1f
JP		 803 dev_warn(&pdev->dev,
804 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
805 match->ident);
2fcad9d2
TH		 806 return false;
807 }
e65cc194
MN		 808
809enable_64bit:
a44fec1f 810 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 811 return true;
58a09b38
SH		 812}
813
1fd68434
RW		 814static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
815{
816 static const struct dmi_system_id broken_systems[] = {
817 {
818 .ident = "HP Compaq nx6310",
819 .matches = {
820 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
821 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
822 },
823 /* PCI slot number of the controller */
824 .driver_data = (void *)0x1FUL,
825 },
d2f9c061
MR		 826 {
827 .ident = "HP Compaq 6720s",
828 .matches = {
829 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
830 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
831 },
832 /* PCI slot number of the controller */
833 .driver_data = (void *)0x1FUL,
834 },
1fd68434
RW		 835
836 { } /* terminate list */
837 };
838 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
839
840 if (dmi) {
841 unsigned long slot = (unsigned long)dmi->driver_data;
842 /* apply the quirk only to on-board controllers */
843 return slot == PCI_SLOT(pdev->devfn);
844 }
845
846 return false;
847}
848
9b10ae86
TH		 849static bool ahci_broken_suspend(struct pci_dev *pdev)
850{
851 static const struct dmi_system_id sysids[] = {
852 /*
853 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
854 * to the harddisk doesn't become online after
855 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 856 *
857 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
858 *
859 * Use dates instead of versions to match as HP is
860 * apparently recycling both product and version
861 * strings.
862 *
863 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 864 */
865 {
866 .ident = "dv4",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
869 DMI_MATCH(DMI_PRODUCT_NAME,
870 "HP Pavilion dv4 Notebook PC"),
871 },
9deb3431 872 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 873 },
874 {
875 .ident = "dv5",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME,
879 "HP Pavilion dv5 Notebook PC"),
880 },
9deb3431 881 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 882 },
883 {
884 .ident = "dv6",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME,
888 "HP Pavilion dv6 Notebook PC"),
889 },
9deb3431 890 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 891 },
892 {
893 .ident = "HDX18",
894 .matches = {
895 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
896 DMI_MATCH(DMI_PRODUCT_NAME,
897 "HP HDX18 Notebook PC"),
898 },
9deb3431 899 .driver_data = "20090430", /* F.23 */
9b10ae86 900 },
cedc9bf9
TH		 901 /*
902 * Acer eMachines G725 has the same problem. BIOS
903 * V1.03 is known to be broken. V3.04 is known to
25985edc 904 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 905 * that we don't have much idea about. For now,
906 * blacklist anything older than V3.04.
9deb3431
TH		 907 *
908 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 909 */
910 {
911 .ident = "G725",
912 .matches = {
913 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
914 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
915 },
9deb3431 916 .driver_data = "20091216", /* V3.04 */
cedc9bf9 917 },
9b10ae86
TH		 918 { } /* terminate list */
919 };
920 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 921 int year, month, date;
922 char buf[9];
9b10ae86
TH		 923
924 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
925 return false;
926
9deb3431
TH		 927 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
928 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 929
9deb3431 930 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 931}
932
5594639a
TH		 933static bool ahci_broken_online(struct pci_dev *pdev)
934{
935#define ENCODE_BUSDEVFN(bus, slot, func) \
936 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
937 static const struct dmi_system_id sysids[] = {
938 /*
939 * There are several gigabyte boards which use
940 * SIMG5723s configured as hardware RAID. Certain
941 * 5723 firmware revisions shipped there keep the link
942 * online but fail to answer properly to SRST or
943 * IDENTIFY when no device is attached downstream
944 * causing libata to retry quite a few times leading
945 * to excessive detection delay.
946 *
947 * As these firmwares respond to the second reset try
948 * with invalid device signature, considering unknown
949 * sig as offline works around the problem acceptably.
950 */
951 {
952 .ident = "EP45-DQ6",
953 .matches = {
954 DMI_MATCH(DMI_BOARD_VENDOR,
955 "Gigabyte Technology Co., Ltd."),
956 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
957 },
958 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
959 },
960 {
961 .ident = "EP45-DS5",
962 .matches = {
963 DMI_MATCH(DMI_BOARD_VENDOR,
964 "Gigabyte Technology Co., Ltd."),
965 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
966 },
967 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
968 },
969 { } /* terminate list */
970 };
971#undef ENCODE_BUSDEVFN
972 const struct dmi_system_id *dmi = dmi_first_match(sysids);
973 unsigned int val;
974
975 if (!dmi)
976 return false;
977
978 val = (unsigned long)dmi->driver_data;
979
980 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
981}
982
8e513217 983#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 984static void ahci_gtf_filter_workaround(struct ata_host *host)
985{
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * Aspire 3810T issues a bunch of SATA enable commands
989 * via _GTF including an invalid one and one which is
990 * rejected by the device. Among the successful ones
991 * is FPDMA non-zero offset enable which when enabled
992 * only on the drive side leads to NCQ command
993 * failures. Filter it out.
994 */
995 {
996 .ident = "Aspire 3810T",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1000 },
1001 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1002 },
1003 { }
1004 };
1005 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1006 unsigned int filter;
1007 int i;
1008
1009 if (!dmi)
1010 return;
1011
1012 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1013 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1014 filter, dmi->ident);
f80ae7e4
TH		 1015
1016 for (i = 0; i < host->n_ports; i++) {
1017 struct ata_port *ap = host->ports[i];
1018 struct ata_link *link;
1019 struct ata_device *dev;
1020
1021 ata_for_each_link(link, ap, EDGE)
1022 ata_for_each_dev(dev, link, ALL)
1023 dev->gtf_filter |= filter;
1024 }
1025}
8e513217
MT		 1026#else
1027static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1028{}
1029#endif
f80ae7e4 1030
24dc5f33 1031static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1032{
e297d99e
TH		 1033 unsigned int board_id = ent->driver_data;
1034 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1035 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1036 struct device *dev = &pdev->dev;
1da177e4 1037 struct ahci_host_priv *hpriv;
4447d351 1038 struct ata_host *host;
837f5f8f 1039 int n_ports, i, rc;
318893e1 1040 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1041
1042 VPRINTK("ENTER\n");
1043
b429dd59 1044 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1045
06296a1e 1046 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1047
5b66c829
AC		 1048 /* The AHCI driver can only drive the SATA ports, the PATA driver
1049 can drive them all so if both drivers are selected make sure
1050 AHCI stays out of the way */
1051 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1052 return -ENODEV;
1053
c6353b45
TH		 1054 /*
1055 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1056 * ahci, use ata_generic instead.
1057 */
1058 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1059 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1060 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1061 pdev->subsystem_device == 0xcb89)
1062 return -ENODEV;
1063
7a02267e
MN		 1064 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1065 * At the moment, we can only use the AHCI mode. Let the users know
1066 * that for SAS drives they're out of luck.
1067 */
1068 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1069 dev_info(&pdev->dev,
1070 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1071
318893e1
AR		 1072 /* The Connext uses non-standard BAR */
1073 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1074 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1075
4447d351 1076 /* acquire resources */
24dc5f33 1077 rc = pcim_enable_device(pdev);
1da177e4
LT		 1078 if (rc)
1079 return rc;
1080
dea55137
TH		 1081 /* AHCI controllers often implement SFF compatible interface.
1082 * Grab all PCI BARs just in case.
1083 */
318893e1 1084 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1085 if (rc == -EBUSY)
24dc5f33 1086 pcim_pin_device(pdev);
0d5ff566 1087 if (rc)
24dc5f33 1088 return rc;
1da177e4 1089
c4f7792c
TH		 1090 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1091 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1092 u8 map;
1093
1094 /* ICH6s share the same PCI ID for both piix and ahci
1095 * modes. Enabling ahci mode while MAP indicates
1096 * combined mode is a bad idea. Yield to ata_piix.
1097 */
1098 pci_read_config_byte(pdev, ICH_MAP, &map);
1099 if (map & 0x3) {
a44fec1f
JP		 1100 dev_info(&pdev->dev,
1101 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1102 return -ENODEV;
1103 }
1104 }
1105
24dc5f33
TH		 1106 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1107 if (!hpriv)
1108 return -ENOMEM;
417a1a6d
TH		 1109 hpriv->flags |= (unsigned long)pi.private_data;
1110
e297d99e
TH		 1111 /* MCP65 revision A1 and A2 can't do MSI */
1112 if (board_id == board_ahci_mcp65 &&
1113 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1114 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1115
e427fe04
SH		 1116 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1117 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1118 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1119
2fcad9d2
TH		 1120 /* only some SB600s can do 64bit DMA */
1121 if (ahci_sb600_enable_64bit(pdev))
1122 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1123
31b239ad
TH		 1124 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1125 pci_intx(pdev, 1);
1da177e4 1126
318893e1 1127 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1128
4447d351 1129 /* save initial config */
394d6e53 1130 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1131
4447d351 1132 /* prepare host */
453d3131
RH		 1133 if (hpriv->cap & HOST_CAP_NCQ) {
1134 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1135 /*
1136 * Auto-activate optimization is supposed to be
1137 * supported on all AHCI controllers indicating NCQ
1138 * capability, but it seems to be broken on some
1139 * chipsets including NVIDIAs.
1140 */
1141 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1142 pi.flags |= ATA_FLAG_FPDMA_AA;
1143 }
1da177e4 1144
7d50b60b
TH		 1145 if (hpriv->cap & HOST_CAP_PMP)
1146 pi.flags |= ATA_FLAG_PMP;
1147
0cbb0e77 1148 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1149
1fd68434
RW		 1150 if (ahci_broken_system_poweroff(pdev)) {
1151 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1152 dev_info(&pdev->dev,
1153 "quirky BIOS, skipping spindown on poweroff\n");
1154 }
1155
9b10ae86
TH		 1156 if (ahci_broken_suspend(pdev)) {
1157 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1158 dev_warn(&pdev->dev,
1159 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1160 }
1161
5594639a
TH		 1162 if (ahci_broken_online(pdev)) {
1163 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1164 dev_info(&pdev->dev,
1165 "online status unreliable, applying workaround\n");
1166 }
1167
837f5f8f
TH		 1168 /* CAP.NP sometimes indicate the index of the last enabled
1169 * port, at other times, that of the last possible port, so
1170 * determining the maximum port number requires looking at
1171 * both CAP.NP and port_map.
1172 */
1173 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1174
1175 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1176 if (!host)
1177 return -ENOMEM;
4447d351
TH		 1178 host->private_data = hpriv;
1179
f3d7f23f 1180 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1181 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1182 else
1183 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1184
18f7ba4c
KCA		 1185 if (pi.flags & ATA_FLAG_EM)
1186 ahci_reset_em(host);
1187
4447d351 1188 for (i = 0; i < host->n_ports; i++) {
dab632e8 1189 struct ata_port *ap = host->ports[i];
4447d351 1190
318893e1
AR		 1191 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1192 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1193 0x100 + ap->port_no * 0x80, "port");
1194
18f7ba4c
KCA		 1195 /* set enclosure management message type */
1196 if (ap->flags & ATA_FLAG_EM)
008dbd61 1197 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1198
1199
dab632e8 1200 /* disabled/not-implemented port */
350756f6 1201 if (!(hpriv->port_map & (1 << i)))
dab632e8 1202 ap->ops = &ata_dummy_port_ops;
4447d351 1203 }
d447df14 1204
edc93052
TH		 1205 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1206 ahci_p5wdh_workaround(host);
1207
f80ae7e4
TH		 1208 /* apply gtf filter quirk */
1209 ahci_gtf_filter_workaround(host);
1210
4447d351
TH		 1211 /* initialize adapter */
1212 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1213 if (rc)
24dc5f33 1214 return rc;
1da177e4 1215
3303040d 1216 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1217 if (rc)
1218 return rc;
1da177e4 1219
781d6550 1220 ahci_pci_init_controller(host);
439fcaec 1221 ahci_pci_print_info(host);
1da177e4 1222
4447d351
TH		 1223 pci_set_master(pdev);
1224 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1225 &ahci_sht);
907f4678 1226}
1da177e4
LT		 1227
1228static int __init ahci_init(void)
1229{
b7887196 1230 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1231}
1232
1da177e4
LT		 1233static void __exit ahci_exit(void)
1234{
1235 pci_unregister_driver(&ahci_pci_driver);
1236}
1237
1238
1239MODULE_AUTHOR("Jeff Garzik");
1240MODULE_DESCRIPTION("AHCI SATA low-level driver");
1241MODULE_LICENSE("GPL");
1242MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1243MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1244
1245module_init(ahci_init);
1246module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)