Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
af36d7f0 JG |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
19285f3c | 27 | * as Documentation/driver-api/libata.rst |
af36d7f0 JG |
28 | * |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
1da177e4 LT |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
87507cfd | 41 | #include <linux/dma-mapping.h> |
a9524a76 | 42 | #include <linux/device.h> |
edc93052 | 43 | #include <linux/dmi.h> |
5a0e3ad6 | 44 | #include <linux/gfp.h> |
ee2aad42 | 45 | #include <linux/msi.h> |
1da177e4 | 46 | #include <scsi/scsi_host.h> |
193515d5 | 47 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 48 | #include <linux/libata.h> |
aecec8b6 CH |
49 | #include <linux/ahci-remap.h> |
50 | #include <linux/io-64-nonatomic-lo-hi.h> | |
365cfa1e | 51 | #include "ahci.h" |
1da177e4 LT |
52 | |
53 | #define DRV_NAME "ahci" | |
7d50b60b | 54 | #define DRV_VERSION "3.0" |
1da177e4 | 55 | |
1da177e4 | 56 | enum { |
318893e1 | 57 | AHCI_PCI_BAR_STA2X11 = 0, |
b7ae128d | 58 | AHCI_PCI_BAR_CAVIUM = 0, |
7f9c9f8e | 59 | AHCI_PCI_BAR_ENMOTUS = 2, |
b1314e3f | 60 | AHCI_PCI_BAR_CAVIUM_GEN5 = 4, |
318893e1 | 61 | AHCI_PCI_BAR_STANDARD = 5, |
441577ef TH |
62 | }; |
63 | ||
64 | enum board_ids { | |
65 | /* board IDs by feature in alphabetical order */ | |
66 | board_ahci, | |
67 | board_ahci_ign_iferr, | |
ebb82e3c | 68 | board_ahci_mobile, |
66a7cbc3 | 69 | board_ahci_nomsi, |
67809f85 | 70 | board_ahci_noncq, |
441577ef | 71 | board_ahci_nosntf, |
5f173107 | 72 | board_ahci_yes_fbs, |
1da177e4 | 73 | |
441577ef | 74 | /* board IDs for specific chipsets in alphabetical order */ |
dbfe8ef5 | 75 | board_ahci_avn, |
441577ef | 76 | board_ahci_mcp65, |
83f2b963 TH |
77 | board_ahci_mcp77, |
78 | board_ahci_mcp89, | |
441577ef TH |
79 | board_ahci_mv, |
80 | board_ahci_sb600, | |
81 | board_ahci_sb700, /* for SB700 and SB800 */ | |
82 | board_ahci_vt8251, | |
83 | ||
84 | /* aliases */ | |
85 | board_ahci_mcp_linux = board_ahci_mcp65, | |
86 | board_ahci_mcp67 = board_ahci_mcp65, | |
87 | board_ahci_mcp73 = board_ahci_mcp65, | |
83f2b963 | 88 | board_ahci_mcp79 = board_ahci_mcp77, |
1da177e4 LT |
89 | }; |
90 | ||
2dcb407e | 91 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
02e53293 | 92 | static void ahci_remove_one(struct pci_dev *dev); |
a1efdaba TH |
93 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
94 | unsigned long deadline); | |
dbfe8ef5 DW |
95 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
96 | unsigned long deadline); | |
cb85696d JL |
97 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev); |
98 | static bool is_mcp89_apple(struct pci_dev *pdev); | |
a1efdaba TH |
99 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
100 | unsigned long deadline); | |
02e53293 MW |
101 | #ifdef CONFIG_PM |
102 | static int ahci_pci_device_runtime_suspend(struct device *dev); | |
103 | static int ahci_pci_device_runtime_resume(struct device *dev); | |
f1d848f9 MW |
104 | #ifdef CONFIG_PM_SLEEP |
105 | static int ahci_pci_device_suspend(struct device *dev); | |
106 | static int ahci_pci_device_resume(struct device *dev); | |
438ac6d5 | 107 | #endif |
02e53293 | 108 | #endif /* CONFIG_PM */ |
ad616ffb | 109 | |
fad16e7a TH |
110 | static struct scsi_host_template ahci_sht = { |
111 | AHCI_SHT("ahci"), | |
112 | }; | |
113 | ||
029cfd6b TH |
114 | static struct ata_port_operations ahci_vt8251_ops = { |
115 | .inherits = &ahci_ops, | |
a1efdaba | 116 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 117 | }; |
edc93052 | 118 | |
029cfd6b TH |
119 | static struct ata_port_operations ahci_p5wdh_ops = { |
120 | .inherits = &ahci_ops, | |
a1efdaba | 121 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
122 | }; |
123 | ||
dbfe8ef5 DW |
124 | static struct ata_port_operations ahci_avn_ops = { |
125 | .inherits = &ahci_ops, | |
126 | .hardreset = ahci_avn_hardreset, | |
127 | }; | |
128 | ||
98ac62de | 129 | static const struct ata_port_info ahci_port_info[] = { |
441577ef | 130 | /* by features */ |
facb8fa6 | 131 | [board_ahci] = { |
1188c0d8 | 132 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 133 | .pio_mask = ATA_PIO4, |
469248ab | 134 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
135 | .port_ops = &ahci_ops, |
136 | }, | |
facb8fa6 | 137 | [board_ahci_ign_iferr] = { |
441577ef | 138 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
417a1a6d | 139 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 140 | .pio_mask = ATA_PIO4, |
469248ab | 141 | .udma_mask = ATA_UDMA6, |
441577ef | 142 | .port_ops = &ahci_ops, |
bf2af2a2 | 143 | }, |
ebb82e3c HG |
144 | [board_ahci_mobile] = { |
145 | AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), | |
146 | .flags = AHCI_FLAG_COMMON, | |
147 | .pio_mask = ATA_PIO4, | |
148 | .udma_mask = ATA_UDMA6, | |
149 | .port_ops = &ahci_ops, | |
150 | }, | |
66a7cbc3 TH |
151 | [board_ahci_nomsi] = { |
152 | AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), | |
153 | .flags = AHCI_FLAG_COMMON, | |
154 | .pio_mask = ATA_PIO4, | |
155 | .udma_mask = ATA_UDMA6, | |
156 | .port_ops = &ahci_ops, | |
157 | }, | |
67809f85 LK |
158 | [board_ahci_noncq] = { |
159 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), | |
160 | .flags = AHCI_FLAG_COMMON, | |
161 | .pio_mask = ATA_PIO4, | |
162 | .udma_mask = ATA_UDMA6, | |
163 | .port_ops = &ahci_ops, | |
164 | }, | |
facb8fa6 | 165 | [board_ahci_nosntf] = { |
441577ef | 166 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), |
417a1a6d | 167 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 168 | .pio_mask = ATA_PIO4, |
469248ab | 169 | .udma_mask = ATA_UDMA6, |
41669553 TH |
170 | .port_ops = &ahci_ops, |
171 | }, | |
facb8fa6 | 172 | [board_ahci_yes_fbs] = { |
5f173107 TH |
173 | AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), |
174 | .flags = AHCI_FLAG_COMMON, | |
175 | .pio_mask = ATA_PIO4, | |
176 | .udma_mask = ATA_UDMA6, | |
177 | .port_ops = &ahci_ops, | |
178 | }, | |
441577ef | 179 | /* by chipsets */ |
dbfe8ef5 DW |
180 | [board_ahci_avn] = { |
181 | .flags = AHCI_FLAG_COMMON, | |
182 | .pio_mask = ATA_PIO4, | |
183 | .udma_mask = ATA_UDMA6, | |
184 | .port_ops = &ahci_avn_ops, | |
185 | }, | |
facb8fa6 | 186 | [board_ahci_mcp65] = { |
83f2b963 TH |
187 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | |
188 | AHCI_HFLAG_YES_NCQ), | |
ae01b249 | 189 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
83f2b963 TH |
190 | .pio_mask = ATA_PIO4, |
191 | .udma_mask = ATA_UDMA6, | |
192 | .port_ops = &ahci_ops, | |
193 | }, | |
facb8fa6 | 194 | [board_ahci_mcp77] = { |
83f2b963 TH |
195 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), |
196 | .flags = AHCI_FLAG_COMMON, | |
197 | .pio_mask = ATA_PIO4, | |
198 | .udma_mask = ATA_UDMA6, | |
199 | .port_ops = &ahci_ops, | |
200 | }, | |
facb8fa6 | 201 | [board_ahci_mcp89] = { |
83f2b963 | 202 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), |
417a1a6d | 203 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 204 | .pio_mask = ATA_PIO4, |
469248ab | 205 | .udma_mask = ATA_UDMA6, |
441577ef | 206 | .port_ops = &ahci_ops, |
55a61604 | 207 | }, |
facb8fa6 | 208 | [board_ahci_mv] = { |
417a1a6d | 209 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 210 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
9cbe056f | 211 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
14bdef98 | 212 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
213 | .udma_mask = ATA_UDMA6, |
214 | .port_ops = &ahci_ops, | |
215 | }, | |
facb8fa6 | 216 | [board_ahci_sb600] = { |
441577ef TH |
217 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
218 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | | |
219 | AHCI_HFLAG_32BIT_ONLY), | |
e39fc8c9 | 220 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 221 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 222 | .udma_mask = ATA_UDMA6, |
345347c5 | 223 | .port_ops = &ahci_pmp_retry_srst_ops, |
e39fc8c9 | 224 | }, |
facb8fa6 | 225 | [board_ahci_sb700] = { /* for SB700 and SB800 */ |
441577ef | 226 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
aa431dd3 TH |
227 | .flags = AHCI_FLAG_COMMON, |
228 | .pio_mask = ATA_PIO4, | |
229 | .udma_mask = ATA_UDMA6, | |
345347c5 | 230 | .port_ops = &ahci_pmp_retry_srst_ops, |
aa431dd3 | 231 | }, |
facb8fa6 | 232 | [board_ahci_vt8251] = { |
441577ef | 233 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
1b677afd SL |
234 | .flags = AHCI_FLAG_COMMON, |
235 | .pio_mask = ATA_PIO4, | |
236 | .udma_mask = ATA_UDMA6, | |
441577ef | 237 | .port_ops = &ahci_vt8251_ops, |
1b677afd | 238 | }, |
1da177e4 LT |
239 | }; |
240 | ||
3b7d697d | 241 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 242 | /* Intel */ |
54bb3a94 JG |
243 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
244 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
245 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
246 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
247 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 248 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
249 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
250 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
251 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
252 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff | 253 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
1b677afd | 254 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ |
7a234aff TH |
255 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
256 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
257 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
258 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
259 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
260 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
261 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
262 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
ebb82e3c HG |
263 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ |
264 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ | |
265 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ | |
266 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ | |
267 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ | |
7a234aff | 268 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
ebb82e3c | 269 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ |
d4155e6f JG |
270 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
271 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 | 272 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
b2dde6af | 273 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
16ad1ad9 | 274 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
c1f57d9b DM |
275 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
276 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ | |
adcb5308 | 277 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 278 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
ebb82e3c | 279 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ |
adcb5308 | 280 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
ebb82e3c | 281 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ |
c1f57d9b | 282 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
342decff AY |
283 | { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ |
284 | { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ | |
285 | { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ | |
286 | { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ | |
287 | { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ | |
288 | { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ | |
289 | { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ | |
290 | { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ | |
291 | { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ | |
292 | { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ | |
293 | { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ | |
294 | { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ | |
295 | { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ | |
296 | { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ | |
297 | { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ | |
298 | { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ | |
299 | { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ | |
300 | { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ | |
301 | { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ | |
302 | { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ | |
5623cab8 | 303 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
ebb82e3c | 304 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ |
5623cab8 | 305 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ |
ebb82e3c | 306 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ |
5623cab8 SH |
307 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ |
308 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ | |
992b3fb9 SH |
309 | { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ |
310 | { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ | |
311 | { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ | |
64a3903d | 312 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ |
a4a461a6 | 313 | { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ |
181e3cea | 314 | { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ |
ebb82e3c | 315 | { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ |
181e3cea SH |
316 | { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ |
317 | { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ | |
318 | { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ | |
ebb82e3c | 319 | { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ |
2cab7a4c | 320 | { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ |
ea4ace66 | 321 | { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ |
ebb82e3c | 322 | { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ |
ea4ace66 | 323 | { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ |
ebb82e3c | 324 | { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ |
ea4ace66 | 325 | { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ |
ebb82e3c | 326 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ |
ea4ace66 | 327 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ |
ebb82e3c HG |
328 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ |
329 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ | |
330 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ | |
331 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ | |
332 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ | |
333 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ | |
334 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ | |
335 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ | |
336 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ | |
4544e403 | 337 | { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ |
29e674dd SH |
338 | { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ |
339 | { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ | |
340 | { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ | |
341 | { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ | |
342 | { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ | |
343 | { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ | |
344 | { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ | |
345 | { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ | |
dbfe8ef5 DW |
346 | { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ |
347 | { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ | |
348 | { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ | |
349 | { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ | |
350 | { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ | |
351 | { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ | |
352 | { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ | |
353 | { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ | |
efda332c JR |
354 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ |
355 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ | |
151743fd JR |
356 | { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ |
357 | { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ | |
358 | { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ | |
359 | { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ | |
360 | { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ | |
361 | { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ | |
362 | { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ | |
363 | { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ | |
1cfc7df3 | 364 | { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ |
ebb82e3c HG |
365 | { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ |
366 | { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ | |
367 | { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ | |
368 | { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ | |
1b071a09 | 369 | { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ |
ebb82e3c | 370 | { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ |
1b071a09 | 371 | { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ |
ebb82e3c | 372 | { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ |
1b071a09 | 373 | { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ |
ebb82e3c | 374 | { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ |
1b071a09 | 375 | { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ |
ebb82e3c HG |
376 | { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ |
377 | { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ | |
378 | { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ | |
379 | { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ | |
c5967b79 | 380 | { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ |
ebb82e3c | 381 | { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ |
690000b9 | 382 | { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ |
c5967b79 | 383 | { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ |
ebb82e3c | 384 | { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ |
690000b9 | 385 | { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ |
4d92f009 | 386 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c | 387 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 388 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c | 389 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ |
4d92f009 | 390 | { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 391 | { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c AY |
392 | { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ |
393 | { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ | |
4d92f009 | 394 | { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 395 | { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c AY |
396 | { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ |
397 | { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ | |
f919dde0 | 398 | { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ |
ebb82e3c HG |
399 | { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ |
400 | { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ | |
401 | { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ | |
402 | { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ | |
ba445791 | 403 | { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ |
fe7fa31a | 404 | |
e34bb370 TH |
405 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
406 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
407 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
1fefb8fd BH |
408 | /* JMicron 362B and 362C have an AHCI function with IDE class code */ |
409 | { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, | |
410 | { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, | |
91f15fb3 | 411 | /* May need to update quirk_jmicron_async_suspend() for additions */ |
fe7fa31a JG |
412 | |
413 | /* ATI */ | |
c65ec1c2 | 414 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
415 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
416 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
417 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
418 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
419 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
420 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a | 421 | |
e2dd90b1 | 422 | /* AMD */ |
5deab536 | 423 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
fafe5c3d | 424 | { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ |
e2dd90b1 SH |
425 | /* AMD is using RAID class only for ahci controllers */ |
426 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
427 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, | |
428 | ||
fe7fa31a | 429 | /* VIA */ |
54bb3a94 | 430 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 431 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
432 | |
433 | /* NVIDIA */ | |
e297d99e TH |
434 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
435 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
441577ef TH |
442 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ |
443 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ | |
463 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ | |
475 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ | |
476 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ | |
479 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ | |
480 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ | |
487 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ | |
488 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ | |
491 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ | |
492 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ | |
494 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ | |
495 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ | |
496 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ | |
502 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ | |
509 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ | |
510 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ | |
511 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ | |
512 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ | |
515 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ | |
516 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ | |
517 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ | |
fe7fa31a | 518 | |
95916edd | 519 | /* SiS */ |
20e2de4a TH |
520 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
521 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
522 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 523 | |
318893e1 AR |
524 | /* ST Microelectronics */ |
525 | { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ | |
526 | ||
cd70c266 JG |
527 | /* Marvell */ |
528 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 529 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
69fd3157 | 530 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), |
10aca06c AH |
531 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
532 | .class_mask = 0xffffff, | |
5f173107 | 533 | .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ |
69fd3157 | 534 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), |
467b41c6 | 535 | .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ |
e098f5cb SG |
536 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, |
537 | PCI_VENDOR_ID_MARVELL_EXT, 0x9170), | |
538 | .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ | |
69fd3157 | 539 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), |
642d8925 | 540 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
fcce9a35 | 541 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), |
c5edfff9 MK |
542 | .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ |
543 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), | |
fcce9a35 | 544 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
69fd3157 | 545 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), |
17c60c6b | 546 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ |
754a292f AS |
547 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), |
548 | .driver_data = board_ahci_yes_fbs }, | |
a40cf3f3 JT |
549 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ |
550 | .driver_data = board_ahci_yes_fbs }, | |
69fd3157 | 551 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), |
50be5e36 | 552 | .driver_data = board_ahci_yes_fbs }, |
6d5278a6 SB |
553 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), |
554 | .driver_data = board_ahci_yes_fbs }, | |
28b2182d HG |
555 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ |
556 | .driver_data = board_ahci_yes_fbs }, | |
557 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ | |
d2518365 | 558 | .driver_data = board_ahci_yes_fbs }, |
cd70c266 | 559 | |
c77a036b MN |
560 | /* Promise */ |
561 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
b32bfc06 | 562 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
c77a036b | 563 | |
c9703765 | 564 | /* Asmedia */ |
7b4f6eca AC |
565 | { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ |
566 | { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ | |
567 | { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ | |
568 | { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ | |
0ce968f3 SL |
569 | { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ |
570 | { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ | |
c9703765 | 571 | |
67809f85 | 572 | /* |
66a7cbc3 TH |
573 | * Samsung SSDs found on some macbooks. NCQ times out if MSI is |
574 | * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 | |
67809f85 | 575 | */ |
66a7cbc3 | 576 | { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, |
2b21ef0a | 577 | { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, |
67809f85 | 578 | |
7f9c9f8e HD |
579 | /* Enmotus */ |
580 | { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, | |
581 | ||
415ae2b5 JG |
582 | /* Generic, PCI class code for AHCI */ |
583 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 584 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 585 | |
1da177e4 LT |
586 | { } /* terminate list */ |
587 | }; | |
588 | ||
f1d848f9 MW |
589 | static const struct dev_pm_ops ahci_pci_pm_ops = { |
590 | SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) | |
02e53293 MW |
591 | SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, |
592 | ahci_pci_device_runtime_resume, NULL) | |
f1d848f9 | 593 | }; |
1da177e4 LT |
594 | |
595 | static struct pci_driver ahci_pci_driver = { | |
596 | .name = DRV_NAME, | |
597 | .id_table = ahci_pci_tbl, | |
598 | .probe = ahci_init_one, | |
02e53293 | 599 | .remove = ahci_remove_one, |
f1d848f9 MW |
600 | .driver = { |
601 | .pm = &ahci_pci_pm_ops, | |
602 | }, | |
365cfa1e | 603 | }; |
1da177e4 | 604 | |
5219d653 | 605 | #if IS_ENABLED(CONFIG_PATA_MARVELL) |
365cfa1e AV |
606 | static int marvell_enable; |
607 | #else | |
608 | static int marvell_enable = 1; | |
609 | #endif | |
610 | module_param(marvell_enable, int, 0644); | |
611 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
d28f87aa | 612 | |
ebb82e3c HG |
613 | static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY; |
614 | module_param(mobile_lpm_policy, int, 0644); | |
615 | MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); | |
1da177e4 | 616 | |
365cfa1e AV |
617 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
618 | struct ahci_host_priv *hpriv) | |
619 | { | |
365cfa1e AV |
620 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
621 | dev_info(&pdev->dev, "JMB361 has only one port\n"); | |
9a23c1d6 | 622 | hpriv->force_port_map = 1; |
1da177e4 LT |
623 | } |
624 | ||
365cfa1e AV |
625 | /* |
626 | * Temporary Marvell 6145 hack: PATA port presence | |
627 | * is asserted through the standard AHCI port | |
628 | * presence register, as bit 4 (counting from 0) | |
d28f87aa | 629 | */ |
365cfa1e AV |
630 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
631 | if (pdev->device == 0x6121) | |
9a23c1d6 | 632 | hpriv->mask_port_map = 0x3; |
365cfa1e | 633 | else |
9a23c1d6 | 634 | hpriv->mask_port_map = 0xf; |
365cfa1e AV |
635 | dev_info(&pdev->dev, |
636 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
637 | } | |
1da177e4 | 638 | |
725c7b57 | 639 | ahci_save_initial_config(&pdev->dev, hpriv); |
1da177e4 LT |
640 | } |
641 | ||
365cfa1e | 642 | static int ahci_pci_reset_controller(struct ata_host *host) |
1da177e4 | 643 | { |
365cfa1e | 644 | struct pci_dev *pdev = to_pci_dev(host->dev); |
d312fefe | 645 | int rc; |
7d50b60b | 646 | |
d312fefe AB |
647 | rc = ahci_reset_controller(host); |
648 | if (rc) | |
649 | return rc; | |
1da177e4 | 650 | |
365cfa1e AV |
651 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
652 | struct ahci_host_priv *hpriv = host->private_data; | |
653 | u16 tmp16; | |
d6ef3153 | 654 | |
365cfa1e AV |
655 | /* configure PCS */ |
656 | pci_read_config_word(pdev, 0x92, &tmp16); | |
657 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { | |
658 | tmp16 |= hpriv->port_map; | |
659 | pci_write_config_word(pdev, 0x92, tmp16); | |
660 | } | |
d6ef3153 SH |
661 | } |
662 | ||
1da177e4 LT |
663 | return 0; |
664 | } | |
665 | ||
365cfa1e | 666 | static void ahci_pci_init_controller(struct ata_host *host) |
78cd52d0 | 667 | { |
365cfa1e AV |
668 | struct ahci_host_priv *hpriv = host->private_data; |
669 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
670 | void __iomem *port_mmio; | |
78cd52d0 | 671 | u32 tmp; |
365cfa1e | 672 | int mv; |
78cd52d0 | 673 | |
365cfa1e AV |
674 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
675 | if (pdev->device == 0x6121) | |
676 | mv = 2; | |
677 | else | |
678 | mv = 4; | |
679 | port_mmio = __ahci_port_base(host, mv); | |
78cd52d0 | 680 | |
365cfa1e | 681 | writel(0, port_mmio + PORT_IRQ_MASK); |
78cd52d0 | 682 | |
365cfa1e AV |
683 | /* clear port IRQ */ |
684 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
685 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
686 | if (tmp) | |
687 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
78cd52d0 TH |
688 | } |
689 | ||
365cfa1e | 690 | ahci_init_controller(host); |
edc93052 TH |
691 | } |
692 | ||
365cfa1e AV |
693 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
694 | unsigned long deadline) | |
d6ef3153 | 695 | { |
365cfa1e | 696 | struct ata_port *ap = link->ap; |
039ece38 | 697 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e | 698 | bool online; |
d6ef3153 SH |
699 | int rc; |
700 | ||
365cfa1e | 701 | DPRINTK("ENTER\n"); |
d6ef3153 | 702 | |
fa89f53b | 703 | hpriv->stop_engine(ap); |
d6ef3153 | 704 | |
365cfa1e AV |
705 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
706 | deadline, &online, NULL); | |
d6ef3153 | 707 | |
039ece38 | 708 | hpriv->start_engine(ap); |
d6ef3153 | 709 | |
365cfa1e | 710 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
d6ef3153 | 711 | |
365cfa1e AV |
712 | /* vt8251 doesn't clear BSY on signature FIS reception, |
713 | * request follow-up softreset. | |
714 | */ | |
715 | return online ? -EAGAIN : rc; | |
7d50b60b TH |
716 | } |
717 | ||
365cfa1e AV |
718 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
719 | unsigned long deadline) | |
7d50b60b | 720 | { |
365cfa1e | 721 | struct ata_port *ap = link->ap; |
1c954a4d | 722 | struct ahci_port_priv *pp = ap->private_data; |
039ece38 | 723 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
724 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
725 | struct ata_taskfile tf; | |
726 | bool online; | |
727 | int rc; | |
7d50b60b | 728 | |
fa89f53b | 729 | hpriv->stop_engine(ap); |
028a2596 | 730 | |
365cfa1e AV |
731 | /* clear D2H reception area to properly wait for D2H FIS */ |
732 | ata_tf_init(link->device, &tf); | |
9bbb1b0e | 733 | tf.command = ATA_BUSY; |
365cfa1e | 734 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
7d50b60b | 735 | |
365cfa1e AV |
736 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
737 | deadline, &online, NULL); | |
028a2596 | 738 | |
039ece38 | 739 | hpriv->start_engine(ap); |
c1332875 | 740 | |
365cfa1e AV |
741 | /* The pseudo configuration device on SIMG4726 attached to |
742 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
743 | * hardreset if no device is attached to the first downstream | |
744 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
745 | * work around this, wait for !BSY only briefly. If BSY isn't | |
746 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
747 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
748 | * | |
749 | * Wait for two seconds. Devices attached to downstream port | |
750 | * which can't process the following IDENTIFY after this will | |
751 | * have to be reset again. For most cases, this should | |
752 | * suffice while making probing snappish enough. | |
753 | */ | |
754 | if (online) { | |
755 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
756 | ahci_check_ready); | |
757 | if (rc) | |
758 | ahci_kick_engine(ap); | |
c1332875 | 759 | } |
c1332875 TH |
760 | return rc; |
761 | } | |
762 | ||
dbfe8ef5 DW |
763 | /* |
764 | * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. | |
765 | * | |
766 | * It has been observed with some SSDs that the timing of events in the | |
767 | * link synchronization phase can leave the port in a state that can not | |
768 | * be recovered by a SATA-hard-reset alone. The failing signature is | |
769 | * SStatus.DET stuck at 1 ("Device presence detected but Phy | |
770 | * communication not established"). It was found that unloading and | |
771 | * reloading the driver when this problem occurs allows the drive | |
772 | * connection to be recovered (DET advanced to 0x3). The critical | |
773 | * component of reloading the driver is that the port state machines are | |
774 | * reset by bouncing "port enable" in the AHCI PCS configuration | |
775 | * register. So, reproduce that effect by bouncing a port whenever we | |
776 | * see DET==1 after a reset. | |
777 | */ | |
778 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, | |
779 | unsigned long deadline) | |
780 | { | |
781 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
782 | struct ata_port *ap = link->ap; | |
783 | struct ahci_port_priv *pp = ap->private_data; | |
784 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
785 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
786 | unsigned long tmo = deadline - jiffies; | |
787 | struct ata_taskfile tf; | |
788 | bool online; | |
789 | int rc, i; | |
790 | ||
791 | DPRINTK("ENTER\n"); | |
792 | ||
fa89f53b | 793 | hpriv->stop_engine(ap); |
dbfe8ef5 DW |
794 | |
795 | for (i = 0; i < 2; i++) { | |
796 | u16 val; | |
797 | u32 sstatus; | |
798 | int port = ap->port_no; | |
799 | struct ata_host *host = ap->host; | |
800 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
801 | ||
802 | /* clear D2H reception area to properly wait for D2H FIS */ | |
803 | ata_tf_init(link->device, &tf); | |
804 | tf.command = ATA_BUSY; | |
805 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
806 | ||
807 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
808 | ahci_check_ready); | |
809 | ||
810 | if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || | |
811 | (sstatus & 0xf) != 1) | |
812 | break; | |
813 | ||
814 | ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", | |
815 | port); | |
816 | ||
817 | pci_read_config_word(pdev, 0x92, &val); | |
818 | val &= ~(1 << port); | |
819 | pci_write_config_word(pdev, 0x92, val); | |
820 | ata_msleep(ap, 1000); | |
821 | val |= 1 << port; | |
822 | pci_write_config_word(pdev, 0x92, val); | |
823 | deadline += tmo; | |
824 | } | |
825 | ||
826 | hpriv->start_engine(ap); | |
827 | ||
828 | if (online) | |
829 | *class = ahci_dev_classify(ap); | |
830 | ||
831 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
832 | return rc; | |
833 | } | |
834 | ||
835 | ||
02e53293 MW |
836 | #ifdef CONFIG_PM |
837 | static void ahci_pci_disable_interrupts(struct ata_host *host) | |
c1332875 | 838 | { |
9b10ae86 | 839 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 840 | void __iomem *mmio = hpriv->mmio; |
c1332875 TH |
841 | u32 ctl; |
842 | ||
f1d848f9 MW |
843 | /* AHCI spec rev1.1 section 8.3.3: |
844 | * Software must disable interrupts prior to requesting a | |
845 | * transition of the HBA to D3 state. | |
846 | */ | |
847 | ctl = readl(mmio + HOST_CTL); | |
848 | ctl &= ~HOST_IRQ_EN; | |
849 | writel(ctl, mmio + HOST_CTL); | |
850 | readl(mmio + HOST_CTL); /* flush */ | |
02e53293 MW |
851 | } |
852 | ||
853 | static int ahci_pci_device_runtime_suspend(struct device *dev) | |
854 | { | |
855 | struct pci_dev *pdev = to_pci_dev(dev); | |
856 | struct ata_host *host = pci_get_drvdata(pdev); | |
c1332875 | 857 | |
02e53293 MW |
858 | ahci_pci_disable_interrupts(host); |
859 | return 0; | |
860 | } | |
861 | ||
862 | static int ahci_pci_device_runtime_resume(struct device *dev) | |
863 | { | |
864 | struct pci_dev *pdev = to_pci_dev(dev); | |
865 | struct ata_host *host = pci_get_drvdata(pdev); | |
866 | int rc; | |
867 | ||
868 | rc = ahci_pci_reset_controller(host); | |
869 | if (rc) | |
870 | return rc; | |
871 | ahci_pci_init_controller(host); | |
872 | return 0; | |
873 | } | |
874 | ||
875 | #ifdef CONFIG_PM_SLEEP | |
876 | static int ahci_pci_device_suspend(struct device *dev) | |
877 | { | |
878 | struct pci_dev *pdev = to_pci_dev(dev); | |
879 | struct ata_host *host = pci_get_drvdata(pdev); | |
880 | struct ahci_host_priv *hpriv = host->private_data; | |
881 | ||
882 | if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
883 | dev_err(&pdev->dev, | |
884 | "BIOS update required for suspend/resume\n"); | |
885 | return -EIO; | |
886 | } | |
887 | ||
888 | ahci_pci_disable_interrupts(host); | |
f1d848f9 | 889 | return ata_host_suspend(host, PMSG_SUSPEND); |
c1332875 TH |
890 | } |
891 | ||
f1d848f9 | 892 | static int ahci_pci_device_resume(struct device *dev) |
c1332875 | 893 | { |
f1d848f9 | 894 | struct pci_dev *pdev = to_pci_dev(dev); |
0a86e1c8 | 895 | struct ata_host *host = pci_get_drvdata(pdev); |
c1332875 TH |
896 | int rc; |
897 | ||
cb85696d JL |
898 | /* Apple BIOS helpfully mangles the registers on resume */ |
899 | if (is_mcp89_apple(pdev)) | |
900 | ahci_mcp89_apple_enable(pdev); | |
901 | ||
c1332875 | 902 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
3303040d | 903 | rc = ahci_pci_reset_controller(host); |
c1332875 TH |
904 | if (rc) |
905 | return rc; | |
906 | ||
781d6550 | 907 | ahci_pci_init_controller(host); |
c1332875 TH |
908 | } |
909 | ||
cca3974e | 910 | ata_host_resume(host); |
c1332875 TH |
911 | |
912 | return 0; | |
913 | } | |
438ac6d5 | 914 | #endif |
c1332875 | 915 | |
02e53293 MW |
916 | #endif /* CONFIG_PM */ |
917 | ||
4447d351 | 918 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 919 | { |
1da177e4 | 920 | int rc; |
1da177e4 | 921 | |
318893e1 AR |
922 | /* |
923 | * If the device fixup already set the dma_mask to some non-standard | |
924 | * value, don't extend it here. This happens on STA2X11, for example. | |
925 | */ | |
926 | if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) | |
927 | return 0; | |
928 | ||
1da177e4 | 929 | if (using_dac && |
c54c719b QL |
930 | !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
931 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
1da177e4 | 932 | if (rc) { |
c54c719b | 933 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 934 | if (rc) { |
a44fec1f JP |
935 | dev_err(&pdev->dev, |
936 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
937 | return rc; |
938 | } | |
939 | } | |
1da177e4 | 940 | } else { |
c54c719b | 941 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 942 | if (rc) { |
a44fec1f | 943 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
1da177e4 LT |
944 | return rc; |
945 | } | |
c54c719b | 946 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 947 | if (rc) { |
a44fec1f JP |
948 | dev_err(&pdev->dev, |
949 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
950 | return rc; |
951 | } | |
952 | } | |
1da177e4 LT |
953 | return 0; |
954 | } | |
955 | ||
439fcaec AV |
956 | static void ahci_pci_print_info(struct ata_host *host) |
957 | { | |
958 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
959 | u16 cc; | |
960 | const char *scc_s; | |
961 | ||
962 | pci_read_config_word(pdev, 0x0a, &cc); | |
963 | if (cc == PCI_CLASS_STORAGE_IDE) | |
964 | scc_s = "IDE"; | |
965 | else if (cc == PCI_CLASS_STORAGE_SATA) | |
966 | scc_s = "SATA"; | |
967 | else if (cc == PCI_CLASS_STORAGE_RAID) | |
968 | scc_s = "RAID"; | |
969 | else | |
970 | scc_s = "unknown"; | |
971 | ||
972 | ahci_print_info(host, scc_s); | |
973 | } | |
974 | ||
edc93052 TH |
975 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
976 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
977 | * support PMP and the 4726 either directly exports the device | |
978 | * attached to the first downstream port or acts as a hardware storage | |
979 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
980 | * other configuration). | |
981 | * | |
982 | * When there's no device attached to the first downstream port of the | |
983 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
984 | * configure the 4726. However, ATA emulation of the device is very | |
985 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
986 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
987 | * | |
988 | * The following function works around the problem by always using | |
989 | * hardreset on the port and not depending on receiving signature FIS | |
990 | * afterward. If signature FIS isn't received soon, ATA class is | |
991 | * assumed without follow-up softreset. | |
992 | */ | |
993 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
994 | { | |
1bd06867 | 995 | static const struct dmi_system_id sysids[] = { |
edc93052 TH |
996 | { |
997 | .ident = "P5W DH Deluxe", | |
998 | .matches = { | |
999 | DMI_MATCH(DMI_SYS_VENDOR, | |
1000 | "ASUSTEK COMPUTER INC"), | |
1001 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
1002 | }, | |
1003 | }, | |
1004 | { } | |
1005 | }; | |
1006 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1007 | ||
1008 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
1009 | dmi_check_system(sysids)) { | |
1010 | struct ata_port *ap = host->ports[1]; | |
1011 | ||
a44fec1f JP |
1012 | dev_info(&pdev->dev, |
1013 | "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); | |
edc93052 TH |
1014 | |
1015 | ap->ops = &ahci_p5wdh_ops; | |
1016 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
1017 | } | |
1018 | } | |
1019 | ||
cb85696d JL |
1020 | /* |
1021 | * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when | |
1022 | * booting in BIOS compatibility mode. We restore the registers but not ID. | |
1023 | */ | |
1024 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev) | |
1025 | { | |
1026 | u32 val; | |
1027 | ||
1028 | printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); | |
1029 | ||
1030 | pci_read_config_dword(pdev, 0xf8, &val); | |
1031 | val |= 1 << 0x1b; | |
1032 | /* the following changes the device ID, but appears not to affect function */ | |
1033 | /* val = (val & ~0xf0000000) | 0x80000000; */ | |
1034 | pci_write_config_dword(pdev, 0xf8, val); | |
1035 | ||
1036 | pci_read_config_dword(pdev, 0x54c, &val); | |
1037 | val |= 1 << 0xc; | |
1038 | pci_write_config_dword(pdev, 0x54c, val); | |
1039 | ||
1040 | pci_read_config_dword(pdev, 0x4a4, &val); | |
1041 | val &= 0xff; | |
1042 | val |= 0x01060100; | |
1043 | pci_write_config_dword(pdev, 0x4a4, val); | |
1044 | ||
1045 | pci_read_config_dword(pdev, 0x54c, &val); | |
1046 | val &= ~(1 << 0xc); | |
1047 | pci_write_config_dword(pdev, 0x54c, val); | |
1048 | ||
1049 | pci_read_config_dword(pdev, 0xf8, &val); | |
1050 | val &= ~(1 << 0x1b); | |
1051 | pci_write_config_dword(pdev, 0xf8, val); | |
1052 | } | |
1053 | ||
1054 | static bool is_mcp89_apple(struct pci_dev *pdev) | |
1055 | { | |
1056 | return pdev->vendor == PCI_VENDOR_ID_NVIDIA && | |
1057 | pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && | |
1058 | pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
1059 | pdev->subsystem_device == 0xcb89; | |
1060 | } | |
1061 | ||
2fcad9d2 TH |
1062 | /* only some SB600 ahci controllers can do 64bit DMA */ |
1063 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) | |
58a09b38 SH |
1064 | { |
1065 | static const struct dmi_system_id sysids[] = { | |
03d783bf TH |
1066 | /* |
1067 | * The oldest version known to be broken is 0901 and | |
1068 | * working is 1501 which was released on 2007-10-26. | |
2fcad9d2 TH |
1069 | * Enable 64bit DMA on 1501 and anything newer. |
1070 | * | |
03d783bf TH |
1071 | * Please read bko#9412 for more info. |
1072 | */ | |
58a09b38 SH |
1073 | { |
1074 | .ident = "ASUS M2A-VM", | |
1075 | .matches = { | |
1076 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1077 | "ASUSTeK Computer INC."), | |
1078 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), | |
1079 | }, | |
03d783bf | 1080 | .driver_data = "20071026", /* yyyymmdd */ |
58a09b38 | 1081 | }, |
e65cc194 MN |
1082 | /* |
1083 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) | |
1084 | * support 64bit DMA. | |
1085 | * | |
1086 | * BIOS versions earlier than 1.5 had the Manufacturer DMI | |
1087 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". | |
1088 | * This spelling mistake was fixed in BIOS version 1.5, so | |
1089 | * 1.5 and later have the Manufacturer as | |
1090 | * "MICRO-STAR INTERNATIONAL CO.,LTD". | |
1091 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". | |
1092 | * | |
1093 | * BIOS versions earlier than 1.9 had a Board Product Name | |
1094 | * DMI field of "MS-7376". This was changed to be | |
1095 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still | |
1096 | * match on DMI_BOARD_NAME of "MS-7376". | |
1097 | */ | |
1098 | { | |
1099 | .ident = "MSI K9A2 Platinum", | |
1100 | .matches = { | |
1101 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1102 | "MICRO-STAR INTER"), | |
1103 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), | |
1104 | }, | |
1105 | }, | |
ff0173c1 MN |
1106 | /* |
1107 | * All BIOS versions for the MSI K9AGM2 (MS-7327) support | |
1108 | * 64bit DMA. | |
1109 | * | |
1110 | * This board also had the typo mentioned above in the | |
1111 | * Manufacturer DMI field (fixed in BIOS version 1.5), so | |
1112 | * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. | |
1113 | */ | |
1114 | { | |
1115 | .ident = "MSI K9AGM2", | |
1116 | .matches = { | |
1117 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1118 | "MICRO-STAR INTER"), | |
1119 | DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), | |
1120 | }, | |
1121 | }, | |
3c4aa91f MN |
1122 | /* |
1123 | * All BIOS versions for the Asus M3A support 64bit DMA. | |
1124 | * (all release versions from 0301 to 1206 were tested) | |
1125 | */ | |
1126 | { | |
1127 | .ident = "ASUS M3A", | |
1128 | .matches = { | |
1129 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1130 | "ASUSTeK Computer INC."), | |
1131 | DMI_MATCH(DMI_BOARD_NAME, "M3A"), | |
1132 | }, | |
1133 | }, | |
58a09b38 SH |
1134 | { } |
1135 | }; | |
03d783bf | 1136 | const struct dmi_system_id *match; |
2fcad9d2 TH |
1137 | int year, month, date; |
1138 | char buf[9]; | |
58a09b38 | 1139 | |
03d783bf | 1140 | match = dmi_first_match(sysids); |
58a09b38 | 1141 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
03d783bf | 1142 | !match) |
58a09b38 SH |
1143 | return false; |
1144 | ||
e65cc194 MN |
1145 | if (!match->driver_data) |
1146 | goto enable_64bit; | |
1147 | ||
2fcad9d2 TH |
1148 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1149 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
03d783bf | 1150 | |
e65cc194 MN |
1151 | if (strcmp(buf, match->driver_data) >= 0) |
1152 | goto enable_64bit; | |
1153 | else { | |
a44fec1f JP |
1154 | dev_warn(&pdev->dev, |
1155 | "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", | |
1156 | match->ident); | |
2fcad9d2 TH |
1157 | return false; |
1158 | } | |
e65cc194 MN |
1159 | |
1160 | enable_64bit: | |
a44fec1f | 1161 | dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); |
e65cc194 | 1162 | return true; |
58a09b38 SH |
1163 | } |
1164 | ||
1fd68434 RW |
1165 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
1166 | { | |
1167 | static const struct dmi_system_id broken_systems[] = { | |
1168 | { | |
1169 | .ident = "HP Compaq nx6310", | |
1170 | .matches = { | |
1171 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1172 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
1173 | }, | |
1174 | /* PCI slot number of the controller */ | |
1175 | .driver_data = (void *)0x1FUL, | |
1176 | }, | |
d2f9c061 MR |
1177 | { |
1178 | .ident = "HP Compaq 6720s", | |
1179 | .matches = { | |
1180 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1181 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
1182 | }, | |
1183 | /* PCI slot number of the controller */ | |
1184 | .driver_data = (void *)0x1FUL, | |
1185 | }, | |
1fd68434 RW |
1186 | |
1187 | { } /* terminate list */ | |
1188 | }; | |
1189 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1190 | ||
1191 | if (dmi) { | |
1192 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1193 | /* apply the quirk only to on-board controllers */ | |
1194 | return slot == PCI_SLOT(pdev->devfn); | |
1195 | } | |
1196 | ||
1197 | return false; | |
1198 | } | |
1199 | ||
9b10ae86 TH |
1200 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
1201 | { | |
1202 | static const struct dmi_system_id sysids[] = { | |
1203 | /* | |
1204 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
1205 | * to the harddisk doesn't become online after | |
1206 | * resuming from STR. Warn and fail suspend. | |
9deb3431 TH |
1207 | * |
1208 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 | |
1209 | * | |
1210 | * Use dates instead of versions to match as HP is | |
1211 | * apparently recycling both product and version | |
1212 | * strings. | |
1213 | * | |
1214 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 | |
9b10ae86 TH |
1215 | */ |
1216 | { | |
1217 | .ident = "dv4", | |
1218 | .matches = { | |
1219 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1220 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1221 | "HP Pavilion dv4 Notebook PC"), | |
1222 | }, | |
9deb3431 | 1223 | .driver_data = "20090105", /* F.30 */ |
9b10ae86 TH |
1224 | }, |
1225 | { | |
1226 | .ident = "dv5", | |
1227 | .matches = { | |
1228 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1229 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1230 | "HP Pavilion dv5 Notebook PC"), | |
1231 | }, | |
9deb3431 | 1232 | .driver_data = "20090506", /* F.16 */ |
9b10ae86 TH |
1233 | }, |
1234 | { | |
1235 | .ident = "dv6", | |
1236 | .matches = { | |
1237 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1238 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1239 | "HP Pavilion dv6 Notebook PC"), | |
1240 | }, | |
9deb3431 | 1241 | .driver_data = "20090423", /* F.21 */ |
9b10ae86 TH |
1242 | }, |
1243 | { | |
1244 | .ident = "HDX18", | |
1245 | .matches = { | |
1246 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1247 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1248 | "HP HDX18 Notebook PC"), | |
1249 | }, | |
9deb3431 | 1250 | .driver_data = "20090430", /* F.23 */ |
9b10ae86 | 1251 | }, |
cedc9bf9 TH |
1252 | /* |
1253 | * Acer eMachines G725 has the same problem. BIOS | |
1254 | * V1.03 is known to be broken. V3.04 is known to | |
25985edc | 1255 | * work. Between, there are V1.06, V2.06 and V3.03 |
cedc9bf9 TH |
1256 | * that we don't have much idea about. For now, |
1257 | * blacklist anything older than V3.04. | |
9deb3431 TH |
1258 | * |
1259 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 | |
cedc9bf9 TH |
1260 | */ |
1261 | { | |
1262 | .ident = "G725", | |
1263 | .matches = { | |
1264 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), | |
1265 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), | |
1266 | }, | |
9deb3431 | 1267 | .driver_data = "20091216", /* V3.04 */ |
cedc9bf9 | 1268 | }, |
9b10ae86 TH |
1269 | { } /* terminate list */ |
1270 | }; | |
1271 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
9deb3431 TH |
1272 | int year, month, date; |
1273 | char buf[9]; | |
9b10ae86 TH |
1274 | |
1275 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
1276 | return false; | |
1277 | ||
9deb3431 TH |
1278 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1279 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
9b10ae86 | 1280 | |
9deb3431 | 1281 | return strcmp(buf, dmi->driver_data) < 0; |
9b10ae86 TH |
1282 | } |
1283 | ||
240630e6 HG |
1284 | static bool ahci_broken_lpm(struct pci_dev *pdev) |
1285 | { | |
1286 | static const struct dmi_system_id sysids[] = { | |
1287 | /* Various Lenovo 50 series have LPM issues with older BIOSen */ | |
1288 | { | |
1289 | .matches = { | |
1290 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1291 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), | |
1292 | }, | |
1293 | .driver_data = "20180406", /* 1.31 */ | |
1294 | }, | |
1295 | { | |
1296 | .matches = { | |
1297 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1298 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), | |
1299 | }, | |
1300 | .driver_data = "20180420", /* 1.28 */ | |
1301 | }, | |
1302 | { | |
1303 | .matches = { | |
1304 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1305 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), | |
1306 | }, | |
1307 | .driver_data = "20180315", /* 1.33 */ | |
1308 | }, | |
1309 | { | |
1310 | .matches = { | |
1311 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1312 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), | |
1313 | }, | |
1314 | /* | |
1315 | * Note date based on release notes, 2.35 has been | |
1316 | * reported to be good, but I've been unable to get | |
1317 | * a hold of the reporter to get the DMI BIOS date. | |
1318 | * TODO: fix this. | |
1319 | */ | |
1320 | .driver_data = "20180310", /* 2.35 */ | |
1321 | }, | |
1322 | { } /* terminate list */ | |
1323 | }; | |
1324 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1325 | int year, month, date; | |
1326 | char buf[9]; | |
1327 | ||
1328 | if (!dmi) | |
1329 | return false; | |
1330 | ||
1331 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); | |
1332 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
1333 | ||
1334 | return strcmp(buf, dmi->driver_data) < 0; | |
1335 | } | |
1336 | ||
5594639a TH |
1337 | static bool ahci_broken_online(struct pci_dev *pdev) |
1338 | { | |
1339 | #define ENCODE_BUSDEVFN(bus, slot, func) \ | |
1340 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) | |
1341 | static const struct dmi_system_id sysids[] = { | |
1342 | /* | |
1343 | * There are several gigabyte boards which use | |
1344 | * SIMG5723s configured as hardware RAID. Certain | |
1345 | * 5723 firmware revisions shipped there keep the link | |
1346 | * online but fail to answer properly to SRST or | |
1347 | * IDENTIFY when no device is attached downstream | |
1348 | * causing libata to retry quite a few times leading | |
1349 | * to excessive detection delay. | |
1350 | * | |
1351 | * As these firmwares respond to the second reset try | |
1352 | * with invalid device signature, considering unknown | |
1353 | * sig as offline works around the problem acceptably. | |
1354 | */ | |
1355 | { | |
1356 | .ident = "EP45-DQ6", | |
1357 | .matches = { | |
1358 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1359 | "Gigabyte Technology Co., Ltd."), | |
1360 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), | |
1361 | }, | |
1362 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), | |
1363 | }, | |
1364 | { | |
1365 | .ident = "EP45-DS5", | |
1366 | .matches = { | |
1367 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1368 | "Gigabyte Technology Co., Ltd."), | |
1369 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), | |
1370 | }, | |
1371 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), | |
1372 | }, | |
1373 | { } /* terminate list */ | |
1374 | }; | |
1375 | #undef ENCODE_BUSDEVFN | |
1376 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1377 | unsigned int val; | |
1378 | ||
1379 | if (!dmi) | |
1380 | return false; | |
1381 | ||
1382 | val = (unsigned long)dmi->driver_data; | |
1383 | ||
1384 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); | |
1385 | } | |
1386 | ||
0cf4a7d6 JP |
1387 | static bool ahci_broken_devslp(struct pci_dev *pdev) |
1388 | { | |
1389 | /* device with broken DEVSLP but still showing SDS capability */ | |
1390 | static const struct pci_device_id ids[] = { | |
1391 | { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ | |
1392 | {} | |
1393 | }; | |
1394 | ||
1395 | return pci_match_id(ids, pdev); | |
1396 | } | |
1397 | ||
8e513217 | 1398 | #ifdef CONFIG_ATA_ACPI |
f80ae7e4 TH |
1399 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
1400 | { | |
1401 | static const struct dmi_system_id sysids[] = { | |
1402 | /* | |
1403 | * Aspire 3810T issues a bunch of SATA enable commands | |
1404 | * via _GTF including an invalid one and one which is | |
1405 | * rejected by the device. Among the successful ones | |
1406 | * is FPDMA non-zero offset enable which when enabled | |
1407 | * only on the drive side leads to NCQ command | |
1408 | * failures. Filter it out. | |
1409 | */ | |
1410 | { | |
1411 | .ident = "Aspire 3810T", | |
1412 | .matches = { | |
1413 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1414 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), | |
1415 | }, | |
1416 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, | |
1417 | }, | |
1418 | { } | |
1419 | }; | |
1420 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1421 | unsigned int filter; | |
1422 | int i; | |
1423 | ||
1424 | if (!dmi) | |
1425 | return; | |
1426 | ||
1427 | filter = (unsigned long)dmi->driver_data; | |
a44fec1f JP |
1428 | dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", |
1429 | filter, dmi->ident); | |
f80ae7e4 TH |
1430 | |
1431 | for (i = 0; i < host->n_ports; i++) { | |
1432 | struct ata_port *ap = host->ports[i]; | |
1433 | struct ata_link *link; | |
1434 | struct ata_device *dev; | |
1435 | ||
1436 | ata_for_each_link(link, ap, EDGE) | |
1437 | ata_for_each_dev(dev, link, ALL) | |
1438 | dev->gtf_filter |= filter; | |
1439 | } | |
1440 | } | |
8e513217 MT |
1441 | #else |
1442 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) | |
1443 | {} | |
1444 | #endif | |
f80ae7e4 | 1445 | |
8bfd1743 SC |
1446 | /* |
1447 | * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected | |
1448 | * as DUMMY, or detected but eventually get a "link down" and never get up | |
1449 | * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the | |
1450 | * port_map may hold a value of 0x00. | |
1451 | * | |
1452 | * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports | |
1453 | * and can significantly reduce the occurrence of the problem. | |
1454 | * | |
1455 | * https://bugzilla.kernel.org/show_bug.cgi?id=189471 | |
1456 | */ | |
1457 | static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, | |
1458 | struct pci_dev *pdev) | |
1459 | { | |
1460 | static const struct dmi_system_id sysids[] = { | |
1461 | { | |
1462 | .ident = "Acer Switch Alpha 12", | |
1463 | .matches = { | |
1464 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1465 | DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") | |
1466 | }, | |
1467 | }, | |
1468 | { } | |
1469 | }; | |
1470 | ||
1471 | if (dmi_check_system(sysids)) { | |
1472 | dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); | |
1473 | if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { | |
1474 | hpriv->port_map = 0x7; | |
1475 | hpriv->cap = 0xC734FF02; | |
1476 | } | |
1477 | } | |
1478 | } | |
1479 | ||
d243bed3 TC |
1480 | #ifdef CONFIG_ARM64 |
1481 | /* | |
1482 | * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. | |
1483 | * Workaround is to make sure all pending IRQs are served before leaving | |
1484 | * handler. | |
1485 | */ | |
1486 | static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) | |
1487 | { | |
1488 | struct ata_host *host = dev_instance; | |
1489 | struct ahci_host_priv *hpriv; | |
1490 | unsigned int rc = 0; | |
1491 | void __iomem *mmio; | |
1492 | u32 irq_stat, irq_masked; | |
1493 | unsigned int handled = 1; | |
1494 | ||
1495 | VPRINTK("ENTER\n"); | |
1496 | hpriv = host->private_data; | |
1497 | mmio = hpriv->mmio; | |
1498 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1499 | if (!irq_stat) | |
1500 | return IRQ_NONE; | |
1501 | ||
1502 | do { | |
1503 | irq_masked = irq_stat & hpriv->port_map; | |
1504 | spin_lock(&host->lock); | |
1505 | rc = ahci_handle_port_intr(host, irq_masked); | |
1506 | if (!rc) | |
1507 | handled = 0; | |
1508 | writel(irq_stat, mmio + HOST_IRQ_STAT); | |
1509 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1510 | spin_unlock(&host->lock); | |
1511 | } while (irq_stat); | |
1512 | VPRINTK("EXIT\n"); | |
1513 | ||
1514 | return IRQ_RETVAL(handled); | |
1515 | } | |
1516 | #endif | |
1517 | ||
aecec8b6 CH |
1518 | static void ahci_remap_check(struct pci_dev *pdev, int bar, |
1519 | struct ahci_host_priv *hpriv) | |
1520 | { | |
1521 | int i, count = 0; | |
1522 | u32 cap; | |
1523 | ||
1524 | /* | |
1525 | * Check if this device might have remapped nvme devices. | |
1526 | */ | |
1527 | if (pdev->vendor != PCI_VENDOR_ID_INTEL || | |
1528 | pci_resource_len(pdev, bar) < SZ_512K || | |
1529 | bar != AHCI_PCI_BAR_STANDARD || | |
1530 | !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) | |
1531 | return; | |
1532 | ||
1533 | cap = readq(hpriv->mmio + AHCI_REMAP_CAP); | |
1534 | for (i = 0; i < AHCI_MAX_REMAP; i++) { | |
1535 | if ((cap & (1 << i)) == 0) | |
1536 | continue; | |
1537 | if (readl(hpriv->mmio + ahci_remap_dcc(i)) | |
1538 | != PCI_CLASS_STORAGE_EXPRESS) | |
1539 | continue; | |
1540 | ||
1541 | /* We've found a remapped device */ | |
1542 | count++; | |
1543 | } | |
1544 | ||
1545 | if (!count) | |
1546 | return; | |
1547 | ||
1548 | dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); | |
f723fa4e CH |
1549 | dev_warn(&pdev->dev, |
1550 | "Switch your BIOS from RAID to AHCI mode to use them.\n"); | |
1551 | ||
1552 | /* | |
1553 | * Don't rely on the msi-x capability in the remap case, | |
1554 | * share the legacy interrupt across ahci and remapped devices. | |
1555 | */ | |
1556 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
aecec8b6 CH |
1557 | } |
1558 | ||
0b9e2988 | 1559 | static int ahci_get_irq_vector(struct ata_host *host, int port) |
5ca72c4f | 1560 | { |
0b9e2988 | 1561 | return pci_irq_vector(to_pci_dev(host->dev), port); |
ee2aad42 RR |
1562 | } |
1563 | ||
a1c82311 RR |
1564 | static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, |
1565 | struct ahci_host_priv *hpriv) | |
5ca72c4f | 1566 | { |
0b9e2988 | 1567 | int nvec; |
5ca72c4f | 1568 | |
7b92b4f6 | 1569 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
a1c82311 | 1570 | return -ENODEV; |
7b92b4f6 | 1571 | |
7b92b4f6 AG |
1572 | /* |
1573 | * If number of MSIs is less than number of ports then Sharing Last | |
1574 | * Message mode could be enforced. In this case assume that advantage | |
1575 | * of multipe MSIs is negated and use single MSI mode instead. | |
1576 | */ | |
17a51f12 CH |
1577 | if (n_ports > 1) { |
1578 | nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, | |
1579 | PCI_IRQ_MSIX | PCI_IRQ_MSI); | |
1580 | if (nvec > 0) { | |
1581 | if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { | |
1582 | hpriv->get_irq_vector = ahci_get_irq_vector; | |
1583 | hpriv->flags |= AHCI_HFLAG_MULTI_MSI; | |
1584 | return nvec; | |
1585 | } | |
5ca72c4f | 1586 | |
17a51f12 CH |
1587 | /* |
1588 | * Fallback to single MSI mode if the controller | |
1589 | * enforced MRSM mode. | |
1590 | */ | |
1591 | printk(KERN_INFO | |
1592 | "ahci: MRSM is on, fallback to single MSI\n"); | |
1593 | pci_free_irq_vectors(pdev); | |
1594 | } | |
a478b097 | 1595 | } |
d684a90d | 1596 | |
0b9e2988 CH |
1597 | /* |
1598 | * If the host is not capable of supporting per-port vectors, fall | |
1599 | * back to single MSI before finally attempting single MSI-X. | |
1600 | */ | |
1601 | nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); | |
1602 | if (nvec == 1) | |
ee2aad42 | 1603 | return nvec; |
0b9e2988 | 1604 | return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); |
5ca72c4f AG |
1605 | } |
1606 | ||
24dc5f33 | 1607 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1608 | { |
e297d99e TH |
1609 | unsigned int board_id = ent->driver_data; |
1610 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 1611 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 1612 | struct device *dev = &pdev->dev; |
1da177e4 | 1613 | struct ahci_host_priv *hpriv; |
4447d351 | 1614 | struct ata_host *host; |
c3ebd6a9 | 1615 | int n_ports, i, rc; |
318893e1 | 1616 | int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; |
1da177e4 LT |
1617 | |
1618 | VPRINTK("ENTER\n"); | |
1619 | ||
b429dd59 | 1620 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
12fad3f9 | 1621 | |
06296a1e | 1622 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1623 | |
5b66c829 AC |
1624 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
1625 | can drive them all so if both drivers are selected make sure | |
1626 | AHCI stays out of the way */ | |
1627 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
1628 | return -ENODEV; | |
1629 | ||
cb85696d JL |
1630 | /* Apple BIOS on MCP89 prevents us using AHCI */ |
1631 | if (is_mcp89_apple(pdev)) | |
1632 | ahci_mcp89_apple_enable(pdev); | |
c6353b45 | 1633 | |
7a02267e MN |
1634 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
1635 | * At the moment, we can only use the AHCI mode. Let the users know | |
1636 | * that for SAS drives they're out of luck. | |
1637 | */ | |
1638 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) | |
a44fec1f JP |
1639 | dev_info(&pdev->dev, |
1640 | "PDC42819 can only drive SATA devices with this driver\n"); | |
7a02267e | 1641 | |
b7ae128d | 1642 | /* Some devices use non-standard BARs */ |
318893e1 AR |
1643 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) |
1644 | ahci_pci_bar = AHCI_PCI_BAR_STA2X11; | |
7f9c9f8e HD |
1645 | else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) |
1646 | ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; | |
b1314e3f RMC |
1647 | else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { |
1648 | if (pdev->device == 0xa01c) | |
1649 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; | |
1650 | if (pdev->device == 0xa084) | |
1651 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; | |
1652 | } | |
318893e1 | 1653 | |
4447d351 | 1654 | /* acquire resources */ |
24dc5f33 | 1655 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1656 | if (rc) |
1657 | return rc; | |
1658 | ||
c4f7792c TH |
1659 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
1660 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
1661 | u8 map; | |
1662 | ||
1663 | /* ICH6s share the same PCI ID for both piix and ahci | |
1664 | * modes. Enabling ahci mode while MAP indicates | |
1665 | * combined mode is a bad idea. Yield to ata_piix. | |
1666 | */ | |
1667 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
1668 | if (map & 0x3) { | |
a44fec1f JP |
1669 | dev_info(&pdev->dev, |
1670 | "controller is in combined mode, can't enable AHCI mode\n"); | |
c4f7792c TH |
1671 | return -ENODEV; |
1672 | } | |
1673 | } | |
1674 | ||
6fec8871 PB |
1675 | /* AHCI controllers often implement SFF compatible interface. |
1676 | * Grab all PCI BARs just in case. | |
1677 | */ | |
1678 | rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); | |
1679 | if (rc == -EBUSY) | |
1680 | pcim_pin_device(pdev); | |
1681 | if (rc) | |
1682 | return rc; | |
1683 | ||
24dc5f33 TH |
1684 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1685 | if (!hpriv) | |
1686 | return -ENOMEM; | |
417a1a6d TH |
1687 | hpriv->flags |= (unsigned long)pi.private_data; |
1688 | ||
e297d99e TH |
1689 | /* MCP65 revision A1 and A2 can't do MSI */ |
1690 | if (board_id == board_ahci_mcp65 && | |
1691 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
1692 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
1693 | ||
e427fe04 SH |
1694 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
1695 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
1696 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
1697 | ||
2fcad9d2 TH |
1698 | /* only some SB600s can do 64bit DMA */ |
1699 | if (ahci_sb600_enable_64bit(pdev)) | |
1700 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; | |
58a09b38 | 1701 | |
318893e1 | 1702 | hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; |
d8993349 | 1703 | |
aecec8b6 CH |
1704 | /* detect remapped nvme devices */ |
1705 | ahci_remap_check(pdev, ahci_pci_bar, hpriv); | |
1706 | ||
0cf4a7d6 JP |
1707 | /* must set flag prior to save config in order to take effect */ |
1708 | if (ahci_broken_devslp(pdev)) | |
1709 | hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; | |
1710 | ||
d243bed3 TC |
1711 | #ifdef CONFIG_ARM64 |
1712 | if (pdev->vendor == 0x177d && pdev->device == 0xa01c) | |
1713 | hpriv->irq_handler = ahci_thunderx_irq_handler; | |
1714 | #endif | |
1715 | ||
4447d351 | 1716 | /* save initial config */ |
394d6e53 | 1717 | ahci_pci_save_initial_config(pdev, hpriv); |
1da177e4 | 1718 | |
4447d351 | 1719 | /* prepare host */ |
453d3131 RH |
1720 | if (hpriv->cap & HOST_CAP_NCQ) { |
1721 | pi.flags |= ATA_FLAG_NCQ; | |
83f2b963 TH |
1722 | /* |
1723 | * Auto-activate optimization is supposed to be | |
1724 | * supported on all AHCI controllers indicating NCQ | |
1725 | * capability, but it seems to be broken on some | |
1726 | * chipsets including NVIDIAs. | |
1727 | */ | |
1728 | if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) | |
453d3131 | 1729 | pi.flags |= ATA_FLAG_FPDMA_AA; |
40fb59e7 MC |
1730 | |
1731 | /* | |
1732 | * All AHCI controllers should be forward-compatible | |
1733 | * with the new auxiliary field. This code should be | |
1734 | * conditionalized if any buggy AHCI controllers are | |
1735 | * encountered. | |
1736 | */ | |
1737 | pi.flags |= ATA_FLAG_FPDMA_AUX; | |
453d3131 | 1738 | } |
1da177e4 | 1739 | |
7d50b60b TH |
1740 | if (hpriv->cap & HOST_CAP_PMP) |
1741 | pi.flags |= ATA_FLAG_PMP; | |
1742 | ||
0cbb0e77 | 1743 | ahci_set_em_messages(hpriv, &pi); |
18f7ba4c | 1744 | |
1fd68434 RW |
1745 | if (ahci_broken_system_poweroff(pdev)) { |
1746 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
1747 | dev_info(&pdev->dev, | |
1748 | "quirky BIOS, skipping spindown on poweroff\n"); | |
1749 | } | |
1750 | ||
240630e6 HG |
1751 | if (ahci_broken_lpm(pdev)) { |
1752 | pi.flags |= ATA_FLAG_NO_LPM; | |
1753 | dev_warn(&pdev->dev, | |
1754 | "BIOS update required for Link Power Management support\n"); | |
1755 | } | |
1756 | ||
9b10ae86 TH |
1757 | if (ahci_broken_suspend(pdev)) { |
1758 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
a44fec1f JP |
1759 | dev_warn(&pdev->dev, |
1760 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
1761 | } |
1762 | ||
5594639a TH |
1763 | if (ahci_broken_online(pdev)) { |
1764 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; | |
1765 | dev_info(&pdev->dev, | |
1766 | "online status unreliable, applying workaround\n"); | |
1767 | } | |
1768 | ||
8bfd1743 SC |
1769 | |
1770 | /* Acer SA5-271 workaround modifies private_data */ | |
1771 | acer_sa5_271_workaround(hpriv, pdev); | |
1772 | ||
837f5f8f TH |
1773 | /* CAP.NP sometimes indicate the index of the last enabled |
1774 | * port, at other times, that of the last possible port, so | |
1775 | * determining the maximum port number requires looking at | |
1776 | * both CAP.NP and port_map. | |
1777 | */ | |
1778 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
1779 | ||
1780 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
1781 | if (!host) |
1782 | return -ENOMEM; | |
4447d351 | 1783 | host->private_data = hpriv; |
0b9e2988 CH |
1784 | |
1785 | if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { | |
1786 | /* legacy intx interrupts */ | |
1787 | pci_intx(pdev, 1); | |
1788 | } | |
0ce57f8a | 1789 | hpriv->irq = pci_irq_vector(pdev, 0); |
21bfd1aa | 1790 | |
f3d7f23f | 1791 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 1792 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f | 1793 | else |
d2782d96 | 1794 | dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); |
886ad09f | 1795 | |
18f7ba4c KCA |
1796 | if (pi.flags & ATA_FLAG_EM) |
1797 | ahci_reset_em(host); | |
1798 | ||
4447d351 | 1799 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 1800 | struct ata_port *ap = host->ports[i]; |
4447d351 | 1801 | |
318893e1 AR |
1802 | ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); |
1803 | ata_port_pbar_desc(ap, ahci_pci_bar, | |
cbcdd875 TH |
1804 | 0x100 + ap->port_no * 0x80, "port"); |
1805 | ||
18f7ba4c KCA |
1806 | /* set enclosure management message type */ |
1807 | if (ap->flags & ATA_FLAG_EM) | |
008dbd61 | 1808 | ap->em_message_type = hpriv->em_msg_type; |
18f7ba4c | 1809 | |
ebb82e3c HG |
1810 | if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) && |
1811 | mobile_lpm_policy >= ATA_LPM_UNKNOWN && | |
1812 | mobile_lpm_policy <= ATA_LPM_MIN_POWER) | |
1813 | ap->target_lpm_policy = mobile_lpm_policy; | |
18f7ba4c | 1814 | |
dab632e8 | 1815 | /* disabled/not-implemented port */ |
350756f6 | 1816 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 1817 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 1818 | } |
d447df14 | 1819 | |
edc93052 TH |
1820 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
1821 | ahci_p5wdh_workaround(host); | |
1822 | ||
f80ae7e4 TH |
1823 | /* apply gtf filter quirk */ |
1824 | ahci_gtf_filter_workaround(host); | |
1825 | ||
4447d351 TH |
1826 | /* initialize adapter */ |
1827 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1828 | if (rc) |
24dc5f33 | 1829 | return rc; |
1da177e4 | 1830 | |
3303040d | 1831 | rc = ahci_pci_reset_controller(host); |
4447d351 TH |
1832 | if (rc) |
1833 | return rc; | |
1da177e4 | 1834 | |
781d6550 | 1835 | ahci_pci_init_controller(host); |
439fcaec | 1836 | ahci_pci_print_info(host); |
1da177e4 | 1837 | |
4447d351 | 1838 | pci_set_master(pdev); |
5ca72c4f | 1839 | |
02e53293 MW |
1840 | rc = ahci_host_activate(host, &ahci_sht); |
1841 | if (rc) | |
1842 | return rc; | |
1843 | ||
1844 | pm_runtime_put_noidle(&pdev->dev); | |
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | static void ahci_remove_one(struct pci_dev *pdev) | |
1849 | { | |
1850 | pm_runtime_get_noresume(&pdev->dev); | |
1851 | ata_pci_remove_one(pdev); | |
907f4678 | 1852 | } |
1da177e4 | 1853 | |
2fc75da0 | 1854 | module_pci_driver(ahci_pci_driver); |
1da177e4 LT |
1855 | |
1856 | MODULE_AUTHOR("Jeff Garzik"); | |
1857 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1858 | MODULE_LICENSE("GPL"); | |
1859 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1860 | MODULE_VERSION(DRV_VERSION); |