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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec
[linux-2.6-block.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 27 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
ee2aad42 45#include <linux/msi.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
aecec8b6
CH		 49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 51#include "ahci.h"
1da177e4
LT		 52
53#define DRV_NAME "ahci"
7d50b60b 54#define DRV_VERSION "3.0"
1da177e4 55
1da177e4 56enum {
318893e1 57 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 58 AHCI_PCI_BAR_CAVIUM = 0,
7f9c9f8e 59 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 60 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 61};
62
63enum board_ids {
64 /* board IDs by feature in alphabetical order */
65 board_ahci,
66 board_ahci_ign_iferr,
66a7cbc3 67 board_ahci_nomsi,
67809f85 68 board_ahci_noncq,
441577ef 69 board_ahci_nosntf,
5f173107 70 board_ahci_yes_fbs,
1da177e4 71
441577ef 72 /* board IDs for specific chipsets in alphabetical order */
dbfe8ef5 73 board_ahci_avn,
441577ef 74 board_ahci_mcp65,
83f2b963
TH		 75 board_ahci_mcp77,
76 board_ahci_mcp89,
441577ef
TH		 77 board_ahci_mv,
78 board_ahci_sb600,
79 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_vt8251,
81
82 /* aliases */
83 board_ahci_mcp_linux = board_ahci_mcp65,
84 board_ahci_mcp67 = board_ahci_mcp65,
85 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 86 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 87};
88
2dcb407e 89static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 90static void ahci_remove_one(struct pci_dev *dev);
a1efdaba
TH		 91static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
dbfe8ef5
DW		 93static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
cb85696d
JL		 95static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
96static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 97static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
98 unsigned long deadline);
02e53293
MW		 99#ifdef CONFIG_PM
100static int ahci_pci_device_runtime_suspend(struct device *dev);
101static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 102#ifdef CONFIG_PM_SLEEP
103static int ahci_pci_device_suspend(struct device *dev);
104static int ahci_pci_device_resume(struct device *dev);
438ac6d5 105#endif
02e53293 106#endif /* CONFIG_PM */
ad616ffb 107
fad16e7a
TH		 108static struct scsi_host_template ahci_sht = {
109 AHCI_SHT("ahci"),
110};
111
029cfd6b
TH		 112static struct ata_port_operations ahci_vt8251_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_vt8251_hardreset,
029cfd6b 115};
edc93052 116
029cfd6b
TH		 117static struct ata_port_operations ahci_p5wdh_ops = {
118 .inherits = &ahci_ops,
a1efdaba 119 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 120};
121
dbfe8ef5
DW		 122static struct ata_port_operations ahci_avn_ops = {
123 .inherits = &ahci_ops,
124 .hardreset = ahci_avn_hardreset,
125};
126
98ac62de 127static const struct ata_port_info ahci_port_info[] = {
441577ef 128 /* by features */
facb8fa6 129 [board_ahci] = {
1188c0d8 130 .flags = AHCI_FLAG_COMMON,
14bdef98 131 .pio_mask = ATA_PIO4,
469248ab 132 .udma_mask = ATA_UDMA6,
1da177e4
LT		 133 .port_ops = &ahci_ops,
134 },
facb8fa6 135 [board_ahci_ign_iferr] = {
441577ef 136 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 137 .flags = AHCI_FLAG_COMMON,
14bdef98 138 .pio_mask = ATA_PIO4,
469248ab 139 .udma_mask = ATA_UDMA6,
441577ef 140 .port_ops = &ahci_ops,
bf2af2a2 141 },
66a7cbc3
TH		 142 [board_ahci_nomsi] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
67809f85
LK		 149 [board_ahci_noncq] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
facb8fa6 156 [board_ahci_nosntf] = {
441577ef 157 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 158 .flags = AHCI_FLAG_COMMON,
14bdef98 159 .pio_mask = ATA_PIO4,
469248ab 160 .udma_mask = ATA_UDMA6,
41669553
TH		 161 .port_ops = &ahci_ops,
162 },
facb8fa6 163 [board_ahci_yes_fbs] = {
5f173107
TH		 164 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
441577ef 170 /* by chipsets */
dbfe8ef5
DW		 171 [board_ahci_avn] = {
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_avn_ops,
176 },
facb8fa6 177 [board_ahci_mcp65] = {
83f2b963
TH		 178 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 AHCI_HFLAG_YES_NCQ),
ae01b249 180 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
facb8fa6 185 [board_ahci_mcp77] = {
83f2b963
TH		 186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
facb8fa6 192 [board_ahci_mcp89] = {
83f2b963 193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 194 .flags = AHCI_FLAG_COMMON,
14bdef98 195 .pio_mask = ATA_PIO4,
469248ab 196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_ops,
55a61604 198 },
facb8fa6 199 [board_ahci_mv] = {
417a1a6d 200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 203 .pio_mask = ATA_PIO4,
cd70c266
JG		 204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
206 },
facb8fa6 207 [board_ahci_sb600] = {
441577ef
TH		 208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
209 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
210 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 211 .flags = AHCI_FLAG_COMMON,
14bdef98 212 .pio_mask = ATA_PIO4,
e39fc8c9 213 .udma_mask = ATA_UDMA6,
345347c5 214 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 215 },
facb8fa6 216 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
345347c5 221 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 222 },
facb8fa6 223 [board_ahci_vt8251] = {
441577ef 224 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
441577ef 228 .port_ops = &ahci_vt8251_ops,
1b677afd 229 },
1da177e4
LT		 230};
231
3b7d697d 232static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 233 /* Intel */
54bb3a94
JG		 234 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
235 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
236 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
237 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
238 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 239 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 240 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 244 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 245 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 246 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
248 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 261 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
262 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 263 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 264 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 265 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 266 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 268 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 269 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 270 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 271 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 272 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 273 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
342decff
AY		 274 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
5623cab8
SH		 294 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
297 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 300 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
301 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
302 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 303 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 304 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 305 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 311 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 312 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
313 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 320 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
321 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 328 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 336 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 344 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 346 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
347 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
351 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 354 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 355 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 359 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
360 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
362 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
249cd0a1
DR		 367 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
368 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
369 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
c5967b79 370 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
690000b9 371 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
690000b9 372 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 373 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
690000b9
JR		 374 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 376 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 377 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 378 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 379 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 380 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 381 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 382 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 384 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 385 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 386 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
fe7fa31a 388
e34bb370
TH		 389 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
390 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 392 /* JMicron 362B and 362C have an AHCI function with IDE class code */
393 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
394 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 395 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 396
397 /* ATI */
c65ec1c2 398 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 399 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 405
e2dd90b1 406 /* AMD */
5deab536 407 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 408 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 409 /* AMD is using RAID class only for ahci controllers */
410 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
412
fe7fa31a 413 /* VIA */
54bb3a94 414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 416
417 /* NVIDIA */
e297d99e
TH		 418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 502
95916edd 503 /* SiS */
20e2de4a
TH		 504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 507
318893e1
AR		 508 /* ST Microelectronics */
509 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
510
cd70c266
JG		 511 /* Marvell */
512 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 513 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 515 .class = PCI_CLASS_STORAGE_SATA_AHCI,
516 .class_mask = 0xffffff,
5f173107 517 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 519 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 520 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 524 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 526 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
534 .driver_data = board_ahci_yes_fbs },
69fd3157 535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 536 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 539 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
540 .driver_data = board_ahci_yes_fbs },
cd70c266 541
c77a036b
MN		 542 /* Promise */
543 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 544 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 545
c9703765 546 /* Asmedia */
7b4f6eca
AC		 547 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
548 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
549 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
550 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 551 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
552 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 553
67809f85 554 /*
66a7cbc3
TH		 555 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
556 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 557 */
66a7cbc3 558 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 559 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 560
7f9c9f8e
HD		 561 /* Enmotus */
562 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
563
415ae2b5
JG		 564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 567
1da177e4
LT		 568 { } /* terminate list */
569};
570
f1d848f9
MW		 571static const struct dev_pm_ops ahci_pci_pm_ops = {
572 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 573 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
574 ahci_pci_device_runtime_resume, NULL)
f1d848f9 575};
1da177e4
LT		 576
577static struct pci_driver ahci_pci_driver = {
578 .name = DRV_NAME,
579 .id_table = ahci_pci_tbl,
580 .probe = ahci_init_one,
02e53293 581 .remove = ahci_remove_one,
f1d848f9
MW		 582 .driver = {
583 .pm = &ahci_pci_pm_ops,
584 },
365cfa1e 585};
1da177e4 586
5219d653 587#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 588static int marvell_enable;
589#else
590static int marvell_enable = 1;
591#endif
592module_param(marvell_enable, int, 0644);
593MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 594
1da177e4 595
365cfa1e
AV		 596static void ahci_pci_save_initial_config(struct pci_dev *pdev,
597 struct ahci_host_priv *hpriv)
598{
365cfa1e
AV		 599 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
600 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 601 hpriv->force_port_map = 1;
1da177e4
LT		 602 }
603
365cfa1e
AV		 604 /*
605 * Temporary Marvell 6145 hack: PATA port presence
606 * is asserted through the standard AHCI port
607 * presence register, as bit 4 (counting from 0)
d28f87aa 608 */
365cfa1e
AV		 609 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
610 if (pdev->device == 0x6121)
9a23c1d6 611 hpriv->mask_port_map = 0x3;
365cfa1e 612 else
9a23c1d6 613 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 614 dev_info(&pdev->dev,
615 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
616 }
1da177e4 617
725c7b57 618 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 619}
620
365cfa1e 621static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 622{
365cfa1e 623 struct pci_dev *pdev = to_pci_dev(host->dev);
d312fefe 624 int rc;
7d50b60b 625
d312fefe
AB		 626 rc = ahci_reset_controller(host);
627 if (rc)
628 return rc;
1da177e4 629
365cfa1e
AV		 630 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
631 struct ahci_host_priv *hpriv = host->private_data;
632 u16 tmp16;
d6ef3153 633
365cfa1e
AV		 634 /* configure PCS */
635 pci_read_config_word(pdev, 0x92, &tmp16);
636 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
637 tmp16 |= hpriv->port_map;
638 pci_write_config_word(pdev, 0x92, tmp16);
639 }
d6ef3153
SH		 640 }
641
1da177e4
LT		 642 return 0;
643}
644
365cfa1e 645static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 646{
365cfa1e
AV		 647 struct ahci_host_priv *hpriv = host->private_data;
648 struct pci_dev *pdev = to_pci_dev(host->dev);
649 void __iomem *port_mmio;
78cd52d0 650 u32 tmp;
365cfa1e 651 int mv;
78cd52d0 652
365cfa1e
AV		 653 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
654 if (pdev->device == 0x6121)
655 mv = 2;
656 else
657 mv = 4;
658 port_mmio = __ahci_port_base(host, mv);
78cd52d0 659
365cfa1e 660 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 661
365cfa1e
AV		 662 /* clear port IRQ */
663 tmp = readl(port_mmio + PORT_IRQ_STAT);
664 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
665 if (tmp)
666 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 667 }
668
365cfa1e 669 ahci_init_controller(host);
edc93052
TH		 670}
671
365cfa1e
AV		 672static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
673 unsigned long deadline)
d6ef3153 674{
365cfa1e 675 struct ata_port *ap = link->ap;
039ece38 676 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 677 bool online;
d6ef3153
SH		 678 int rc;
679
365cfa1e 680 DPRINTK("ENTER\n");
d6ef3153 681
365cfa1e 682 ahci_stop_engine(ap);
d6ef3153 683
365cfa1e
AV		 684 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
685 deadline, &online, NULL);
d6ef3153 686
039ece38 687 hpriv->start_engine(ap);
d6ef3153 688
365cfa1e 689 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 690
365cfa1e
AV		 691 /* vt8251 doesn't clear BSY on signature FIS reception,
692 * request follow-up softreset.
693 */
694 return online ? -EAGAIN : rc;
7d50b60b
TH		 695}
696
365cfa1e
AV		 697static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
7d50b60b 699{
365cfa1e 700 struct ata_port *ap = link->ap;
1c954a4d 701 struct ahci_port_priv *pp = ap->private_data;
039ece38 702 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 703 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
704 struct ata_taskfile tf;
705 bool online;
706 int rc;
7d50b60b 707
365cfa1e 708 ahci_stop_engine(ap);
028a2596 709
365cfa1e
AV		 710 /* clear D2H reception area to properly wait for D2H FIS */
711 ata_tf_init(link->device, &tf);
9bbb1b0e 712 tf.command = ATA_BUSY;
365cfa1e 713 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 714
365cfa1e
AV		 715 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
716 deadline, &online, NULL);
028a2596 717
039ece38 718 hpriv->start_engine(ap);
c1332875 719
365cfa1e
AV		 720 /* The pseudo configuration device on SIMG4726 attached to
721 * ASUS P5W-DH Deluxe doesn't send signature FIS after
722 * hardreset if no device is attached to the first downstream
723 * port && the pseudo device locks up on SRST w/ PMP==0. To
724 * work around this, wait for !BSY only briefly. If BSY isn't
725 * cleared, perform CLO and proceed to IDENTIFY (achieved by
726 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
727 *
728 * Wait for two seconds. Devices attached to downstream port
729 * which can't process the following IDENTIFY after this will
730 * have to be reset again. For most cases, this should
731 * suffice while making probing snappish enough.
732 */
733 if (online) {
734 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
735 ahci_check_ready);
736 if (rc)
737 ahci_kick_engine(ap);
c1332875 738 }
c1332875
TH		 739 return rc;
740}
741
dbfe8ef5
DW		 742/*
743 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
744 *
745 * It has been observed with some SSDs that the timing of events in the
746 * link synchronization phase can leave the port in a state that can not
747 * be recovered by a SATA-hard-reset alone. The failing signature is
748 * SStatus.DET stuck at 1 ("Device presence detected but Phy
749 * communication not established"). It was found that unloading and
750 * reloading the driver when this problem occurs allows the drive
751 * connection to be recovered (DET advanced to 0x3). The critical
752 * component of reloading the driver is that the port state machines are
753 * reset by bouncing "port enable" in the AHCI PCS configuration
754 * register. So, reproduce that effect by bouncing a port whenever we
755 * see DET==1 after a reset.
756 */
757static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
758 unsigned long deadline)
759{
760 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
761 struct ata_port *ap = link->ap;
762 struct ahci_port_priv *pp = ap->private_data;
763 struct ahci_host_priv *hpriv = ap->host->private_data;
764 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
765 unsigned long tmo = deadline - jiffies;
766 struct ata_taskfile tf;
767 bool online;
768 int rc, i;
769
770 DPRINTK("ENTER\n");
771
772 ahci_stop_engine(ap);
773
774 for (i = 0; i < 2; i++) {
775 u16 val;
776 u32 sstatus;
777 int port = ap->port_no;
778 struct ata_host *host = ap->host;
779 struct pci_dev *pdev = to_pci_dev(host->dev);
780
781 /* clear D2H reception area to properly wait for D2H FIS */
782 ata_tf_init(link->device, &tf);
783 tf.command = ATA_BUSY;
784 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
785
786 rc = sata_link_hardreset(link, timing, deadline, &online,
787 ahci_check_ready);
788
789 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
790 (sstatus & 0xf) != 1)
791 break;
792
793 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
794 port);
795
796 pci_read_config_word(pdev, 0x92, &val);
797 val &= ~(1 << port);
798 pci_write_config_word(pdev, 0x92, val);
799 ata_msleep(ap, 1000);
800 val |= 1 << port;
801 pci_write_config_word(pdev, 0x92, val);
802 deadline += tmo;
803 }
804
805 hpriv->start_engine(ap);
806
807 if (online)
808 *class = ahci_dev_classify(ap);
809
810 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
811 return rc;
812}
813
814
02e53293
MW		 815#ifdef CONFIG_PM
816static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 817{
9b10ae86 818 struct ahci_host_priv *hpriv = host->private_data;
d8993349 819 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 820 u32 ctl;
821
f1d848f9
MW		 822 /* AHCI spec rev1.1 section 8.3.3:
823 * Software must disable interrupts prior to requesting a
824 * transition of the HBA to D3 state.
825 */
826 ctl = readl(mmio + HOST_CTL);
827 ctl &= ~HOST_IRQ_EN;
828 writel(ctl, mmio + HOST_CTL);
829 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 830}
831
832static int ahci_pci_device_runtime_suspend(struct device *dev)
833{
834 struct pci_dev *pdev = to_pci_dev(dev);
835 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 836
02e53293
MW		 837 ahci_pci_disable_interrupts(host);
838 return 0;
839}
840
841static int ahci_pci_device_runtime_resume(struct device *dev)
842{
843 struct pci_dev *pdev = to_pci_dev(dev);
844 struct ata_host *host = pci_get_drvdata(pdev);
845 int rc;
846
847 rc = ahci_pci_reset_controller(host);
848 if (rc)
849 return rc;
850 ahci_pci_init_controller(host);
851 return 0;
852}
853
854#ifdef CONFIG_PM_SLEEP
855static int ahci_pci_device_suspend(struct device *dev)
856{
857 struct pci_dev *pdev = to_pci_dev(dev);
858 struct ata_host *host = pci_get_drvdata(pdev);
859 struct ahci_host_priv *hpriv = host->private_data;
860
861 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
862 dev_err(&pdev->dev,
863 "BIOS update required for suspend/resume\n");
864 return -EIO;
865 }
866
867 ahci_pci_disable_interrupts(host);
f1d848f9 868 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 869}
870
f1d848f9 871static int ahci_pci_device_resume(struct device *dev)
c1332875 872{
f1d848f9 873 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 874 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 875 int rc;
876
cb85696d
JL		 877 /* Apple BIOS helpfully mangles the registers on resume */
878 if (is_mcp89_apple(pdev))
879 ahci_mcp89_apple_enable(pdev);
880
c1332875 881 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 882 rc = ahci_pci_reset_controller(host);
c1332875
TH		 883 if (rc)
884 return rc;
885
781d6550 886 ahci_pci_init_controller(host);
c1332875
TH		 887 }
888
cca3974e 889 ata_host_resume(host);
c1332875
TH		 890
891 return 0;
892}
438ac6d5 893#endif
c1332875 894
02e53293
MW		 895#endif /* CONFIG_PM */
896
4447d351 897static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 898{
1da177e4 899 int rc;
1da177e4 900
318893e1
AR		 901 /*
902 * If the device fixup already set the dma_mask to some non-standard
903 * value, don't extend it here. This happens on STA2X11, for example.
904 */
905 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
906 return 0;
907
1da177e4 908 if (using_dac &&
c54c719b
QL		 909 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
910 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 911 if (rc) {
c54c719b 912 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 913 if (rc) {
a44fec1f
JP		 914 dev_err(&pdev->dev,
915 "64-bit DMA enable failed\n");
1da177e4
LT		 916 return rc;
917 }
918 }
1da177e4 919 } else {
c54c719b 920 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 921 if (rc) {
a44fec1f 922 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 923 return rc;
924 }
c54c719b 925 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 926 if (rc) {
a44fec1f
JP		 927 dev_err(&pdev->dev,
928 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 929 return rc;
930 }
931 }
1da177e4
LT		 932 return 0;
933}
934
439fcaec
AV		 935static void ahci_pci_print_info(struct ata_host *host)
936{
937 struct pci_dev *pdev = to_pci_dev(host->dev);
938 u16 cc;
939 const char *scc_s;
940
941 pci_read_config_word(pdev, 0x0a, &cc);
942 if (cc == PCI_CLASS_STORAGE_IDE)
943 scc_s = "IDE";
944 else if (cc == PCI_CLASS_STORAGE_SATA)
945 scc_s = "SATA";
946 else if (cc == PCI_CLASS_STORAGE_RAID)
947 scc_s = "RAID";
948 else
949 scc_s = "unknown";
950
951 ahci_print_info(host, scc_s);
952}
953
edc93052
TH		 954/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
955 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
956 * support PMP and the 4726 either directly exports the device
957 * attached to the first downstream port or acts as a hardware storage
958 * controller and emulate a single ATA device (can be RAID 0/1 or some
959 * other configuration).
960 *
961 * When there's no device attached to the first downstream port of the
962 * 4726, "Config Disk" appears, which is a pseudo ATA device to
963 * configure the 4726. However, ATA emulation of the device is very
964 * lame. It doesn't send signature D2H Reg FIS after the initial
965 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
966 *
967 * The following function works around the problem by always using
968 * hardreset on the port and not depending on receiving signature FIS
969 * afterward. If signature FIS isn't received soon, ATA class is
970 * assumed without follow-up softreset.
971 */
972static void ahci_p5wdh_workaround(struct ata_host *host)
973{
1bd06867 974 static const struct dmi_system_id sysids[] = {
edc93052
TH		 975 {
976 .ident = "P5W DH Deluxe",
977 .matches = {
978 DMI_MATCH(DMI_SYS_VENDOR,
979 "ASUSTEK COMPUTER INC"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
981 },
982 },
983 { }
984 };
985 struct pci_dev *pdev = to_pci_dev(host->dev);
986
987 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
988 dmi_check_system(sysids)) {
989 struct ata_port *ap = host->ports[1];
990
a44fec1f
JP		 991 dev_info(&pdev->dev,
992 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 993
994 ap->ops = &ahci_p5wdh_ops;
995 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
996 }
997}
998
cb85696d
JL		 999/*
1000 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1001 * booting in BIOS compatibility mode. We restore the registers but not ID.
1002 */
1003static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1004{
1005 u32 val;
1006
1007 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1008
1009 pci_read_config_dword(pdev, 0xf8, &val);
1010 val |= 1 << 0x1b;
1011 /* the following changes the device ID, but appears not to affect function */
1012 /* val = (val & ~0xf0000000) | 0x80000000; */
1013 pci_write_config_dword(pdev, 0xf8, val);
1014
1015 pci_read_config_dword(pdev, 0x54c, &val);
1016 val |= 1 << 0xc;
1017 pci_write_config_dword(pdev, 0x54c, val);
1018
1019 pci_read_config_dword(pdev, 0x4a4, &val);
1020 val &= 0xff;
1021 val |= 0x01060100;
1022 pci_write_config_dword(pdev, 0x4a4, val);
1023
1024 pci_read_config_dword(pdev, 0x54c, &val);
1025 val &= ~(1 << 0xc);
1026 pci_write_config_dword(pdev, 0x54c, val);
1027
1028 pci_read_config_dword(pdev, 0xf8, &val);
1029 val &= ~(1 << 0x1b);
1030 pci_write_config_dword(pdev, 0xf8, val);
1031}
1032
1033static bool is_mcp89_apple(struct pci_dev *pdev)
1034{
1035 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1036 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1037 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1038 pdev->subsystem_device == 0xcb89;
1039}
1040
2fcad9d2
TH		 1041/* only some SB600 ahci controllers can do 64bit DMA */
1042static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1043{
1044 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1045 /*
1046 * The oldest version known to be broken is 0901 and
1047 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1048 * Enable 64bit DMA on 1501 and anything newer.
1049 *
03d783bf
TH		 1050 * Please read bko#9412 for more info.
1051 */
58a09b38
SH		 1052 {
1053 .ident = "ASUS M2A-VM",
1054 .matches = {
1055 DMI_MATCH(DMI_BOARD_VENDOR,
1056 "ASUSTeK Computer INC."),
1057 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1058 },
03d783bf 1059 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1060 },
e65cc194
MN		 1061 /*
1062 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1063 * support 64bit DMA.
1064 *
1065 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1066 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1067 * This spelling mistake was fixed in BIOS version 1.5, so
1068 * 1.5 and later have the Manufacturer as
1069 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1070 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1071 *
1072 * BIOS versions earlier than 1.9 had a Board Product Name
1073 * DMI field of "MS-7376". This was changed to be
1074 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1075 * match on DMI_BOARD_NAME of "MS-7376".
1076 */
1077 {
1078 .ident = "MSI K9A2 Platinum",
1079 .matches = {
1080 DMI_MATCH(DMI_BOARD_VENDOR,
1081 "MICRO-STAR INTER"),
1082 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1083 },
1084 },
ff0173c1
MN		 1085 /*
1086 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1087 * 64bit DMA.
1088 *
1089 * This board also had the typo mentioned above in the
1090 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1091 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1092 */
1093 {
1094 .ident = "MSI K9AGM2",
1095 .matches = {
1096 DMI_MATCH(DMI_BOARD_VENDOR,
1097 "MICRO-STAR INTER"),
1098 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1099 },
1100 },
3c4aa91f
MN		 1101 /*
1102 * All BIOS versions for the Asus M3A support 64bit DMA.
1103 * (all release versions from 0301 to 1206 were tested)
1104 */
1105 {
1106 .ident = "ASUS M3A",
1107 .matches = {
1108 DMI_MATCH(DMI_BOARD_VENDOR,
1109 "ASUSTeK Computer INC."),
1110 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1111 },
1112 },
58a09b38
SH		 1113 { }
1114 };
03d783bf 1115 const struct dmi_system_id *match;
2fcad9d2
TH		 1116 int year, month, date;
1117 char buf[9];
58a09b38 1118
03d783bf 1119 match = dmi_first_match(sysids);
58a09b38 1120 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1121 !match)
58a09b38
SH		 1122 return false;
1123
e65cc194
MN		 1124 if (!match->driver_data)
1125 goto enable_64bit;
1126
2fcad9d2
TH		 1127 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1128 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1129
e65cc194
MN		 1130 if (strcmp(buf, match->driver_data) >= 0)
1131 goto enable_64bit;
1132 else {
a44fec1f
JP		 1133 dev_warn(&pdev->dev,
1134 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1135 match->ident);
2fcad9d2
TH		 1136 return false;
1137 }
e65cc194
MN		 1138
1139enable_64bit:
a44fec1f 1140 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1141 return true;
58a09b38
SH		 1142}
1143
1fd68434
RW		 1144static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1145{
1146 static const struct dmi_system_id broken_systems[] = {
1147 {
1148 .ident = "HP Compaq nx6310",
1149 .matches = {
1150 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1151 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1152 },
1153 /* PCI slot number of the controller */
1154 .driver_data = (void *)0x1FUL,
1155 },
d2f9c061
MR		 1156 {
1157 .ident = "HP Compaq 6720s",
1158 .matches = {
1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1160 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1161 },
1162 /* PCI slot number of the controller */
1163 .driver_data = (void *)0x1FUL,
1164 },
1fd68434
RW		 1165
1166 { } /* terminate list */
1167 };
1168 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1169
1170 if (dmi) {
1171 unsigned long slot = (unsigned long)dmi->driver_data;
1172 /* apply the quirk only to on-board controllers */
1173 return slot == PCI_SLOT(pdev->devfn);
1174 }
1175
1176 return false;
1177}
1178
9b10ae86
TH		 1179static bool ahci_broken_suspend(struct pci_dev *pdev)
1180{
1181 static const struct dmi_system_id sysids[] = {
1182 /*
1183 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1184 * to the harddisk doesn't become online after
1185 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1186 *
1187 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1188 *
1189 * Use dates instead of versions to match as HP is
1190 * apparently recycling both product and version
1191 * strings.
1192 *
1193 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1194 */
1195 {
1196 .ident = "dv4",
1197 .matches = {
1198 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1199 DMI_MATCH(DMI_PRODUCT_NAME,
1200 "HP Pavilion dv4 Notebook PC"),
1201 },
9deb3431 1202 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1203 },
1204 {
1205 .ident = "dv5",
1206 .matches = {
1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1208 DMI_MATCH(DMI_PRODUCT_NAME,
1209 "HP Pavilion dv5 Notebook PC"),
1210 },
9deb3431 1211 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1212 },
1213 {
1214 .ident = "dv6",
1215 .matches = {
1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1217 DMI_MATCH(DMI_PRODUCT_NAME,
1218 "HP Pavilion dv6 Notebook PC"),
1219 },
9deb3431 1220 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1221 },
1222 {
1223 .ident = "HDX18",
1224 .matches = {
1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1226 DMI_MATCH(DMI_PRODUCT_NAME,
1227 "HP HDX18 Notebook PC"),
1228 },
9deb3431 1229 .driver_data = "20090430", /* F.23 */
9b10ae86 1230 },
cedc9bf9
TH		 1231 /*
1232 * Acer eMachines G725 has the same problem. BIOS
1233 * V1.03 is known to be broken. V3.04 is known to
25985edc 1234 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1235 * that we don't have much idea about. For now,
1236 * blacklist anything older than V3.04.
9deb3431
TH		 1237 *
1238 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1239 */
1240 {
1241 .ident = "G725",
1242 .matches = {
1243 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1244 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1245 },
9deb3431 1246 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1247 },
9b10ae86
TH		 1248 { } /* terminate list */
1249 };
1250 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1251 int year, month, date;
1252 char buf[9];
9b10ae86
TH		 1253
1254 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1255 return false;
1256
9deb3431
TH		 1257 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1258 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1259
9deb3431 1260 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1261}
1262
5594639a
TH		 1263static bool ahci_broken_online(struct pci_dev *pdev)
1264{
1265#define ENCODE_BUSDEVFN(bus, slot, func) \
1266 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1267 static const struct dmi_system_id sysids[] = {
1268 /*
1269 * There are several gigabyte boards which use
1270 * SIMG5723s configured as hardware RAID. Certain
1271 * 5723 firmware revisions shipped there keep the link
1272 * online but fail to answer properly to SRST or
1273 * IDENTIFY when no device is attached downstream
1274 * causing libata to retry quite a few times leading
1275 * to excessive detection delay.
1276 *
1277 * As these firmwares respond to the second reset try
1278 * with invalid device signature, considering unknown
1279 * sig as offline works around the problem acceptably.
1280 */
1281 {
1282 .ident = "EP45-DQ6",
1283 .matches = {
1284 DMI_MATCH(DMI_BOARD_VENDOR,
1285 "Gigabyte Technology Co., Ltd."),
1286 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1287 },
1288 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1289 },
1290 {
1291 .ident = "EP45-DS5",
1292 .matches = {
1293 DMI_MATCH(DMI_BOARD_VENDOR,
1294 "Gigabyte Technology Co., Ltd."),
1295 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1296 },
1297 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1298 },
1299 { } /* terminate list */
1300 };
1301#undef ENCODE_BUSDEVFN
1302 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1303 unsigned int val;
1304
1305 if (!dmi)
1306 return false;
1307
1308 val = (unsigned long)dmi->driver_data;
1309
1310 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1311}
1312
0cf4a7d6
JP		 1313static bool ahci_broken_devslp(struct pci_dev *pdev)
1314{
1315 /* device with broken DEVSLP but still showing SDS capability */
1316 static const struct pci_device_id ids[] = {
1317 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1318 {}
1319 };
1320
1321 return pci_match_id(ids, pdev);
1322}
1323
8e513217 1324#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1325static void ahci_gtf_filter_workaround(struct ata_host *host)
1326{
1327 static const struct dmi_system_id sysids[] = {
1328 /*
1329 * Aspire 3810T issues a bunch of SATA enable commands
1330 * via _GTF including an invalid one and one which is
1331 * rejected by the device. Among the successful ones
1332 * is FPDMA non-zero offset enable which when enabled
1333 * only on the drive side leads to NCQ command
1334 * failures. Filter it out.
1335 */
1336 {
1337 .ident = "Aspire 3810T",
1338 .matches = {
1339 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1340 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1341 },
1342 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1343 },
1344 { }
1345 };
1346 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1347 unsigned int filter;
1348 int i;
1349
1350 if (!dmi)
1351 return;
1352
1353 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1354 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1355 filter, dmi->ident);
f80ae7e4
TH		 1356
1357 for (i = 0; i < host->n_ports; i++) {
1358 struct ata_port *ap = host->ports[i];
1359 struct ata_link *link;
1360 struct ata_device *dev;
1361
1362 ata_for_each_link(link, ap, EDGE)
1363 ata_for_each_dev(dev, link, ALL)
1364 dev->gtf_filter |= filter;
1365 }
1366}
8e513217
MT		 1367#else
1368static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1369{}
1370#endif
f80ae7e4 1371
8bfd1743
SC		 1372/*
1373 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1374 * as DUMMY, or detected but eventually get a "link down" and never get up
1375 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1376 * port_map may hold a value of 0x00.
1377 *
1378 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1379 * and can significantly reduce the occurrence of the problem.
1380 *
1381 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1382 */
1383static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1384 struct pci_dev *pdev)
1385{
1386 static const struct dmi_system_id sysids[] = {
1387 {
1388 .ident = "Acer Switch Alpha 12",
1389 .matches = {
1390 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1391 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1392 },
1393 },
1394 { }
1395 };
1396
1397 if (dmi_check_system(sysids)) {
1398 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1399 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1400 hpriv->port_map = 0x7;
1401 hpriv->cap = 0xC734FF02;
1402 }
1403 }
1404}
1405
d243bed3
TC		 1406#ifdef CONFIG_ARM64
1407/*
1408 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1409 * Workaround is to make sure all pending IRQs are served before leaving
1410 * handler.
1411 */
1412static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1413{
1414 struct ata_host *host = dev_instance;
1415 struct ahci_host_priv *hpriv;
1416 unsigned int rc = 0;
1417 void __iomem *mmio;
1418 u32 irq_stat, irq_masked;
1419 unsigned int handled = 1;
1420
1421 VPRINTK("ENTER\n");
1422 hpriv = host->private_data;
1423 mmio = hpriv->mmio;
1424 irq_stat = readl(mmio + HOST_IRQ_STAT);
1425 if (!irq_stat)
1426 return IRQ_NONE;
1427
1428 do {
1429 irq_masked = irq_stat & hpriv->port_map;
1430 spin_lock(&host->lock);
1431 rc = ahci_handle_port_intr(host, irq_masked);
1432 if (!rc)
1433 handled = 0;
1434 writel(irq_stat, mmio + HOST_IRQ_STAT);
1435 irq_stat = readl(mmio + HOST_IRQ_STAT);
1436 spin_unlock(&host->lock);
1437 } while (irq_stat);
1438 VPRINTK("EXIT\n");
1439
1440 return IRQ_RETVAL(handled);
1441}
1442#endif
1443
aecec8b6
CH		 1444static void ahci_remap_check(struct pci_dev *pdev, int bar,
1445 struct ahci_host_priv *hpriv)
1446{
1447 int i, count = 0;
1448 u32 cap;
1449
1450 /*
1451 * Check if this device might have remapped nvme devices.
1452 */
1453 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1454 pci_resource_len(pdev, bar) < SZ_512K ||
1455 bar != AHCI_PCI_BAR_STANDARD ||
1456 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1457 return;
1458
1459 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1460 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1461 if ((cap & (1 << i)) == 0)
1462 continue;
1463 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1464 != PCI_CLASS_STORAGE_EXPRESS)
1465 continue;
1466
1467 /* We've found a remapped device */
1468 count++;
1469 }
1470
1471 if (!count)
1472 return;
1473
1474 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
f723fa4e
CH		 1475 dev_warn(&pdev->dev,
1476 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1477
1478 /*
1479 * Don't rely on the msi-x capability in the remap case,
1480 * share the legacy interrupt across ahci and remapped devices.
1481 */
1482 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1483}
1484
0b9e2988 1485static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1486{
0b9e2988 1487 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1488}
1489
a1c82311
RR		 1490static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1491 struct ahci_host_priv *hpriv)
5ca72c4f 1492{
0b9e2988 1493 int nvec;
5ca72c4f 1494
7b92b4f6 1495 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1496 return -ENODEV;
7b92b4f6 1497
7b92b4f6
AG		 1498 /*
1499 * If number of MSIs is less than number of ports then Sharing Last
1500 * Message mode could be enforced. In this case assume that advantage
1501 * of multipe MSIs is negated and use single MSI mode instead.
1502 */
17a51f12
CH		 1503 if (n_ports > 1) {
1504 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1505 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1506 if (nvec > 0) {
1507 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1508 hpriv->get_irq_vector = ahci_get_irq_vector;
1509 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1510 return nvec;
1511 }
5ca72c4f 1512
17a51f12
CH		 1513 /*
1514 * Fallback to single MSI mode if the controller
1515 * enforced MRSM mode.
1516 */
1517 printk(KERN_INFO
1518 "ahci: MRSM is on, fallback to single MSI\n");
1519 pci_free_irq_vectors(pdev);
1520 }
a478b097 1521 }
d684a90d 1522
0b9e2988
CH		 1523 /*
1524 * If the host is not capable of supporting per-port vectors, fall
1525 * back to single MSI before finally attempting single MSI-X.
1526 */
1527 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1528 if (nvec == 1)
ee2aad42 1529 return nvec;
0b9e2988 1530 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1531}
1532
24dc5f33 1533static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1534{
e297d99e
TH		 1535 unsigned int board_id = ent->driver_data;
1536 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1537 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1538 struct device *dev = &pdev->dev;
1da177e4 1539 struct ahci_host_priv *hpriv;
4447d351 1540 struct ata_host *host;
c3ebd6a9 1541 int n_ports, i, rc;
318893e1 1542 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1543
1544 VPRINTK("ENTER\n");
1545
b429dd59 1546 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1547
06296a1e 1548 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1549
5b66c829
AC		 1550 /* The AHCI driver can only drive the SATA ports, the PATA driver
1551 can drive them all so if both drivers are selected make sure
1552 AHCI stays out of the way */
1553 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1554 return -ENODEV;
1555
cb85696d
JL		 1556 /* Apple BIOS on MCP89 prevents us using AHCI */
1557 if (is_mcp89_apple(pdev))
1558 ahci_mcp89_apple_enable(pdev);
c6353b45 1559
7a02267e
MN		 1560 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1561 * At the moment, we can only use the AHCI mode. Let the users know
1562 * that for SAS drives they're out of luck.
1563 */
1564 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1565 dev_info(&pdev->dev,
1566 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1567
b7ae128d 1568 /* Some devices use non-standard BARs */
318893e1
AR		 1569 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1570 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1571 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1572 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b7ae128d
RR		 1573 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1574 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
318893e1 1575
4447d351 1576 /* acquire resources */
24dc5f33 1577 rc = pcim_enable_device(pdev);
1da177e4
LT		 1578 if (rc)
1579 return rc;
1580
c4f7792c
TH		 1581 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1582 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1583 u8 map;
1584
1585 /* ICH6s share the same PCI ID for both piix and ahci
1586 * modes. Enabling ahci mode while MAP indicates
1587 * combined mode is a bad idea. Yield to ata_piix.
1588 */
1589 pci_read_config_byte(pdev, ICH_MAP, &map);
1590 if (map & 0x3) {
a44fec1f
JP		 1591 dev_info(&pdev->dev,
1592 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1593 return -ENODEV;
1594 }
1595 }
1596
6fec8871
PB		 1597 /* AHCI controllers often implement SFF compatible interface.
1598 * Grab all PCI BARs just in case.
1599 */
1600 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1601 if (rc == -EBUSY)
1602 pcim_pin_device(pdev);
1603 if (rc)
1604 return rc;
1605
24dc5f33
TH		 1606 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1607 if (!hpriv)
1608 return -ENOMEM;
417a1a6d
TH		 1609 hpriv->flags |= (unsigned long)pi.private_data;
1610
e297d99e
TH		 1611 /* MCP65 revision A1 and A2 can't do MSI */
1612 if (board_id == board_ahci_mcp65 &&
1613 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1614 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1615
e427fe04
SH		 1616 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1617 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1618 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1619
2fcad9d2
TH		 1620 /* only some SB600s can do 64bit DMA */
1621 if (ahci_sb600_enable_64bit(pdev))
1622 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1623
318893e1 1624 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1625
aecec8b6
CH		 1626 /* detect remapped nvme devices */
1627 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1628
0cf4a7d6
JP		 1629 /* must set flag prior to save config in order to take effect */
1630 if (ahci_broken_devslp(pdev))
1631 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1632
d243bed3
TC		 1633#ifdef CONFIG_ARM64
1634 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1635 hpriv->irq_handler = ahci_thunderx_irq_handler;
1636#endif
1637
4447d351 1638 /* save initial config */
394d6e53 1639 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1640
4447d351 1641 /* prepare host */
453d3131
RH		 1642 if (hpriv->cap & HOST_CAP_NCQ) {
1643 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1644 /*
1645 * Auto-activate optimization is supposed to be
1646 * supported on all AHCI controllers indicating NCQ
1647 * capability, but it seems to be broken on some
1648 * chipsets including NVIDIAs.
1649 */
1650 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1651 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1652
1653 /*
1654 * All AHCI controllers should be forward-compatible
1655 * with the new auxiliary field. This code should be
1656 * conditionalized if any buggy AHCI controllers are
1657 * encountered.
1658 */
1659 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1660 }
1da177e4 1661
7d50b60b
TH		 1662 if (hpriv->cap & HOST_CAP_PMP)
1663 pi.flags |= ATA_FLAG_PMP;
1664
0cbb0e77 1665 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1666
1fd68434
RW		 1667 if (ahci_broken_system_poweroff(pdev)) {
1668 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1669 dev_info(&pdev->dev,
1670 "quirky BIOS, skipping spindown on poweroff\n");
1671 }
1672
9b10ae86
TH		 1673 if (ahci_broken_suspend(pdev)) {
1674 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1675 dev_warn(&pdev->dev,
1676 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1677 }
1678
5594639a
TH		 1679 if (ahci_broken_online(pdev)) {
1680 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1681 dev_info(&pdev->dev,
1682 "online status unreliable, applying workaround\n");
1683 }
1684
8bfd1743
SC		 1685
1686 /* Acer SA5-271 workaround modifies private_data */
1687 acer_sa5_271_workaround(hpriv, pdev);
1688
837f5f8f
TH		 1689 /* CAP.NP sometimes indicate the index of the last enabled
1690 * port, at other times, that of the last possible port, so
1691 * determining the maximum port number requires looking at
1692 * both CAP.NP and port_map.
1693 */
1694 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1695
1696 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1697 if (!host)
1698 return -ENOMEM;
4447d351 1699 host->private_data = hpriv;
0b9e2988
CH		 1700
1701 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1702 /* legacy intx interrupts */
1703 pci_intx(pdev, 1);
1704 }
0ce57f8a 1705 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1706
f3d7f23f 1707 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1708 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1709 else
d2782d96 1710 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1711
18f7ba4c
KCA		 1712 if (pi.flags & ATA_FLAG_EM)
1713 ahci_reset_em(host);
1714
4447d351 1715 for (i = 0; i < host->n_ports; i++) {
dab632e8 1716 struct ata_port *ap = host->ports[i];
4447d351 1717
318893e1
AR		 1718 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1719 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1720 0x100 + ap->port_no * 0x80, "port");
1721
18f7ba4c
KCA		 1722 /* set enclosure management message type */
1723 if (ap->flags & ATA_FLAG_EM)
008dbd61 1724 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1725
1726
dab632e8 1727 /* disabled/not-implemented port */
350756f6 1728 if (!(hpriv->port_map & (1 << i)))
dab632e8 1729 ap->ops = &ata_dummy_port_ops;
4447d351 1730 }
d447df14 1731
edc93052
TH		 1732 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1733 ahci_p5wdh_workaround(host);
1734
f80ae7e4
TH		 1735 /* apply gtf filter quirk */
1736 ahci_gtf_filter_workaround(host);
1737
4447d351
TH		 1738 /* initialize adapter */
1739 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1740 if (rc)
24dc5f33 1741 return rc;
1da177e4 1742
3303040d 1743 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1744 if (rc)
1745 return rc;
1da177e4 1746
781d6550 1747 ahci_pci_init_controller(host);
439fcaec 1748 ahci_pci_print_info(host);
1da177e4 1749
4447d351 1750 pci_set_master(pdev);
5ca72c4f 1751
02e53293
MW		 1752 rc = ahci_host_activate(host, &ahci_sht);
1753 if (rc)
1754 return rc;
1755
1756 pm_runtime_put_noidle(&pdev->dev);
1757 return 0;
1758}
1759
1760static void ahci_remove_one(struct pci_dev *pdev)
1761{
1762 pm_runtime_get_noresume(&pdev->dev);
1763 ata_pci_remove_one(pdev);
907f4678 1764}
1da177e4 1765
2fc75da0 1766module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1767
1768MODULE_AUTHOR("Jeff Garzik");
1769MODULE_DESCRIPTION("AHCI SATA low-level driver");
1770MODULE_LICENSE("GPL");
1771MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1772MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)