projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'dma-mapping-5.13' of git://git.infradead.org/users/hch/dma-mapping
[linux-block.git] / drivers / ata / ahci.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ahci.c - AHCI SATA support
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * AHCI hardware documentation:
1da177e4 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
1da177e4
LT		 22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
87507cfd 25#include <linux/dma-mapping.h>
a9524a76 26#include <linux/device.h>
edc93052 27#include <linux/dmi.h>
5a0e3ad6 28#include <linux/gfp.h>
ee2aad42 29#include <linux/msi.h>
1da177e4 30#include <scsi/scsi_host.h>
193515d5 31#include <scsi/scsi_cmnd.h>
1da177e4 32#include <linux/libata.h>
aecec8b6
CH		 33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 35#include "ahci.h"
1da177e4
LT		 36
37#define DRV_NAME "ahci"
7d50b60b 38#define DRV_VERSION "3.0"
1da177e4 39
1da177e4 40enum {
318893e1 41 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 42 AHCI_PCI_BAR_CAVIUM = 0,
e49bd683 43 AHCI_PCI_BAR_LOONGSON = 0,
7f9c9f8e 44 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 46 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 47};
48
49enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
ebb82e3c 53 board_ahci_mobile,
66a7cbc3 54 board_ahci_nomsi,
67809f85 55 board_ahci_noncq,
441577ef 56 board_ahci_nosntf,
5f173107 57 board_ahci_yes_fbs,
1da177e4 58
441577ef 59 /* board IDs for specific chipsets in alphabetical order */
7d523bdc 60 board_ahci_al,
dbfe8ef5 61 board_ahci_avn,
441577ef 62 board_ahci_mcp65,
83f2b963
TH		 63 board_ahci_mcp77,
64 board_ahci_mcp89,
441577ef
TH		 65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
c312ef17
DW		 70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
441577ef
TH		 76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 84static void ahci_remove_one(struct pci_dev *dev);
10a663a1 85static void ahci_shutdown_one(struct pci_dev *dev);
a1efdaba
TH		 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
dbfe8ef5
DW		 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
cb85696d
JL		 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
02e53293
MW		 94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
438ac6d5 100#endif
02e53293 101#endif /* CONFIG_PM */
ad616ffb 102
fad16e7a
TH		 103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
029cfd6b
TH		 107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
a1efdaba 109 .hardreset = ahci_vt8251_hardreset,
029cfd6b 110};
edc93052 111
029cfd6b
TH		 112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 115};
116
dbfe8ef5
DW		 117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
98ac62de 122static const struct ata_port_info ahci_port_info[] = {
441577ef 123 /* by features */
facb8fa6 124 [board_ahci] = {
1188c0d8 125 .flags = AHCI_FLAG_COMMON,
14bdef98 126 .pio_mask = ATA_PIO4,
469248ab 127 .udma_mask = ATA_UDMA6,
1da177e4
LT		 128 .port_ops = &ahci_ops,
129 },
facb8fa6 130 [board_ahci_ign_iferr] = {
441577ef 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 132 .flags = AHCI_FLAG_COMMON,
14bdef98 133 .pio_mask = ATA_PIO4,
469248ab 134 .udma_mask = ATA_UDMA6,
441577ef 135 .port_ops = &ahci_ops,
bf2af2a2 136 },
ebb82e3c
HG		 137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
66a7cbc3
TH		 144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
67809f85
LK		 151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
facb8fa6 158 [board_ahci_nosntf] = {
441577ef 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
41669553
TH		 163 .port_ops = &ahci_ops,
164 },
facb8fa6 165 [board_ahci_yes_fbs] = {
5f173107
TH		 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
441577ef 172 /* by chipsets */
7d523bdc
HH		 173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
dbfe8ef5
DW		 180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
facb8fa6 186 [board_ahci_mcp65] = {
83f2b963
TH		 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
ae01b249 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
facb8fa6 194 [board_ahci_mcp77] = {
83f2b963
TH		 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
facb8fa6 201 [board_ahci_mcp89] = {
83f2b963 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 203 .flags = AHCI_FLAG_COMMON,
14bdef98 204 .pio_mask = ATA_PIO4,
469248ab 205 .udma_mask = ATA_UDMA6,
441577ef 206 .port_ops = &ahci_ops,
55a61604 207 },
facb8fa6 208 [board_ahci_mv] = {
417a1a6d 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 212 .pio_mask = ATA_PIO4,
cd70c266
JG		 213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
facb8fa6 216 [board_ahci_sb600] = {
441577ef
TH		 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 220 .flags = AHCI_FLAG_COMMON,
14bdef98 221 .pio_mask = ATA_PIO4,
e39fc8c9 222 .udma_mask = ATA_UDMA6,
345347c5 223 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 224 },
facb8fa6 225 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
345347c5 230 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 231 },
facb8fa6 232 [board_ahci_vt8251] = {
441577ef 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
441577ef 237 .port_ops = &ahci_vt8251_ops,
1b677afd 238 },
c312ef17
DW		 239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
1da177e4
LT		 245};
246
3b7d697d 247static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 248 /* Intel */
5e125d13 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
54bb3a94
JG		 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
ebb82e3c
HG		 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
7a234aff 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
ebb82e3c 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
d4155e6f
JG		 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ebb82e3c 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
adcb5308 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ebb82e3c 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
c1f57d9b 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
c312ef17
DW		 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
5623cab8 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ebb82e3c 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
5623cab8 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ebb82e3c 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
5623cab8
SH		 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ebb82e3c 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
181e3cea
SH		 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ebb82e3c 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
2cab7a4c 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ebb82e3c 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
ea4ace66 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ebb82e3c 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ebb82e3c 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ebb82e3c
HG		 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
4544e403 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
29e674dd
SH		 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
8e85f605
MW		 363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
151743fd
JR		 367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
ebb82e3c
HG		 376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
1b071a09 380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ebb82e3c 381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
1b071a09 382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ebb82e3c 383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ebb82e3c 385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ebb82e3c
HG		 387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
c5967b79 391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ebb82e3c 392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
690000b9 393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ebb82e3c 395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
690000b9 396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
f919dde0 409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
32d25454 410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
58c42b0b 411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
ebb82e3c
HG		 412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
ba445791 416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
1f2ef049 417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
7667e63c 418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
fe7fa31a 419
e34bb370
TH		 420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 426 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 427
428 /* ATI */
c65ec1c2 429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 436
7d523bdc
HH		 437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
e2dd90b1 442 /* AMD */
5deab536 443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 445 /* AMD is using RAID class only for ahci controllers */
446 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
447 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
448
fe7fa31a 449 /* VIA */
54bb3a94 450 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 451 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 452
453 /* NVIDIA */
e297d99e
TH		 454 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 462 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 538
95916edd 539 /* SiS */
20e2de4a
TH		 540 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
541 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
542 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 543
318893e1
AR		 544 /* ST Microelectronics */
545 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
546
cd70c266
JG		 547 /* Marvell */
548 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 549 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 551 .class = PCI_CLASS_STORAGE_SATA_AHCI,
552 .class_mask = 0xffffff,
5f173107 553 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 555 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 556 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
557 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
558 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 562 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 564 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 566 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
568 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
570 .driver_data = board_ahci_yes_fbs },
69fd3157 571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 572 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
574 .driver_data = board_ahci_yes_fbs },
28b2182d
HG		 575 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
d2518365 578 .driver_data = board_ahci_yes_fbs },
cd70c266 579
c77a036b
MN		 580 /* Promise */
581 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 582 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 583
c9703765 584 /* Asmedia */
7b4f6eca
AC		 585 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
586 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
587 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
588 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 589 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
590 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 591
67809f85 592 /*
66a7cbc3
TH		 593 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
594 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 595 */
66a7cbc3 596 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 597 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 598
7f9c9f8e
HD		 599 /* Enmotus */
600 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
601
e49bd683
TY		 602 /* Loongson */
603 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
604
415ae2b5
JG		 605 /* Generic, PCI class code for AHCI */
606 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 607 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 608
1da177e4
LT		 609 { } /* terminate list */
610};
611
f1d848f9
MW		 612static const struct dev_pm_ops ahci_pci_pm_ops = {
613 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 614 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
615 ahci_pci_device_runtime_resume, NULL)
f1d848f9 616};
1da177e4
LT		 617
618static struct pci_driver ahci_pci_driver = {
619 .name = DRV_NAME,
620 .id_table = ahci_pci_tbl,
621 .probe = ahci_init_one,
02e53293 622 .remove = ahci_remove_one,
10a663a1 623 .shutdown = ahci_shutdown_one,
f1d848f9
MW		 624 .driver = {
625 .pm = &ahci_pci_pm_ops,
626 },
365cfa1e 627};
1da177e4 628
5219d653 629#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 630static int marvell_enable;
631#else
632static int marvell_enable = 1;
633#endif
634module_param(marvell_enable, int, 0644);
635MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 636
b1a9585c 637static int mobile_lpm_policy = -1;
ebb82e3c
HG		 638module_param(mobile_lpm_policy, int, 0644);
639MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
1da177e4 640
365cfa1e
AV		 641static void ahci_pci_save_initial_config(struct pci_dev *pdev,
642 struct ahci_host_priv *hpriv)
643{
365cfa1e
AV		 644 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
645 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 646 hpriv->force_port_map = 1;
1da177e4
LT		 647 }
648
365cfa1e
AV		 649 /*
650 * Temporary Marvell 6145 hack: PATA port presence
651 * is asserted through the standard AHCI port
652 * presence register, as bit 4 (counting from 0)
d28f87aa 653 */
365cfa1e
AV		 654 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
655 if (pdev->device == 0x6121)
9a23c1d6 656 hpriv->mask_port_map = 0x3;
365cfa1e 657 else
9a23c1d6 658 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 659 dev_info(&pdev->dev,
660 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
661 }
1da177e4 662
725c7b57 663 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 664}
665
365cfa1e 666static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 667{
365cfa1e
AV		 668 struct ahci_host_priv *hpriv = host->private_data;
669 struct pci_dev *pdev = to_pci_dev(host->dev);
670 void __iomem *port_mmio;
78cd52d0 671 u32 tmp;
365cfa1e 672 int mv;
78cd52d0 673
365cfa1e
AV		 674 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
675 if (pdev->device == 0x6121)
676 mv = 2;
677 else
678 mv = 4;
679 port_mmio = __ahci_port_base(host, mv);
78cd52d0 680
365cfa1e 681 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 682
365cfa1e
AV		 683 /* clear port IRQ */
684 tmp = readl(port_mmio + PORT_IRQ_STAT);
685 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
686 if (tmp)
687 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 688 }
689
365cfa1e 690 ahci_init_controller(host);
edc93052
TH		 691}
692
365cfa1e
AV		 693static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
694 unsigned long deadline)
d6ef3153 695{
365cfa1e 696 struct ata_port *ap = link->ap;
039ece38 697 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 698 bool online;
d6ef3153
SH		 699 int rc;
700
365cfa1e 701 DPRINTK("ENTER\n");
d6ef3153 702
fa89f53b 703 hpriv->stop_engine(ap);
d6ef3153 704
365cfa1e
AV		 705 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
706 deadline, &online, NULL);
d6ef3153 707
039ece38 708 hpriv->start_engine(ap);
d6ef3153 709
365cfa1e 710 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 711
365cfa1e
AV		 712 /* vt8251 doesn't clear BSY on signature FIS reception,
713 * request follow-up softreset.
714 */
715 return online ? -EAGAIN : rc;
7d50b60b
TH		 716}
717
365cfa1e
AV		 718static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
719 unsigned long deadline)
7d50b60b 720{
365cfa1e 721 struct ata_port *ap = link->ap;
1c954a4d 722 struct ahci_port_priv *pp = ap->private_data;
039ece38 723 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 724 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
725 struct ata_taskfile tf;
726 bool online;
727 int rc;
7d50b60b 728
fa89f53b 729 hpriv->stop_engine(ap);
028a2596 730
365cfa1e
AV		 731 /* clear D2H reception area to properly wait for D2H FIS */
732 ata_tf_init(link->device, &tf);
9bbb1b0e 733 tf.command = ATA_BUSY;
365cfa1e 734 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 735
365cfa1e
AV		 736 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
737 deadline, &online, NULL);
028a2596 738
039ece38 739 hpriv->start_engine(ap);
c1332875 740
365cfa1e
AV		 741 /* The pseudo configuration device on SIMG4726 attached to
742 * ASUS P5W-DH Deluxe doesn't send signature FIS after
743 * hardreset if no device is attached to the first downstream
744 * port && the pseudo device locks up on SRST w/ PMP==0. To
745 * work around this, wait for !BSY only briefly. If BSY isn't
746 * cleared, perform CLO and proceed to IDENTIFY (achieved by
747 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
748 *
749 * Wait for two seconds. Devices attached to downstream port
750 * which can't process the following IDENTIFY after this will
751 * have to be reset again. For most cases, this should
752 * suffice while making probing snappish enough.
753 */
754 if (online) {
755 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
756 ahci_check_ready);
757 if (rc)
758 ahci_kick_engine(ap);
c1332875 759 }
c1332875
TH		 760 return rc;
761}
762
dbfe8ef5
DW		 763/*
764 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
765 *
766 * It has been observed with some SSDs that the timing of events in the
767 * link synchronization phase can leave the port in a state that can not
768 * be recovered by a SATA-hard-reset alone. The failing signature is
769 * SStatus.DET stuck at 1 ("Device presence detected but Phy
770 * communication not established"). It was found that unloading and
771 * reloading the driver when this problem occurs allows the drive
772 * connection to be recovered (DET advanced to 0x3). The critical
773 * component of reloading the driver is that the port state machines are
774 * reset by bouncing "port enable" in the AHCI PCS configuration
775 * register. So, reproduce that effect by bouncing a port whenever we
776 * see DET==1 after a reset.
777 */
778static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
779 unsigned long deadline)
780{
781 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
782 struct ata_port *ap = link->ap;
783 struct ahci_port_priv *pp = ap->private_data;
784 struct ahci_host_priv *hpriv = ap->host->private_data;
785 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
786 unsigned long tmo = deadline - jiffies;
787 struct ata_taskfile tf;
788 bool online;
789 int rc, i;
790
791 DPRINTK("ENTER\n");
792
fa89f53b 793 hpriv->stop_engine(ap);
dbfe8ef5
DW		 794
795 for (i = 0; i < 2; i++) {
796 u16 val;
797 u32 sstatus;
798 int port = ap->port_no;
799 struct ata_host *host = ap->host;
800 struct pci_dev *pdev = to_pci_dev(host->dev);
801
802 /* clear D2H reception area to properly wait for D2H FIS */
803 ata_tf_init(link->device, &tf);
804 tf.command = ATA_BUSY;
805 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
806
807 rc = sata_link_hardreset(link, timing, deadline, &online,
808 ahci_check_ready);
809
810 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
811 (sstatus & 0xf) != 1)
812 break;
813
e276c9bd 814 ata_link_info(link, "avn bounce port%d\n", port);
dbfe8ef5
DW		 815
816 pci_read_config_word(pdev, 0x92, &val);
817 val &= ~(1 << port);
818 pci_write_config_word(pdev, 0x92, val);
819 ata_msleep(ap, 1000);
820 val |= 1 << port;
821 pci_write_config_word(pdev, 0x92, val);
822 deadline += tmo;
823 }
824
825 hpriv->start_engine(ap);
826
827 if (online)
828 *class = ahci_dev_classify(ap);
829
830 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
831 return rc;
832}
833
834
02e53293
MW		 835#ifdef CONFIG_PM
836static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 837{
9b10ae86 838 struct ahci_host_priv *hpriv = host->private_data;
d8993349 839 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 840 u32 ctl;
841
f1d848f9
MW		 842 /* AHCI spec rev1.1 section 8.3.3:
843 * Software must disable interrupts prior to requesting a
844 * transition of the HBA to D3 state.
845 */
846 ctl = readl(mmio + HOST_CTL);
847 ctl &= ~HOST_IRQ_EN;
848 writel(ctl, mmio + HOST_CTL);
849 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 850}
851
852static int ahci_pci_device_runtime_suspend(struct device *dev)
853{
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 856
02e53293
MW		 857 ahci_pci_disable_interrupts(host);
858 return 0;
859}
860
861static int ahci_pci_device_runtime_resume(struct device *dev)
862{
863 struct pci_dev *pdev = to_pci_dev(dev);
864 struct ata_host *host = pci_get_drvdata(pdev);
865 int rc;
866
c312ef17 867 rc = ahci_reset_controller(host);
02e53293
MW		 868 if (rc)
869 return rc;
870 ahci_pci_init_controller(host);
871 return 0;
872}
873
874#ifdef CONFIG_PM_SLEEP
875static int ahci_pci_device_suspend(struct device *dev)
876{
877 struct pci_dev *pdev = to_pci_dev(dev);
878 struct ata_host *host = pci_get_drvdata(pdev);
879 struct ahci_host_priv *hpriv = host->private_data;
880
881 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
882 dev_err(&pdev->dev,
883 "BIOS update required for suspend/resume\n");
884 return -EIO;
885 }
886
887 ahci_pci_disable_interrupts(host);
f1d848f9 888 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 889}
890
f1d848f9 891static int ahci_pci_device_resume(struct device *dev)
c1332875 892{
f1d848f9 893 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 894 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 895 int rc;
896
cb85696d
JL		 897 /* Apple BIOS helpfully mangles the registers on resume */
898 if (is_mcp89_apple(pdev))
899 ahci_mcp89_apple_enable(pdev);
900
c1332875 901 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
c312ef17 902 rc = ahci_reset_controller(host);
c1332875
TH		 903 if (rc)
904 return rc;
905
781d6550 906 ahci_pci_init_controller(host);
c1332875
TH		 907 }
908
cca3974e 909 ata_host_resume(host);
c1332875
TH		 910
911 return 0;
912}
438ac6d5 913#endif
c1332875 914
02e53293
MW		 915#endif /* CONFIG_PM */
916
4447d351 917static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 918{
b1716871 919 const int dma_bits = using_dac ? 64 : 32;
1da177e4 920 int rc;
1da177e4 921
318893e1
AR		 922 /*
923 * If the device fixup already set the dma_mask to some non-standard
924 * value, don't extend it here. This happens on STA2X11, for example.
b1716871
CH		 925 *
926 * XXX: manipulating the DMA mask from platform code is completely
a7ba70f1 927 * bogus, platform code should use dev->bus_dma_limit instead..
318893e1
AR		 928 */
929 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
930 return 0;
931
b1716871
CH		 932 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
933 if (rc)
934 dev_err(&pdev->dev, "DMA enable failed\n");
935 return rc;
1da177e4
LT		 936}
937
439fcaec
AV		 938static void ahci_pci_print_info(struct ata_host *host)
939{
940 struct pci_dev *pdev = to_pci_dev(host->dev);
941 u16 cc;
942 const char *scc_s;
943
944 pci_read_config_word(pdev, 0x0a, &cc);
945 if (cc == PCI_CLASS_STORAGE_IDE)
946 scc_s = "IDE";
947 else if (cc == PCI_CLASS_STORAGE_SATA)
948 scc_s = "SATA";
949 else if (cc == PCI_CLASS_STORAGE_RAID)
950 scc_s = "RAID";
951 else
952 scc_s = "unknown";
953
954 ahci_print_info(host, scc_s);
955}
956
edc93052
TH		 957/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
958 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
959 * support PMP and the 4726 either directly exports the device
960 * attached to the first downstream port or acts as a hardware storage
961 * controller and emulate a single ATA device (can be RAID 0/1 or some
962 * other configuration).
963 *
964 * When there's no device attached to the first downstream port of the
965 * 4726, "Config Disk" appears, which is a pseudo ATA device to
966 * configure the 4726. However, ATA emulation of the device is very
967 * lame. It doesn't send signature D2H Reg FIS after the initial
968 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
969 *
970 * The following function works around the problem by always using
971 * hardreset on the port and not depending on receiving signature FIS
972 * afterward. If signature FIS isn't received soon, ATA class is
973 * assumed without follow-up softreset.
974 */
975static void ahci_p5wdh_workaround(struct ata_host *host)
976{
1bd06867 977 static const struct dmi_system_id sysids[] = {
edc93052
TH		 978 {
979 .ident = "P5W DH Deluxe",
980 .matches = {
981 DMI_MATCH(DMI_SYS_VENDOR,
982 "ASUSTEK COMPUTER INC"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
984 },
985 },
986 { }
987 };
988 struct pci_dev *pdev = to_pci_dev(host->dev);
989
990 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
991 dmi_check_system(sysids)) {
992 struct ata_port *ap = host->ports[1];
993
a44fec1f
JP		 994 dev_info(&pdev->dev,
995 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 996
997 ap->ops = &ahci_p5wdh_ops;
998 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
999 }
1000}
1001
cb85696d
JL		 1002/*
1003 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1004 * booting in BIOS compatibility mode. We restore the registers but not ID.
1005 */
1006static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1007{
1008 u32 val;
1009
1010 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1011
1012 pci_read_config_dword(pdev, 0xf8, &val);
1013 val |= 1 << 0x1b;
1014 /* the following changes the device ID, but appears not to affect function */
1015 /* val = (val & ~0xf0000000) | 0x80000000; */
1016 pci_write_config_dword(pdev, 0xf8, val);
1017
1018 pci_read_config_dword(pdev, 0x54c, &val);
1019 val |= 1 << 0xc;
1020 pci_write_config_dword(pdev, 0x54c, val);
1021
1022 pci_read_config_dword(pdev, 0x4a4, &val);
1023 val &= 0xff;
1024 val |= 0x01060100;
1025 pci_write_config_dword(pdev, 0x4a4, val);
1026
1027 pci_read_config_dword(pdev, 0x54c, &val);
1028 val &= ~(1 << 0xc);
1029 pci_write_config_dword(pdev, 0x54c, val);
1030
1031 pci_read_config_dword(pdev, 0xf8, &val);
1032 val &= ~(1 << 0x1b);
1033 pci_write_config_dword(pdev, 0xf8, val);
1034}
1035
1036static bool is_mcp89_apple(struct pci_dev *pdev)
1037{
1038 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1039 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1040 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1041 pdev->subsystem_device == 0xcb89;
1042}
1043
2fcad9d2
TH		 1044/* only some SB600 ahci controllers can do 64bit DMA */
1045static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1046{
1047 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1048 /*
1049 * The oldest version known to be broken is 0901 and
1050 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1051 * Enable 64bit DMA on 1501 and anything newer.
1052 *
03d783bf
TH		 1053 * Please read bko#9412 for more info.
1054 */
58a09b38
SH		 1055 {
1056 .ident = "ASUS M2A-VM",
1057 .matches = {
1058 DMI_MATCH(DMI_BOARD_VENDOR,
1059 "ASUSTeK Computer INC."),
1060 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1061 },
03d783bf 1062 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1063 },
e65cc194
MN		 1064 /*
1065 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1066 * support 64bit DMA.
1067 *
1068 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1069 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1070 * This spelling mistake was fixed in BIOS version 1.5, so
1071 * 1.5 and later have the Manufacturer as
1072 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1073 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1074 *
1075 * BIOS versions earlier than 1.9 had a Board Product Name
1076 * DMI field of "MS-7376". This was changed to be
1077 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1078 * match on DMI_BOARD_NAME of "MS-7376".
1079 */
1080 {
1081 .ident = "MSI K9A2 Platinum",
1082 .matches = {
1083 DMI_MATCH(DMI_BOARD_VENDOR,
1084 "MICRO-STAR INTER"),
1085 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1086 },
1087 },
ff0173c1
MN		 1088 /*
1089 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1090 * 64bit DMA.
1091 *
1092 * This board also had the typo mentioned above in the
1093 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1094 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1095 */
1096 {
1097 .ident = "MSI K9AGM2",
1098 .matches = {
1099 DMI_MATCH(DMI_BOARD_VENDOR,
1100 "MICRO-STAR INTER"),
1101 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1102 },
1103 },
3c4aa91f
MN		 1104 /*
1105 * All BIOS versions for the Asus M3A support 64bit DMA.
1106 * (all release versions from 0301 to 1206 were tested)
1107 */
1108 {
1109 .ident = "ASUS M3A",
1110 .matches = {
1111 DMI_MATCH(DMI_BOARD_VENDOR,
1112 "ASUSTeK Computer INC."),
1113 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1114 },
1115 },
58a09b38
SH		 1116 { }
1117 };
03d783bf 1118 const struct dmi_system_id *match;
2fcad9d2
TH		 1119 int year, month, date;
1120 char buf[9];
58a09b38 1121
03d783bf 1122 match = dmi_first_match(sysids);
58a09b38 1123 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1124 !match)
58a09b38
SH		 1125 return false;
1126
e65cc194
MN		 1127 if (!match->driver_data)
1128 goto enable_64bit;
1129
2fcad9d2
TH		 1130 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1131 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1132
e65cc194
MN		 1133 if (strcmp(buf, match->driver_data) >= 0)
1134 goto enable_64bit;
1135 else {
a44fec1f
JP		 1136 dev_warn(&pdev->dev,
1137 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1138 match->ident);
2fcad9d2
TH		 1139 return false;
1140 }
e65cc194
MN		 1141
1142enable_64bit:
a44fec1f 1143 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1144 return true;
58a09b38
SH		 1145}
1146
1fd68434
RW		 1147static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1148{
1149 static const struct dmi_system_id broken_systems[] = {
1150 {
1151 .ident = "HP Compaq nx6310",
1152 .matches = {
1153 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1154 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1155 },
1156 /* PCI slot number of the controller */
1157 .driver_data = (void *)0x1FUL,
1158 },
d2f9c061
MR		 1159 {
1160 .ident = "HP Compaq 6720s",
1161 .matches = {
1162 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1163 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1164 },
1165 /* PCI slot number of the controller */
1166 .driver_data = (void *)0x1FUL,
1167 },
1fd68434
RW		 1168
1169 { } /* terminate list */
1170 };
1171 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1172
1173 if (dmi) {
1174 unsigned long slot = (unsigned long)dmi->driver_data;
1175 /* apply the quirk only to on-board controllers */
1176 return slot == PCI_SLOT(pdev->devfn);
1177 }
1178
1179 return false;
1180}
1181
9b10ae86
TH		 1182static bool ahci_broken_suspend(struct pci_dev *pdev)
1183{
1184 static const struct dmi_system_id sysids[] = {
1185 /*
1186 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1187 * to the harddisk doesn't become online after
1188 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1189 *
1190 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1191 *
1192 * Use dates instead of versions to match as HP is
1193 * apparently recycling both product and version
1194 * strings.
1195 *
1196 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1197 */
1198 {
1199 .ident = "dv4",
1200 .matches = {
1201 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1202 DMI_MATCH(DMI_PRODUCT_NAME,
1203 "HP Pavilion dv4 Notebook PC"),
1204 },
9deb3431 1205 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1206 },
1207 {
1208 .ident = "dv5",
1209 .matches = {
1210 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1211 DMI_MATCH(DMI_PRODUCT_NAME,
1212 "HP Pavilion dv5 Notebook PC"),
1213 },
9deb3431 1214 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1215 },
1216 {
1217 .ident = "dv6",
1218 .matches = {
1219 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1220 DMI_MATCH(DMI_PRODUCT_NAME,
1221 "HP Pavilion dv6 Notebook PC"),
1222 },
9deb3431 1223 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1224 },
1225 {
1226 .ident = "HDX18",
1227 .matches = {
1228 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1229 DMI_MATCH(DMI_PRODUCT_NAME,
1230 "HP HDX18 Notebook PC"),
1231 },
9deb3431 1232 .driver_data = "20090430", /* F.23 */
9b10ae86 1233 },
cedc9bf9
TH		 1234 /*
1235 * Acer eMachines G725 has the same problem. BIOS
1236 * V1.03 is known to be broken. V3.04 is known to
25985edc 1237 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1238 * that we don't have much idea about. For now,
1239 * blacklist anything older than V3.04.
9deb3431
TH		 1240 *
1241 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1242 */
1243 {
1244 .ident = "G725",
1245 .matches = {
1246 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1247 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1248 },
9deb3431 1249 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1250 },
9b10ae86
TH		 1251 { } /* terminate list */
1252 };
1253 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1254 int year, month, date;
1255 char buf[9];
9b10ae86
TH		 1256
1257 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1258 return false;
1259
9deb3431
TH		 1260 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1261 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1262
9deb3431 1263 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1264}
1265
240630e6
HG		 1266static bool ahci_broken_lpm(struct pci_dev *pdev)
1267{
1268 static const struct dmi_system_id sysids[] = {
1269 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1270 {
1271 .matches = {
1272 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1273 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1274 },
1275 .driver_data = "20180406", /* 1.31 */
1276 },
1277 {
1278 .matches = {
1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1281 },
1282 .driver_data = "20180420", /* 1.28 */
1283 },
1284 {
1285 .matches = {
1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1288 },
1289 .driver_data = "20180315", /* 1.33 */
1290 },
1291 {
1292 .matches = {
1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1295 },
1296 /*
1297 * Note date based on release notes, 2.35 has been
1298 * reported to be good, but I've been unable to get
1299 * a hold of the reporter to get the DMI BIOS date.
1300 * TODO: fix this.
1301 */
1302 .driver_data = "20180310", /* 2.35 */
1303 },
1304 { } /* terminate list */
1305 };
1306 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1307 int year, month, date;
1308 char buf[9];
1309
1310 if (!dmi)
1311 return false;
1312
1313 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1314 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1315
1316 return strcmp(buf, dmi->driver_data) < 0;
1317}
1318
5594639a
TH		 1319static bool ahci_broken_online(struct pci_dev *pdev)
1320{
1321#define ENCODE_BUSDEVFN(bus, slot, func) \
1322 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1323 static const struct dmi_system_id sysids[] = {
1324 /*
1325 * There are several gigabyte boards which use
1326 * SIMG5723s configured as hardware RAID. Certain
1327 * 5723 firmware revisions shipped there keep the link
1328 * online but fail to answer properly to SRST or
1329 * IDENTIFY when no device is attached downstream
1330 * causing libata to retry quite a few times leading
1331 * to excessive detection delay.
1332 *
1333 * As these firmwares respond to the second reset try
1334 * with invalid device signature, considering unknown
1335 * sig as offline works around the problem acceptably.
1336 */
1337 {
1338 .ident = "EP45-DQ6",
1339 .matches = {
1340 DMI_MATCH(DMI_BOARD_VENDOR,
1341 "Gigabyte Technology Co., Ltd."),
1342 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1343 },
1344 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1345 },
1346 {
1347 .ident = "EP45-DS5",
1348 .matches = {
1349 DMI_MATCH(DMI_BOARD_VENDOR,
1350 "Gigabyte Technology Co., Ltd."),
1351 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1352 },
1353 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1354 },
1355 { } /* terminate list */
1356 };
1357#undef ENCODE_BUSDEVFN
1358 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1359 unsigned int val;
1360
1361 if (!dmi)
1362 return false;
1363
1364 val = (unsigned long)dmi->driver_data;
1365
1366 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1367}
1368
0cf4a7d6
JP		 1369static bool ahci_broken_devslp(struct pci_dev *pdev)
1370{
1371 /* device with broken DEVSLP but still showing SDS capability */
1372 static const struct pci_device_id ids[] = {
1373 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1374 {}
1375 };
1376
1377 return pci_match_id(ids, pdev);
1378}
1379
8e513217 1380#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1381static void ahci_gtf_filter_workaround(struct ata_host *host)
1382{
1383 static const struct dmi_system_id sysids[] = {
1384 /*
1385 * Aspire 3810T issues a bunch of SATA enable commands
1386 * via _GTF including an invalid one and one which is
1387 * rejected by the device. Among the successful ones
1388 * is FPDMA non-zero offset enable which when enabled
1389 * only on the drive side leads to NCQ command
1390 * failures. Filter it out.
1391 */
1392 {
1393 .ident = "Aspire 3810T",
1394 .matches = {
1395 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1396 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1397 },
1398 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1399 },
1400 { }
1401 };
1402 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1403 unsigned int filter;
1404 int i;
1405
1406 if (!dmi)
1407 return;
1408
1409 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1410 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1411 filter, dmi->ident);
f80ae7e4
TH		 1412
1413 for (i = 0; i < host->n_ports; i++) {
1414 struct ata_port *ap = host->ports[i];
1415 struct ata_link *link;
1416 struct ata_device *dev;
1417
1418 ata_for_each_link(link, ap, EDGE)
1419 ata_for_each_dev(dev, link, ALL)
1420 dev->gtf_filter |= filter;
1421 }
1422}
8e513217
MT		 1423#else
1424static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1425{}
1426#endif
f80ae7e4 1427
8bfd1743
SC		 1428/*
1429 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1430 * as DUMMY, or detected but eventually get a "link down" and never get up
1431 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1432 * port_map may hold a value of 0x00.
1433 *
1434 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1435 * and can significantly reduce the occurrence of the problem.
1436 *
1437 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1438 */
1439static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1440 struct pci_dev *pdev)
1441{
1442 static const struct dmi_system_id sysids[] = {
1443 {
1444 .ident = "Acer Switch Alpha 12",
1445 .matches = {
1446 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1447 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1448 },
1449 },
1450 { }
1451 };
1452
1453 if (dmi_check_system(sysids)) {
1454 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1455 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1456 hpriv->port_map = 0x7;
1457 hpriv->cap = 0xC734FF02;
1458 }
1459 }
1460}
1461
d243bed3
TC		 1462#ifdef CONFIG_ARM64
1463/*
1464 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1465 * Workaround is to make sure all pending IRQs are served before leaving
1466 * handler.
1467 */
1468static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1469{
1470 struct ata_host *host = dev_instance;
1471 struct ahci_host_priv *hpriv;
1472 unsigned int rc = 0;
1473 void __iomem *mmio;
1474 u32 irq_stat, irq_masked;
1475 unsigned int handled = 1;
1476
1477 VPRINTK("ENTER\n");
1478 hpriv = host->private_data;
1479 mmio = hpriv->mmio;
1480 irq_stat = readl(mmio + HOST_IRQ_STAT);
1481 if (!irq_stat)
1482 return IRQ_NONE;
1483
1484 do {
1485 irq_masked = irq_stat & hpriv->port_map;
1486 spin_lock(&host->lock);
1487 rc = ahci_handle_port_intr(host, irq_masked);
1488 if (!rc)
1489 handled = 0;
1490 writel(irq_stat, mmio + HOST_IRQ_STAT);
1491 irq_stat = readl(mmio + HOST_IRQ_STAT);
1492 spin_unlock(&host->lock);
1493 } while (irq_stat);
1494 VPRINTK("EXIT\n");
1495
1496 return IRQ_RETVAL(handled);
1497}
1498#endif
1499
aecec8b6
CH		 1500static void ahci_remap_check(struct pci_dev *pdev, int bar,
1501 struct ahci_host_priv *hpriv)
1502{
894fba7f 1503 int i;
aecec8b6
CH		 1504 u32 cap;
1505
1506 /*
1507 * Check if this device might have remapped nvme devices.
1508 */
1509 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1510 pci_resource_len(pdev, bar) < SZ_512K ||
1511 bar != AHCI_PCI_BAR_STANDARD ||
1512 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1513 return;
1514
1515 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1516 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1517 if ((cap & (1 << i)) == 0)
1518 continue;
1519 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1520 != PCI_CLASS_STORAGE_EXPRESS)
1521 continue;
1522
1523 /* We've found a remapped device */
894fba7f 1524 hpriv->remapped_nvme++;
aecec8b6
CH		 1525 }
1526
894fba7f 1527 if (!hpriv->remapped_nvme)
aecec8b6
CH		 1528 return;
1529
894fba7f
KHF		 1530 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1531 hpriv->remapped_nvme);
f723fa4e
CH		 1532 dev_warn(&pdev->dev,
1533 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1534
1535 /*
1536 * Don't rely on the msi-x capability in the remap case,
1537 * share the legacy interrupt across ahci and remapped devices.
1538 */
1539 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1540}
1541
0b9e2988 1542static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1543{
0b9e2988 1544 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1545}
1546
a1c82311
RR		 1547static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1548 struct ahci_host_priv *hpriv)
5ca72c4f 1549{
0b9e2988 1550 int nvec;
5ca72c4f 1551
7b92b4f6 1552 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1553 return -ENODEV;
7b92b4f6 1554
7b92b4f6
AG		 1555 /*
1556 * If number of MSIs is less than number of ports then Sharing Last
1557 * Message mode could be enforced. In this case assume that advantage
1558 * of multipe MSIs is negated and use single MSI mode instead.
1559 */
17a51f12
CH		 1560 if (n_ports > 1) {
1561 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1562 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1563 if (nvec > 0) {
1564 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1565 hpriv->get_irq_vector = ahci_get_irq_vector;
1566 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1567 return nvec;
1568 }
5ca72c4f 1569
17a51f12
CH		 1570 /*
1571 * Fallback to single MSI mode if the controller
1572 * enforced MRSM mode.
1573 */
1574 printk(KERN_INFO
1575 "ahci: MRSM is on, fallback to single MSI\n");
1576 pci_free_irq_vectors(pdev);
1577 }
a478b097 1578 }
d684a90d 1579
0b9e2988
CH		 1580 /*
1581 * If the host is not capable of supporting per-port vectors, fall
1582 * back to single MSI before finally attempting single MSI-X.
1583 */
1584 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1585 if (nvec == 1)
ee2aad42 1586 return nvec;
0b9e2988 1587 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1588}
1589
b1a9585c
SP		 1590static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1591 struct ahci_host_priv *hpriv)
1592{
1593 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1594
1595
1596 /* Ignore processing for non mobile platforms */
1597 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1598 return;
1599
1600 /* user modified policy via module param */
1601 if (mobile_lpm_policy != -1) {
1602 policy = mobile_lpm_policy;
1603 goto update_policy;
1604 }
1605
1606#ifdef CONFIG_ACPI
1607 if (policy > ATA_LPM_MED_POWER &&
1608 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1609 if (hpriv->cap & HOST_CAP_PART)
1610 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1611 else if (hpriv->cap & HOST_CAP_SSC)
1612 policy = ATA_LPM_MIN_POWER;
1613 }
1614#endif
1615
1616update_policy:
1617 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1618 ap->target_lpm_policy = policy;
1619}
1620
c312ef17
DW		 1621static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1622{
1623 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1624 u16 tmp16;
1625
1626 /*
1627 * Only apply the 6-port PCS quirk for known legacy platforms.
1628 */
1629 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1630 return;
09d6ac8d
DW		 1631
1632 /* Skip applying the quirk on Denverton and beyond */
1633 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
c312ef17
DW		 1634 return;
1635
1636 /*
1637 * port_map is determined from PORTS_IMPL PCI register which is
1638 * implemented as write or write-once register. If the register
1639 * isn't programmed, ahci automatically generates it from number
1640 * of ports, which is good enough for PCS programming. It is
1641 * otherwise expected that platform firmware enables the ports
1642 * before the OS boots.
1643 */
1644 pci_read_config_word(pdev, PCS_6, &tmp16);
1645 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1646 tmp16 |= hpriv->port_map;
1647 pci_write_config_word(pdev, PCS_6, tmp16);
1648 }
1649}
1650
894fba7f
KHF		 1651static ssize_t remapped_nvme_show(struct device *dev,
1652 struct device_attribute *attr,
1653 char *buf)
1654{
1655 struct ata_host *host = dev_get_drvdata(dev);
1656 struct ahci_host_priv *hpriv = host->private_data;
1657
1658 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1659}
1660
1661static DEVICE_ATTR_RO(remapped_nvme);
1662
24dc5f33 1663static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1664{
e297d99e
TH		 1665 unsigned int board_id = ent->driver_data;
1666 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1667 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1668 struct device *dev = &pdev->dev;
1da177e4 1669 struct ahci_host_priv *hpriv;
4447d351 1670 struct ata_host *host;
c3ebd6a9 1671 int n_ports, i, rc;
318893e1 1672 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1673
1674 VPRINTK("ENTER\n");
1675
b429dd59 1676 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1677
06296a1e 1678 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1679
5b66c829
AC		 1680 /* The AHCI driver can only drive the SATA ports, the PATA driver
1681 can drive them all so if both drivers are selected make sure
1682 AHCI stays out of the way */
1683 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1684 return -ENODEV;
1685
cb85696d
JL		 1686 /* Apple BIOS on MCP89 prevents us using AHCI */
1687 if (is_mcp89_apple(pdev))
1688 ahci_mcp89_apple_enable(pdev);
c6353b45 1689
7a02267e
MN		 1690 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1691 * At the moment, we can only use the AHCI mode. Let the users know
1692 * that for SAS drives they're out of luck.
1693 */
1694 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1695 dev_info(&pdev->dev,
1696 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1697
b7ae128d 1698 /* Some devices use non-standard BARs */
318893e1
AR		 1699 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1700 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1701 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1702 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1703 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1704 if (pdev->device == 0xa01c)
1705 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1706 if (pdev->device == 0xa084)
1707 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
e49bd683
TY		 1708 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1709 if (pdev->device == 0x7a08)
1710 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
b1314e3f 1711 }
318893e1 1712
4447d351 1713 /* acquire resources */
24dc5f33 1714 rc = pcim_enable_device(pdev);
1da177e4
LT		 1715 if (rc)
1716 return rc;
1717
c4f7792c
TH		 1718 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1719 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1720 u8 map;
1721
1722 /* ICH6s share the same PCI ID for both piix and ahci
1723 * modes. Enabling ahci mode while MAP indicates
1724 * combined mode is a bad idea. Yield to ata_piix.
1725 */
1726 pci_read_config_byte(pdev, ICH_MAP, &map);
1727 if (map & 0x3) {
a44fec1f
JP		 1728 dev_info(&pdev->dev,
1729 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1730 return -ENODEV;
1731 }
1732 }
1733
6fec8871
PB		 1734 /* AHCI controllers often implement SFF compatible interface.
1735 * Grab all PCI BARs just in case.
1736 */
1737 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1738 if (rc == -EBUSY)
1739 pcim_pin_device(pdev);
1740 if (rc)
1741 return rc;
1742
24dc5f33
TH		 1743 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1744 if (!hpriv)
1745 return -ENOMEM;
417a1a6d
TH		 1746 hpriv->flags |= (unsigned long)pi.private_data;
1747
e297d99e
TH		 1748 /* MCP65 revision A1 and A2 can't do MSI */
1749 if (board_id == board_ahci_mcp65 &&
1750 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1751 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1752
e427fe04
SH		 1753 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1754 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1755 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1756
2fcad9d2
TH		 1757 /* only some SB600s can do 64bit DMA */
1758 if (ahci_sb600_enable_64bit(pdev))
1759 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1760
318893e1 1761 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1762
aecec8b6
CH		 1763 /* detect remapped nvme devices */
1764 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1765
894fba7f
KHF		 1766 sysfs_add_file_to_group(&pdev->dev.kobj,
1767 &dev_attr_remapped_nvme.attr,
1768 NULL);
1769
0cf4a7d6
JP		 1770 /* must set flag prior to save config in order to take effect */
1771 if (ahci_broken_devslp(pdev))
1772 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1773
d243bed3 1774#ifdef CONFIG_ARM64
234e6d2c
XY		 1775 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1776 pdev->device == 0xa235 &&
1777 pdev->revision < 0x30)
1778 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1779
d243bed3
TC		 1780 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1781 hpriv->irq_handler = ahci_thunderx_irq_handler;
1782#endif
1783
4447d351 1784 /* save initial config */
394d6e53 1785 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1786
c312ef17
DW		 1787 /*
1788 * If platform firmware failed to enable ports, try to enable
1789 * them here.
1790 */
1791 ahci_intel_pcs_quirk(pdev, hpriv);
1792
4447d351 1793 /* prepare host */
453d3131
RH		 1794 if (hpriv->cap & HOST_CAP_NCQ) {
1795 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1796 /*
1797 * Auto-activate optimization is supposed to be
1798 * supported on all AHCI controllers indicating NCQ
1799 * capability, but it seems to be broken on some
1800 * chipsets including NVIDIAs.
1801 */
1802 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1803 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1804
1805 /*
1806 * All AHCI controllers should be forward-compatible
1807 * with the new auxiliary field. This code should be
1808 * conditionalized if any buggy AHCI controllers are
1809 * encountered.
1810 */
1811 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1812 }
1da177e4 1813
7d50b60b
TH		 1814 if (hpriv->cap & HOST_CAP_PMP)
1815 pi.flags |= ATA_FLAG_PMP;
1816
0cbb0e77 1817 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1818
1fd68434
RW		 1819 if (ahci_broken_system_poweroff(pdev)) {
1820 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1821 dev_info(&pdev->dev,
1822 "quirky BIOS, skipping spindown on poweroff\n");
1823 }
1824
240630e6
HG		 1825 if (ahci_broken_lpm(pdev)) {
1826 pi.flags |= ATA_FLAG_NO_LPM;
1827 dev_warn(&pdev->dev,
1828 "BIOS update required for Link Power Management support\n");
1829 }
1830
9b10ae86
TH		 1831 if (ahci_broken_suspend(pdev)) {
1832 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1833 dev_warn(&pdev->dev,
1834 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1835 }
1836
5594639a
TH		 1837 if (ahci_broken_online(pdev)) {
1838 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1839 dev_info(&pdev->dev,
1840 "online status unreliable, applying workaround\n");
1841 }
1842
8bfd1743
SC		 1843
1844 /* Acer SA5-271 workaround modifies private_data */
1845 acer_sa5_271_workaround(hpriv, pdev);
1846
837f5f8f
TH		 1847 /* CAP.NP sometimes indicate the index of the last enabled
1848 * port, at other times, that of the last possible port, so
1849 * determining the maximum port number requires looking at
1850 * both CAP.NP and port_map.
1851 */
1852 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1853
1854 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1855 if (!host)
1856 return -ENOMEM;
4447d351 1857 host->private_data = hpriv;
0b9e2988
CH		 1858
1859 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1860 /* legacy intx interrupts */
1861 pci_intx(pdev, 1);
1862 }
0ce57f8a 1863 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1864
f3d7f23f 1865 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1866 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1867 else
d2782d96 1868 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1869
18f7ba4c
KCA		 1870 if (pi.flags & ATA_FLAG_EM)
1871 ahci_reset_em(host);
1872
4447d351 1873 for (i = 0; i < host->n_ports; i++) {
dab632e8 1874 struct ata_port *ap = host->ports[i];
4447d351 1875
318893e1
AR		 1876 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1877 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1878 0x100 + ap->port_no * 0x80, "port");
1879
18f7ba4c
KCA		 1880 /* set enclosure management message type */
1881 if (ap->flags & ATA_FLAG_EM)
008dbd61 1882 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c 1883
b1a9585c 1884 ahci_update_initial_lpm_policy(ap, hpriv);
18f7ba4c 1885
dab632e8 1886 /* disabled/not-implemented port */
350756f6 1887 if (!(hpriv->port_map & (1 << i)))
dab632e8 1888 ap->ops = &ata_dummy_port_ops;
4447d351 1889 }
d447df14 1890
edc93052
TH		 1891 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1892 ahci_p5wdh_workaround(host);
1893
f80ae7e4
TH		 1894 /* apply gtf filter quirk */
1895 ahci_gtf_filter_workaround(host);
1896
4447d351
TH		 1897 /* initialize adapter */
1898 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1899 if (rc)
24dc5f33 1900 return rc;
1da177e4 1901
c312ef17 1902 rc = ahci_reset_controller(host);
4447d351
TH		 1903 if (rc)
1904 return rc;
1da177e4 1905
781d6550 1906 ahci_pci_init_controller(host);
439fcaec 1907 ahci_pci_print_info(host);
1da177e4 1908
4447d351 1909 pci_set_master(pdev);
5ca72c4f 1910
02e53293
MW		 1911 rc = ahci_host_activate(host, &ahci_sht);
1912 if (rc)
1913 return rc;
1914
1915 pm_runtime_put_noidle(&pdev->dev);
1916 return 0;
1917}
1918
10a663a1
PK		 1919static void ahci_shutdown_one(struct pci_dev *pdev)
1920{
1921 ata_pci_shutdown_one(pdev);
1922}
1923
02e53293
MW		 1924static void ahci_remove_one(struct pci_dev *pdev)
1925{
894fba7f
KHF		 1926 sysfs_remove_file_from_group(&pdev->dev.kobj,
1927 &dev_attr_remapped_nvme.attr,
1928 NULL);
02e53293
MW		 1929 pm_runtime_get_noresume(&pdev->dev);
1930 ata_pci_remove_one(pdev);
907f4678 1931}
1da177e4 1932
2fc75da0 1933module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1934
1935MODULE_AUTHOR("Jeff Garzik");
1936MODULE_DESCRIPTION("AHCI SATA low-level driver");
1937MODULE_LICENSE("GPL");
1938MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1939MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)