[linux-2.6-block.git] / drivers / amba / tegra-ahb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 * Copyright (C) 2011 Google, Inc.
 *
 * Author:
 *	Jay Cheng <jacheng@nvidia.com>
 *	James Wylder <james.wylder@motorola.com>
 *	Benoit Goby <benoit@android.com>
 *	Colin Cross <ccross@android.com>
 *	Hiroshi DOYU <hdoyu@nvidia.com>
 */

#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/of.h>

#include <soc/tegra/ahb.h>

#define DRV_NAME "tegra-ahb"

#define AHB_ARBITRATION_DISABLE		0x04
#define AHB_ARBITRATION_PRIORITY_CTRL	0x08
#define   AHB_PRIORITY_WEIGHT(x)	(((x) & 0x7) << 29)
#define   PRIORITY_SELECT_USB BIT(6)
#define   PRIORITY_SELECT_USB2 BIT(18)
#define   PRIORITY_SELECT_USB3 BIT(17)

#define AHB_GIZMO_AHB_MEM		0x10
#define   ENB_FAST_REARBITRATE BIT(2)
#define   DONT_SPLIT_AHB_WR     BIT(7)

#define AHB_GIZMO_APB_DMA		0x14
#define AHB_GIZMO_IDE			0x1c
#define AHB_GIZMO_USB			0x20
#define AHB_GIZMO_AHB_XBAR_BRIDGE	0x24
#define AHB_GIZMO_CPU_AHB_BRIDGE	0x28
#define AHB_GIZMO_COP_AHB_BRIDGE	0x2c
#define AHB_GIZMO_XBAR_APB_CTLR		0x30
#define AHB_GIZMO_VCP_AHB_BRIDGE	0x34
#define AHB_GIZMO_NAND			0x40
#define AHB_GIZMO_SDMMC4		0x48
#define AHB_GIZMO_XIO			0x4c
#define AHB_GIZMO_BSEV			0x64
#define AHB_GIZMO_BSEA			0x74
#define AHB_GIZMO_NOR			0x78
#define AHB_GIZMO_USB2			0x7c
#define AHB_GIZMO_USB3			0x80
#define   IMMEDIATE	BIT(18)

#define AHB_GIZMO_SDMMC1		0x84
#define AHB_GIZMO_SDMMC2		0x88
#define AHB_GIZMO_SDMMC3		0x8c
#define AHB_MEM_PREFETCH_CFG_X		0xdc
#define AHB_ARBITRATION_XBAR_CTRL	0xe0
#define AHB_MEM_PREFETCH_CFG3		0xe4
#define AHB_MEM_PREFETCH_CFG4		0xe8
#define AHB_MEM_PREFETCH_CFG1		0xf0
#define AHB_MEM_PREFETCH_CFG2		0xf4
#define   PREFETCH_ENB	BIT(31)
#define   MST_ID(x)	(((x) & 0x1f) << 26)
#define   AHBDMA_MST_ID	MST_ID(5)
#define   USB_MST_ID	MST_ID(6)
#define   USB2_MST_ID	MST_ID(18)
#define   USB3_MST_ID	MST_ID(17)
#define   ADDR_BNDRY(x)	(((x) & 0xf) << 21)
#define   INACTIVITY_TIMEOUT(x)	(((x) & 0xffff) << 0)

#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID	0xfc

#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)

/*
 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
 * prior to Tegra124 generally use a physical base address ending in
 * 0x4 for the AHB IP block.  According to the TRM, the low byte
 * should be 0x0.  During device probing, this macro is used to detect
 * whether the passed-in physical address is incorrect, and if so, to
 * correct it.
 */
#define INCORRECT_BASE_ADDR_LOW_BYTE		0x4

static struct platform_driver tegra_ahb_driver;

static const u32 tegra_ahb_gizmo[] = {
	AHB_ARBITRATION_DISABLE,
	AHB_ARBITRATION_PRIORITY_CTRL,
	AHB_GIZMO_AHB_MEM,
	AHB_GIZMO_APB_DMA,
	AHB_GIZMO_IDE,
	AHB_GIZMO_USB,
	AHB_GIZMO_AHB_XBAR_BRIDGE,
	AHB_GIZMO_CPU_AHB_BRIDGE,
	AHB_GIZMO_COP_AHB_BRIDGE,
	AHB_GIZMO_XBAR_APB_CTLR,
	AHB_GIZMO_VCP_AHB_BRIDGE,
	AHB_GIZMO_NAND,
	AHB_GIZMO_SDMMC4,
	AHB_GIZMO_XIO,
	AHB_GIZMO_BSEV,
	AHB_GIZMO_BSEA,
	AHB_GIZMO_NOR,
	AHB_GIZMO_USB2,
	AHB_GIZMO_USB3,
	AHB_GIZMO_SDMMC1,
	AHB_GIZMO_SDMMC2,
	AHB_GIZMO_SDMMC3,
	AHB_MEM_PREFETCH_CFG_X,
	AHB_ARBITRATION_XBAR_CTRL,
	AHB_MEM_PREFETCH_CFG3,
	AHB_MEM_PREFETCH_CFG4,
	AHB_MEM_PREFETCH_CFG1,
	AHB_MEM_PREFETCH_CFG2,
	AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
};

struct tegra_ahb {
	void __iomem	*regs;
	struct device	*dev;
	u32		ctx[0];
};

static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
{
	return readl(ahb->regs + offset);
}

static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
{
	writel(value, ahb->regs + offset);
}

#ifdef CONFIG_TEGRA_IOMMU_SMMU
static int tegra_ahb_match_by_smmu(struct device *dev, const void *data)
{
	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	const struct device_node *dn = data;

	return (ahb->dev->of_node == dn) ? 1 : 0;
}

int tegra_ahb_enable_smmu(struct device_node *dn)
{
	struct device *dev;
	u32 val;
	struct tegra_ahb *ahb;

	dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
				 tegra_ahb_match_by_smmu);
	if (!dev)
		return -EPROBE_DEFER;
	ahb = dev_get_drvdata(dev);
	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
	val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
	return 0;
}
EXPORT_SYMBOL(tegra_ahb_enable_smmu);
#endif

static int __maybe_unused tegra_ahb_suspend(struct device *dev)
{
	int i;
	struct tegra_ahb *ahb = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
		ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
	return 0;
}

static int __maybe_unused tegra_ahb_resume(struct device *dev)
{
	int i;
	struct tegra_ahb *ahb = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
		gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
	return 0;
}

static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
			    tegra_ahb_suspend,
			    tegra_ahb_resume, NULL);

static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
{
	u32 val;

	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
	val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);

	val = gizmo_readl(ahb, AHB_GIZMO_USB);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB);

	val = gizmo_readl(ahb, AHB_GIZMO_USB2);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB2);

	val = gizmo_readl(ahb, AHB_GIZMO_USB3);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB3);

	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
	val |= PRIORITY_SELECT_USB |
		PRIORITY_SELECT_USB2 |
		PRIORITY_SELECT_USB3 |
		AHB_PRIORITY_WEIGHT(7);
	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		AHBDMA_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB3_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB2_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
}

static int tegra_ahb_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct tegra_ahb *ahb;
	size_t bytes;

	bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
	if (!ahb)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	/* Correct the IP block base address if necessary */
	if (res &&
	    (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
	    INCORRECT_BASE_ADDR_LOW_BYTE) {
		dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
		res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
	}

	ahb->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ahb->regs))
		return PTR_ERR(ahb->regs);

	ahb->dev = &pdev->dev;
	platform_set_drvdata(pdev, ahb);
	tegra_ahb_gizmo_init(ahb);
	return 0;
}

static const struct of_device_id tegra_ahb_of_match[] = {
	{ .compatible = "nvidia,tegra30-ahb", },
	{ .compatible = "nvidia,tegra20-ahb", },
	{},
};

static struct platform_driver tegra_ahb_driver = {
	.probe = tegra_ahb_probe,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra_ahb_of_match,
		.pm = &tegra_ahb_pm,
	},
};
module_platform_driver(tegra_ahb_driver);

MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
MODULE_DESCRIPTION("Tegra AHB driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
87d0bab2 HD	2	/*
	3	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
	4	* Copyright (C) 2011 Google, Inc.
	5	*
	6	* Author:
	7	* Jay Cheng <jacheng@nvidia.com>
	8	* James Wylder <james.wylder@motorola.com>
	9	* Benoit Goby <benoit@android.com>
	10	* Colin Cross <ccross@android.com>
	11	* Hiroshi DOYU <hdoyu@nvidia.com>
87d0bab2 HD	12	*/
87d0bab2 HD	13
903b33e0	14	#include <linux/err.h>
87d0bab2 HD	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/io.h>
049e4b3f	19	#include <linux/of.h>
306a7f91 TR	20
306a7f91 TR	21	#include <soc/tegra/ahb.h>
87d0bab2 HD	22
	23	#define DRV_NAME "tegra-ahb"
	24
049e4b3f PW	25	#define AHB_ARBITRATION_DISABLE 0x04
049e4b3f PW	26	#define AHB_ARBITRATION_PRIORITY_CTRL 0x08
87d0bab2 HD	27	#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
	28	#define PRIORITY_SELECT_USB BIT(6)
	29	#define PRIORITY_SELECT_USB2 BIT(18)
	30	#define PRIORITY_SELECT_USB3 BIT(17)
	31
049e4b3f	32	#define AHB_GIZMO_AHB_MEM 0x10
87d0bab2 HD	33	#define ENB_FAST_REARBITRATE BIT(2)
	34	#define DONT_SPLIT_AHB_WR BIT(7)
	35
049e4b3f PW	36	#define AHB_GIZMO_APB_DMA 0x14
	37	#define AHB_GIZMO_IDE 0x1c
	38	#define AHB_GIZMO_USB 0x20
	39	#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
	40	#define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
	41	#define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
	42	#define AHB_GIZMO_XBAR_APB_CTLR 0x30
	43	#define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
	44	#define AHB_GIZMO_NAND 0x40
	45	#define AHB_GIZMO_SDMMC4 0x48
	46	#define AHB_GIZMO_XIO 0x4c
	47	#define AHB_GIZMO_BSEV 0x64
	48	#define AHB_GIZMO_BSEA 0x74
	49	#define AHB_GIZMO_NOR 0x78
	50	#define AHB_GIZMO_USB2 0x7c
	51	#define AHB_GIZMO_USB3 0x80
87d0bab2 HD	52	#define IMMEDIATE BIT(18)
87d0bab2 HD	53
049e4b3f PW	54	#define AHB_GIZMO_SDMMC1 0x84
	55	#define AHB_GIZMO_SDMMC2 0x88
	56	#define AHB_GIZMO_SDMMC3 0x8c
	57	#define AHB_MEM_PREFETCH_CFG_X 0xdc
	58	#define AHB_ARBITRATION_XBAR_CTRL 0xe0
	59	#define AHB_MEM_PREFETCH_CFG3 0xe4
	60	#define AHB_MEM_PREFETCH_CFG4 0xe8
	61	#define AHB_MEM_PREFETCH_CFG1 0xf0
	62	#define AHB_MEM_PREFETCH_CFG2 0xf4
87d0bab2 HD	63	#define PREFETCH_ENB BIT(31)
	64	#define MST_ID(x) (((x) & 0x1f) << 26)
	65	#define AHBDMA_MST_ID MST_ID(5)
	66	#define USB_MST_ID MST_ID(6)
	67	#define USB2_MST_ID MST_ID(18)
	68	#define USB3_MST_ID MST_ID(17)
	69	#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
	70	#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
	71
049e4b3f	72	#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
87d0bab2	73
89c788ba HD	74	#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
89c788ba HD	75
ce7a10b0 PW	76	/*
	77	* INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
	78	* prior to Tegra124 generally use a physical base address ending in
	79	* 0x4 for the AHB IP block. According to the TRM, the low byte
	80	* should be 0x0. During device probing, this macro is used to detect
	81	* whether the passed-in physical address is incorrect, and if so, to
	82	* correct it.
	83	*/
	84	#define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
	85
89c788ba HD	86	static struct platform_driver tegra_ahb_driver;
89c788ba HD	87
87d0bab2 HD	88	static const u32 tegra_ahb_gizmo[] = {
	89	AHB_ARBITRATION_DISABLE,
	90	AHB_ARBITRATION_PRIORITY_CTRL,
	91	AHB_GIZMO_AHB_MEM,
	92	AHB_GIZMO_APB_DMA,
	93	AHB_GIZMO_IDE,
	94	AHB_GIZMO_USB,
	95	AHB_GIZMO_AHB_XBAR_BRIDGE,
	96	AHB_GIZMO_CPU_AHB_BRIDGE,
	97	AHB_GIZMO_COP_AHB_BRIDGE,
	98	AHB_GIZMO_XBAR_APB_CTLR,
	99	AHB_GIZMO_VCP_AHB_BRIDGE,
	100	AHB_GIZMO_NAND,
	101	AHB_GIZMO_SDMMC4,
	102	AHB_GIZMO_XIO,
	103	AHB_GIZMO_BSEV,
	104	AHB_GIZMO_BSEA,
	105	AHB_GIZMO_NOR,
	106	AHB_GIZMO_USB2,
	107	AHB_GIZMO_USB3,
	108	AHB_GIZMO_SDMMC1,
	109	AHB_GIZMO_SDMMC2,
	110	AHB_GIZMO_SDMMC3,
	111	AHB_MEM_PREFETCH_CFG_X,
	112	AHB_ARBITRATION_XBAR_CTRL,
	113	AHB_MEM_PREFETCH_CFG3,
	114	AHB_MEM_PREFETCH_CFG4,
	115	AHB_MEM_PREFETCH_CFG1,
	116	AHB_MEM_PREFETCH_CFG2,
	117	AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
	118	};
	119
	120	struct tegra_ahb {
	121	void __iomem *regs;
	122	struct device *dev;
	123	u32 ctx[0];
	124	};
	125
	126	static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
	127	{
ce7a10b0	128	return readl(ahb->regs + offset);
87d0bab2 HD	129	}
	130
	131	static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
	132	{
ce7a10b0	133	writel(value, ahb->regs + offset);
87d0bab2 HD	134	}
87d0bab2 HD	135
b44bf43b	136	#ifdef CONFIG_TEGRA_IOMMU_SMMU
92ce7e83	137	static int tegra_ahb_match_by_smmu(struct device dev, const void data)
89c788ba HD	138	{
89c788ba HD	139	struct tegra_ahb *ahb = dev_get_drvdata(dev);
92ce7e83	140	const struct device_node *dn = data;
89c788ba HD	141
	142	return (ahb->dev->of_node == dn) ? 1 : 0;
	143	}
	144
	145	int tegra_ahb_enable_smmu(struct device_node *dn)
	146	{
	147	struct device *dev;
	148	u32 val;
	149	struct tegra_ahb *ahb;
	150
	151	dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
	152	tegra_ahb_match_by_smmu);
	153	if (!dev)
	154	return -EPROBE_DEFER;
	155	ahb = dev_get_drvdata(dev);
	156	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
	157	val \|= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
	158	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
	159	return 0;
	160	}
	161	EXPORT_SYMBOL(tegra_ahb_enable_smmu);
	162	#endif
	163
6d616560	164	static int __maybe_unused tegra_ahb_suspend(struct device *dev)
87d0bab2 HD	165	{
	166	int i;
	167	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	168
	169	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
	170	ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
	171	return 0;
	172	}
	173
6d616560	174	static int __maybe_unused tegra_ahb_resume(struct device *dev)
87d0bab2 HD	175	{
	176	int i;
	177	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	178
	179	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
	180	gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
	181	return 0;
	182	}
	183
	184	static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
	185	tegra_ahb_suspend,
	186	tegra_ahb_resume, NULL);
	187
	188	static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
	189	{
	190	u32 val;
	191
	192	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
	193	val \|= ENB_FAST_REARBITRATE \| IMMEDIATE \| DONT_SPLIT_AHB_WR;
	194	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
	195
	196	val = gizmo_readl(ahb, AHB_GIZMO_USB);
	197	val \|= IMMEDIATE;
	198	gizmo_writel(ahb, val, AHB_GIZMO_USB);
	199
	200	val = gizmo_readl(ahb, AHB_GIZMO_USB2);
	201	val \|= IMMEDIATE;
	202	gizmo_writel(ahb, val, AHB_GIZMO_USB2);
	203
	204	val = gizmo_readl(ahb, AHB_GIZMO_USB3);
	205	val \|= IMMEDIATE;
	206	gizmo_writel(ahb, val, AHB_GIZMO_USB3);
	207
	208	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
	209	val \|= PRIORITY_SELECT_USB \|
	210	PRIORITY_SELECT_USB2 \|
	211	PRIORITY_SELECT_USB3 \|
	212	AHB_PRIORITY_WEIGHT(7);
	213	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
	214
	215	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
	216	val &= ~MST_ID(~0);
	217	val \|= PREFETCH_ENB \|
	218	AHBDMA_MST_ID \|
	219	ADDR_BNDRY(0xc) \|
	220	INACTIVITY_TIMEOUT(0x1000);
	221	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
	222
	223	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
	224	val &= ~MST_ID(~0);
	225	val \|= PREFETCH_ENB \|
	226	USB_MST_ID \|
	227	ADDR_BNDRY(0xc) \|
	228	INACTIVITY_TIMEOUT(0x1000);
	229	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
	230
	231	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
	232	val &= ~MST_ID(~0);
	233	val \|= PREFETCH_ENB \|
	234	USB3_MST_ID \|
	235	ADDR_BNDRY(0xc) \|
	236	INACTIVITY_TIMEOUT(0x1000);
	237	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
	238
239	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
240	val &= ~MST_ID(~0);
241	val \|= PREFETCH_ENB \|
242	USB2_MST_ID \|
243	ADDR_BNDRY(0xc) \|
244	INACTIVITY_TIMEOUT(0x1000);
245	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
246	}
247
c571b211	248	static int tegra_ahb_probe(struct platform_device *pdev)
87d0bab2 HD	249	{
	250	struct resource *res;
	251	struct tegra_ahb *ahb;
	252	size_t bytes;
	253
	254	bytes = sizeof(ahb) + sizeof(u32) ARRAY_SIZE(tegra_ahb_gizmo);
	255	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
	256	if (!ahb)
	257	return -ENOMEM;
	258
	259	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ce7a10b0 PW	260
	261	/* Correct the IP block base address if necessary */
	262	if (res &&
	263	(res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
	264	INCORRECT_BASE_ADDR_LOW_BYTE) {
	265	dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
	266	res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
	267	}
	268
903b33e0 TR	269	ahb->regs = devm_ioremap_resource(&pdev->dev, res);
	270	if (IS_ERR(ahb->regs))
	271	return PTR_ERR(ahb->regs);
87d0bab2 HD	272
	273	ahb->dev = &pdev->dev;
	274	platform_set_drvdata(pdev, ahb);
	275	tegra_ahb_gizmo_init(ahb);
	276	return 0;
	277	}
	278
c571b211	279	static const struct of_device_id tegra_ahb_of_match[] = {
87d0bab2 HD	280	{ .compatible = "nvidia,tegra30-ahb", },
	281	{ .compatible = "nvidia,tegra20-ahb", },
	282	{},
	283	};
	284
	285	static struct platform_driver tegra_ahb_driver = {
	286	.probe = tegra_ahb_probe,
87d0bab2 HD	287	.driver = {
87d0bab2 HD	288	.name = DRV_NAME,
87d0bab2 HD	289	.of_match_table = tegra_ahb_of_match,
	290	.pm = &tegra_ahb_pm,
	291	},
	292	};
	293	module_platform_driver(tegra_ahb_driver);
	294
	295	MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
	296	MODULE_DESCRIPTION("Tegra AHB driver");
	297	MODULE_LICENSE("GPL v2");
	298	MODULE_ALIAS("platform:" DRV_NAME);