[linux-2.6-block.git] / drivers / acpi / spcr.c

/*
 * Copyright (c) 2012, Intel Corporation
 * Copyright (c) 2015, Red Hat, Inc.
 * Copyright (c) 2015, 2016 Linaro Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#define pr_fmt(fmt) "ACPI: SPCR: " fmt

#include <linux/acpi.h>
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/serial_core.h>

/*
 * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
 * occasionally getting stuck as 1. To avoid the potential for a hang, check
 * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
 * implementations, so only do so if an affected platform is detected in
 * acpi_parse_spcr().
 */
bool qdf2400_e44_present;
EXPORT_SYMBOL(qdf2400_e44_present);

/*
 * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
 * Detect them by examining the OEM fields in the SPCR header, similiar to PCI
 * quirk detection in pci_mcfg.c.
 */
static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
{
	if (memcmp(h->oem_id, "QCOM  ", ACPI_OEM_ID_SIZE))
		return false;

	if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
		return true;

	if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
			h->oem_revision == 1)
		return true;

	return false;
}

/*
 * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
 * register aligned to 32-bit. In addition, the BIOS also encoded the
 * access width to be 8 bits. This function detects this errata condition.
 */
static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
{
	bool xgene_8250 = false;

	if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
		return false;

	if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
	    memcmp(tb->header.oem_id, "HPE   ", ACPI_OEM_ID_SIZE))
		return false;

	if (!memcmp(tb->header.oem_table_id, "XGENESPC",
	    ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
		xgene_8250 = true;

	if (!memcmp(tb->header.oem_table_id, "ProLiant",
	    ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
		xgene_8250 = true;

	return xgene_8250;
}

/**
 * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
 *
 * @enable_earlycon: set up earlycon for the console specified by the table
 * @enable_console: setup the console specified by the table.
 *
 * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
 * defined to parse ACPI SPCR table.  As a result of the parsing preferred
 * console is registered and if @enable_earlycon is true, earlycon is set up.
 * If @enable_console is true the system console is also configured.
 *
 * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
 * from arch initialization code as soon as the DT/ACPI decision is made.
 *
 */
int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
{
	static char opts[64];
	struct acpi_table_spcr *table;
	acpi_status status;
	char *uart;
	char *iotype;
	int baud_rate;
	int err;

	if (acpi_disabled)
		return -ENODEV;

	status = acpi_get_table(ACPI_SIG_SPCR, 0,
				(struct acpi_table_header **)&table);

	if (ACPI_FAILURE(status))
		return -ENOENT;

	if (table->header.revision < 2)
		pr_info("SPCR table version %d\n", table->header.revision);

	if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
		switch (ACPI_ACCESS_BIT_WIDTH((
			table->serial_port.access_width))) {
		default:
			pr_err("Unexpected SPCR Access Width.  Defaulting to byte size\n");
		case 8:
			iotype = "mmio";
			break;
		case 16:
			iotype = "mmio16";
			break;
		case 32:
			iotype = "mmio32";
			break;
		}
	} else
		iotype = "io";

	switch (table->interface_type) {
	case ACPI_DBG2_ARM_SBSA_32BIT:
		iotype = "mmio32";
		/* fall through */
	case ACPI_DBG2_ARM_PL011:
	case ACPI_DBG2_ARM_SBSA_GENERIC:
	case ACPI_DBG2_BCM2835:
		uart = "pl011";
		break;
	case ACPI_DBG2_16550_COMPATIBLE:
	case ACPI_DBG2_16550_SUBSET:
		uart = "uart";
		break;
	default:
		err = -ENOENT;
		goto done;
	}

	switch (table->baud_rate) {
	case 3:
		baud_rate = 9600;
		break;
	case 4:
		baud_rate = 19200;
		break;
	case 6:
		baud_rate = 57600;
		break;
	case 7:
		baud_rate = 115200;
		break;
	default:
		err = -ENOENT;
		goto done;
	}

	/*
	 * If the E44 erratum is required, then we need to tell the pl011
	 * driver to implement the work-around.
	 *
	 * The global variable is used by the probe function when it
	 * creates the UARTs, whether or not they're used as a console.
	 *
	 * If the user specifies "traditional" earlycon, the qdf2400_e44
	 * console name matches the EARLYCON_DECLARE() statement, and
	 * SPCR is not used.  Parameter "earlycon" is false.
	 *
	 * If the user specifies "SPCR" earlycon, then we need to update
	 * the console name so that it also says "qdf2400_e44".  Parameter
	 * "earlycon" is true.
	 *
	 * For consistency, if we change the console name, then we do it
	 * for everyone, not just earlycon.
	 */
	if (qdf2400_erratum_44_present(&table->header)) {
		qdf2400_e44_present = true;
		if (enable_earlycon)
			uart = "qdf2400_e44";
	}

	if (xgene_8250_erratum_present(table)) {
		iotype = "mmio32";

		/* for xgene v1 and v2 we don't know the clock rate of the
		 * UART so don't attempt to change to the baud rate state
		 * in the table because driver cannot calculate the dividers
		 */
		snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
			 table->serial_port.address);
	} else {
		snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
			 table->serial_port.address, baud_rate);
	}

	pr_info("console: %s\n", opts);

	if (enable_earlycon)
		setup_earlycon(opts);

	if (enable_console)
		err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
	else
		err = 0;
done:
	acpi_put_table((struct acpi_table_header *)table);
	return err;
}
Commit	Line	Data
ad1696f6 AM	1	/*
	2	* Copyright (c) 2012, Intel Corporation
	3	* Copyright (c) 2015, Red Hat, Inc.
	4	* Copyright (c) 2015, 2016 Linaro Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#define pr_fmt(fmt) "ACPI: SPCR: " fmt
	13
	14	#include <linux/acpi.h>
	15	#include <linux/console.h>
	16	#include <linux/kernel.h>
	17	#include <linux/serial_core.h>
	18
37ef38f3 TT	19	/*
	20	* Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
	21	* occasionally getting stuck as 1. To avoid the potential for a hang, check
	22	* TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
	23	* implementations, so only do so if an affected platform is detected in
0231d000	24	* acpi_parse_spcr().
37ef38f3 TT	25	*/
	26	bool qdf2400_e44_present;
	27	EXPORT_SYMBOL(qdf2400_e44_present);
	28
d8a4995b CC	29	/*
	30	* Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
	31	* Detect them by examining the OEM fields in the SPCR header, similiar to PCI
	32	* quirk detection in pci_mcfg.c.
	33	*/
	34	static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
	35	{
	36	if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
	37	return false;
	38
	39	if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
	40	return true;
	41
	42	if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
542ed784	43	h->oem_revision == 1)
d8a4995b CC	44	return true;
	45
	46	return false;
	47	}
	48
79a64832 LH	49	/*
	50	* APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
	51	* register aligned to 32-bit. In addition, the BIOS also encoded the
	52	* access width to be 8 bits. This function detects this errata condition.
	53	*/
	54	static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
	55	{
dee82bc1 GG	56	bool xgene_8250 = false;
dee82bc1 GG	57
79a64832 LH	58	if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
	59	return false;
	60
dee82bc1 GG	61	if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
dee82bc1 GG	62	memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
79a64832 LH	63	return false;
	64
	65	if (!memcmp(tb->header.oem_table_id, "XGENESPC",
	66	ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
dee82bc1	67	xgene_8250 = true;
79a64832	68
dee82bc1 GG	69	if (!memcmp(tb->header.oem_table_id, "ProLiant",
	70	ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
	71	xgene_8250 = true;
	72
	73	return xgene_8250;
79a64832 LH	74	}
79a64832 LH	75
ad1696f6	76	/**
0231d000	77	* acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
ad1696f6	78	*
0231d000 PB	79	* @enable_earlycon: set up earlycon for the console specified by the table
0231d000 PB	80	* @enable_console: setup the console specified by the table.
ad1696f6 AM	81	*
	82	* For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
	83	* defined to parse ACPI SPCR table. As a result of the parsing preferred
0231d000 PB	84	* console is registered and if @enable_earlycon is true, earlycon is set up.
0231d000 PB	85	* If @enable_console is true the system console is also configured.
ad1696f6 AM	86	*
ad1696f6 AM	87	* When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
183b8021	88	* from arch initialization code as soon as the DT/ACPI decision is made.
ad1696f6 AM	89	*
ad1696f6 AM	90	*/
0231d000	91	int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
ad1696f6 AM	92	{
	93	static char opts[64];
	94	struct acpi_table_spcr *table;
ad1696f6 AM	95	acpi_status status;
	96	char *uart;
	97	char *iotype;
	98	int baud_rate;
	99	int err;
	100
	101	if (acpi_disabled)
	102	return -ENODEV;
	103
6b11d1d6 LZ	104	status = acpi_get_table(ACPI_SIG_SPCR, 0,
6b11d1d6 LZ	105	(struct acpi_table_header **)&table);
ad1696f6 AM	106
	107	if (ACPI_FAILURE(status))
	108	return -ENOENT;
	109
0231d000 PB	110	if (table->header.revision < 2)
0231d000 PB	111	pr_info("SPCR table version %d\n", table->header.revision);
ad1696f6	112
2bece493	113	if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
4eebedd8 LZ	114	switch (ACPI_ACCESS_BIT_WIDTH((
4eebedd8 LZ	115	table->serial_port.access_width))) {
2bece493 LH	116	default:
2bece493 LH	117	pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n");
4eebedd8	118	case 8:
2bece493 LH	119	iotype = "mmio";
2bece493 LH	120	break;
4eebedd8	121	case 16:
2bece493 LH	122	iotype = "mmio16";
2bece493 LH	123	break;
4eebedd8	124	case 32:
2bece493 LH	125	iotype = "mmio32";
	126	break;
	127	}
	128	} else
	129	iotype = "io";
ad1696f6 AM	130
	131	switch (table->interface_type) {
	132	case ACPI_DBG2_ARM_SBSA_32BIT:
	133	iotype = "mmio32";
	134	/* fall through */
	135	case ACPI_DBG2_ARM_PL011:
	136	case ACPI_DBG2_ARM_SBSA_GENERIC:
	137	case ACPI_DBG2_BCM2835:
	138	uart = "pl011";
	139	break;
	140	case ACPI_DBG2_16550_COMPATIBLE:
	141	case ACPI_DBG2_16550_SUBSET:
	142	uart = "uart";
	143	break;
	144	default:
	145	err = -ENOENT;
	146	goto done;
	147	}
	148
	149	switch (table->baud_rate) {
	150	case 3:
	151	baud_rate = 9600;
	152	break;
	153	case 4:
	154	baud_rate = 19200;
	155	break;
	156	case 6:
	157	baud_rate = 57600;
	158	break;
	159	case 7:
	160	baud_rate = 115200;
	161	break;
	162	default:
	163	err = -ENOENT;
	164	goto done;
	165	}
	166
37ef38f3 TT	167	/*
	168	* If the E44 erratum is required, then we need to tell the pl011
	169	* driver to implement the work-around.
	170	*
	171	* The global variable is used by the probe function when it
	172	* creates the UARTs, whether or not they're used as a console.
	173	*
	174	* If the user specifies "traditional" earlycon, the qdf2400_e44
	175	* console name matches the EARLYCON_DECLARE() statement, and
	176	* SPCR is not used. Parameter "earlycon" is false.
	177	*
	178	* If the user specifies "SPCR" earlycon, then we need to update
	179	* the console name so that it also says "qdf2400_e44". Parameter
	180	* "earlycon" is true.
	181	*
	182	* For consistency, if we change the console name, then we do it
	183	* for everyone, not just earlycon.
	184	*/
	185	if (qdf2400_erratum_44_present(&table->header)) {
	186	qdf2400_e44_present = true;
0231d000	187	if (enable_earlycon)
37ef38f3 TT	188	uart = "qdf2400_e44";
	189	}
	190
03c3876f	191	if (xgene_8250_erratum_present(table)) {
79a64832	192	iotype = "mmio32";
d8a4995b	193
03c3876f GG	194	/* for xgene v1 and v2 we don't know the clock rate of the
	195	* UART so don't attempt to change to the baud rate state
	196	* in the table because driver cannot calculate the dividers
	197	*/
	198	snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
	199	table->serial_port.address);
	200	} else {
	201	snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
	202	table->serial_port.address, baud_rate);
	203	}
ad1696f6 AM	204
	205	pr_info("console: %s\n", opts);
	206
0231d000	207	if (enable_earlycon)
ad1696f6 AM	208	setup_earlycon(opts);
ad1696f6 AM	209
0231d000 PB	210	if (enable_console)
	211	err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
	212	else
	213	err = 0;
ad1696f6	214	done:
6b11d1d6	215	acpi_put_table((struct acpi_table_header *)table);
ad1696f6 AM	216	return err;
ad1696f6 AM	217	}