Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
1da177e4 LT |
36 | #include <linux/acpi.h> |
37 | #include <linux/dmi.h> | |
38 | #include <linux/moduleparam.h> | |
4e57b681 | 39 | #include <linux/sched.h> /* need_resched() */ |
e8db0be1 | 40 | #include <linux/pm_qos.h> |
e9e2cdb4 | 41 | #include <linux/clockchips.h> |
4f86d3a8 | 42 | #include <linux/cpuidle.h> |
ba84be23 | 43 | #include <linux/irqflags.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
c1e3b377 | 60 | #include <asm/processor.h> |
1da177e4 | 61 | |
a192a958 LB |
62 | #define PREFIX "ACPI: " |
63 | ||
1da177e4 | 64 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 65 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 66 | ACPI_MODULE_NAME("processor_idle"); |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
68 | #define C2_OVERHEAD 1 /* 1us */ |
69 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 70 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 71 | |
4f86d3a8 LB |
72 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
73 | module_param(max_cstate, uint, 0000); | |
b6835052 | 74 | static unsigned int nocst __read_mostly; |
1da177e4 | 75 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
76 | static int bm_check_disable __read_mostly; |
77 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 78 | |
25de5718 | 79 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 80 | module_param(latency_factor, uint, 0644); |
1da177e4 | 81 | |
3d339dcb DL |
82 | static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); |
83 | ||
d1896049 TR |
84 | static int disabled_by_idle_boot_param(void) |
85 | { | |
86 | return boot_option_idle_override == IDLE_POLL || | |
87 | boot_option_idle_override == IDLE_FORCE_MWAIT || | |
88 | boot_option_idle_override == IDLE_HALT; | |
89 | } | |
90 | ||
1da177e4 LT |
91 | /* |
92 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
93 | * For now disable this. Probably a bug somewhere else. | |
94 | * | |
95 | * To skip this limit, boot/load with a large max_cstate limit. | |
96 | */ | |
1855256c | 97 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
98 | { |
99 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
100 | return 0; | |
101 | ||
3d35600a | 102 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
103 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
104 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 105 | |
3d35600a | 106 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
107 | |
108 | return 0; | |
109 | } | |
110 | ||
7ded5689 AR |
111 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
112 | callers to only run once -AK */ | |
113 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
114 | { set_max_cstate, "Clevo 5600D", { |
115 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
116 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 117 | (void *)2}, |
370d5cd8 AV |
118 | { set_max_cstate, "Pavilion zv5000", { |
119 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
120 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
121 | (void *)1}, | |
122 | { set_max_cstate, "Asus L8400B", { | |
123 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
124 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
125 | (void *)1}, | |
1da177e4 LT |
126 | {}, |
127 | }; | |
128 | ||
4f86d3a8 | 129 | |
2e906655 | 130 | /* |
131 | * Callers should disable interrupts before the call and enable | |
132 | * interrupts after return. | |
133 | */ | |
ddc081a1 VP |
134 | static void acpi_safe_halt(void) |
135 | { | |
136 | current_thread_info()->status &= ~TS_POLLING; | |
137 | /* | |
138 | * TS_POLLING-cleared state must be visible before we | |
139 | * test NEED_RESCHED: | |
140 | */ | |
141 | smp_mb(); | |
71e93d15 | 142 | if (!need_resched()) { |
ddc081a1 | 143 | safe_halt(); |
71e93d15 VP |
144 | local_irq_disable(); |
145 | } | |
ddc081a1 VP |
146 | current_thread_info()->status |= TS_POLLING; |
147 | } | |
148 | ||
169a0abb TG |
149 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
150 | ||
151 | /* | |
152 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
153 | * This seems to be a common problem on AMD boxen, but other vendors |
154 | * are affected too. We pick the most conservative approach: we assume | |
155 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 156 | */ |
7e275cc4 | 157 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
158 | struct acpi_processor_cx *cx) |
159 | { | |
160 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 161 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 162 | |
db954b58 VP |
163 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
164 | return; | |
165 | ||
02c68a02 | 166 | if (amd_e400_c1e_detected) |
87ad57ba SL |
167 | type = ACPI_STATE_C1; |
168 | ||
169a0abb TG |
169 | /* |
170 | * Check, if one of the previous states already marked the lapic | |
171 | * unstable | |
172 | */ | |
173 | if (pwr->timer_broadcast_on_state < state) | |
174 | return; | |
175 | ||
e585bef8 | 176 | if (cx->type >= type) |
296d93cd | 177 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
178 | } |
179 | ||
918aae42 | 180 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 181 | { |
f833bab8 | 182 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
183 | unsigned long reason; |
184 | ||
185 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
186 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
187 | ||
188 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
189 | } |
190 | ||
918aae42 HS |
191 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
192 | { | |
193 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
194 | (void *)pr, 1); | |
195 | } | |
196 | ||
e9e2cdb4 | 197 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 198 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
199 | struct acpi_processor_cx *cx, |
200 | int broadcast) | |
201 | { | |
e9e2cdb4 TG |
202 | int state = cx - pr->power.states; |
203 | ||
204 | if (state >= pr->power.timer_broadcast_on_state) { | |
205 | unsigned long reason; | |
206 | ||
207 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
208 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
209 | clockevents_notify(reason, &pr->id); | |
210 | } | |
169a0abb TG |
211 | } |
212 | ||
213 | #else | |
214 | ||
7e275cc4 | 215 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 216 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
217 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
218 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
219 | struct acpi_processor_cx *cx, |
220 | int broadcast) | |
221 | { | |
222 | } | |
169a0abb TG |
223 | |
224 | #endif | |
225 | ||
815ab0fd LB |
226 | static u32 saved_bm_rld; |
227 | ||
228 | static void acpi_idle_bm_rld_save(void) | |
229 | { | |
230 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
231 | } | |
232 | static void acpi_idle_bm_rld_restore(void) | |
233 | { | |
234 | u32 resumed_bm_rld; | |
235 | ||
236 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
237 | ||
238 | if (resumed_bm_rld != saved_bm_rld) | |
239 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
240 | } | |
b04e7bdb | 241 | |
e8110b64 | 242 | int acpi_processor_suspend(struct device *dev) |
b04e7bdb | 243 | { |
815ab0fd | 244 | acpi_idle_bm_rld_save(); |
b04e7bdb TG |
245 | return 0; |
246 | } | |
247 | ||
e8110b64 | 248 | int acpi_processor_resume(struct device *dev) |
b04e7bdb | 249 | { |
815ab0fd | 250 | acpi_idle_bm_rld_restore(); |
b04e7bdb TG |
251 | return 0; |
252 | } | |
253 | ||
592913ec | 254 | #if defined(CONFIG_X86) |
520daf72 | 255 | static void tsc_check_state(int state) |
ddb25f9a AK |
256 | { |
257 | switch (boot_cpu_data.x86_vendor) { | |
258 | case X86_VENDOR_AMD: | |
40fb1715 | 259 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
260 | /* |
261 | * AMD Fam10h TSC will tick in all | |
262 | * C/P/S0/S1 states when this bit is set. | |
263 | */ | |
40fb1715 | 264 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 265 | return; |
40fb1715 | 266 | |
ddb25f9a | 267 | /*FALL THROUGH*/ |
ddb25f9a | 268 | default: |
520daf72 LB |
269 | /* TSC could halt in idle, so notify users */ |
270 | if (state > ACPI_STATE_C1) | |
271 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
272 | } |
273 | } | |
520daf72 LB |
274 | #else |
275 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
276 | #endif |
277 | ||
4be44fcd | 278 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 279 | { |
1da177e4 LT |
280 | |
281 | if (!pr) | |
d550d98d | 282 | return -EINVAL; |
1da177e4 LT |
283 | |
284 | if (!pr->pblk) | |
d550d98d | 285 | return -ENODEV; |
1da177e4 | 286 | |
1da177e4 | 287 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
288 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
289 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
290 | ||
4c033552 VP |
291 | #ifndef CONFIG_HOTPLUG_CPU |
292 | /* | |
293 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 294 | * an SMP system. |
4c033552 | 295 | */ |
ad71860a | 296 | if ((num_online_cpus() > 1) && |
cee324b1 | 297 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 298 | return -ENODEV; |
4c033552 VP |
299 | #endif |
300 | ||
1da177e4 LT |
301 | /* determine C2 and C3 address from pblk */ |
302 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
303 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
304 | ||
305 | /* determine latencies from FADT */ | |
ba494bee BM |
306 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; |
307 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; | |
1da177e4 | 308 | |
5d76b6f6 LB |
309 | /* |
310 | * FADT specified C2 latency must be less than or equal to | |
311 | * 100 microseconds. | |
312 | */ | |
ba494bee | 313 | if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
5d76b6f6 | 314 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 315 | "C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency)); |
5d76b6f6 LB |
316 | /* invalidate C2 */ |
317 | pr->power.states[ACPI_STATE_C2].address = 0; | |
318 | } | |
319 | ||
a6d72c18 LB |
320 | /* |
321 | * FADT supplied C3 latency must be less than or equal to | |
322 | * 1000 microseconds. | |
323 | */ | |
ba494bee | 324 | if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
a6d72c18 | 325 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 326 | "C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency)); |
a6d72c18 LB |
327 | /* invalidate C3 */ |
328 | pr->power.states[ACPI_STATE_C3].address = 0; | |
329 | } | |
330 | ||
1da177e4 LT |
331 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
332 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
333 | pr->power.states[ACPI_STATE_C2].address, | |
334 | pr->power.states[ACPI_STATE_C3].address)); | |
335 | ||
d550d98d | 336 | return 0; |
1da177e4 LT |
337 | } |
338 | ||
991528d7 | 339 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 340 | { |
991528d7 VP |
341 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
342 | /* set the first C-State to C1 */ | |
343 | /* all processors need to support C1 */ | |
344 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
345 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 346 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
347 | } |
348 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 349 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 350 | return 0; |
acf05f4b VP |
351 | } |
352 | ||
4be44fcd | 353 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 354 | { |
4be44fcd | 355 | acpi_status status = 0; |
439913ff | 356 | u64 count; |
cf824788 | 357 | int current_count; |
4be44fcd LB |
358 | int i; |
359 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
360 | union acpi_object *cst; | |
1da177e4 | 361 | |
1da177e4 | 362 | |
1da177e4 | 363 | if (nocst) |
d550d98d | 364 | return -ENODEV; |
1da177e4 | 365 | |
991528d7 | 366 | current_count = 0; |
1da177e4 LT |
367 | |
368 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
369 | if (ACPI_FAILURE(status)) { | |
370 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 371 | return -ENODEV; |
4be44fcd | 372 | } |
1da177e4 | 373 | |
50dd0969 | 374 | cst = buffer.pointer; |
1da177e4 LT |
375 | |
376 | /* There must be at least 2 elements */ | |
377 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 378 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
379 | status = -EFAULT; |
380 | goto end; | |
381 | } | |
382 | ||
383 | count = cst->package.elements[0].integer.value; | |
384 | ||
385 | /* Validate number of power states. */ | |
386 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 387 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
388 | status = -EFAULT; |
389 | goto end; | |
390 | } | |
391 | ||
1da177e4 LT |
392 | /* Tell driver that at least _CST is supported. */ |
393 | pr->flags.has_cst = 1; | |
394 | ||
395 | for (i = 1; i <= count; i++) { | |
396 | union acpi_object *element; | |
397 | union acpi_object *obj; | |
398 | struct acpi_power_register *reg; | |
399 | struct acpi_processor_cx cx; | |
400 | ||
401 | memset(&cx, 0, sizeof(cx)); | |
402 | ||
50dd0969 | 403 | element = &(cst->package.elements[i]); |
1da177e4 LT |
404 | if (element->type != ACPI_TYPE_PACKAGE) |
405 | continue; | |
406 | ||
407 | if (element->package.count != 4) | |
408 | continue; | |
409 | ||
50dd0969 | 410 | obj = &(element->package.elements[0]); |
1da177e4 LT |
411 | |
412 | if (obj->type != ACPI_TYPE_BUFFER) | |
413 | continue; | |
414 | ||
4be44fcd | 415 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
416 | |
417 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 418 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
419 | continue; |
420 | ||
1da177e4 | 421 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 422 | obj = &(element->package.elements[1]); |
1da177e4 LT |
423 | if (obj->type != ACPI_TYPE_INTEGER) |
424 | continue; | |
425 | ||
426 | cx.type = obj->integer.value; | |
991528d7 VP |
427 | /* |
428 | * Some buggy BIOSes won't list C1 in _CST - | |
429 | * Let acpi_processor_get_power_info_default() handle them later | |
430 | */ | |
431 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
432 | current_count++; | |
433 | ||
434 | cx.address = reg->address; | |
435 | cx.index = current_count + 1; | |
436 | ||
bc71bec9 | 437 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
438 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
439 | if (acpi_processor_ffh_cstate_probe | |
440 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 441 | cx.entry_method = ACPI_CSTATE_FFH; |
442 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
443 | /* |
444 | * C1 is a special case where FIXED_HARDWARE | |
445 | * can be handled in non-MWAIT way as well. | |
446 | * In that case, save this _CST entry info. | |
991528d7 VP |
447 | * Otherwise, ignore this info and continue. |
448 | */ | |
bc71bec9 | 449 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 450 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 451 | } else { |
991528d7 VP |
452 | continue; |
453 | } | |
da5e09a1 | 454 | if (cx.type == ACPI_STATE_C1 && |
d1896049 | 455 | (boot_option_idle_override == IDLE_NOMWAIT)) { |
c1e3b377 ZY |
456 | /* |
457 | * In most cases the C1 space_id obtained from | |
458 | * _CST object is FIXED_HARDWARE access mode. | |
459 | * But when the option of idle=halt is added, | |
460 | * the entry_method type should be changed from | |
461 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
462 | * When the option of idle=nomwait is added, |
463 | * the C1 entry_method type should be | |
464 | * CSTATE_HALT. | |
c1e3b377 ZY |
465 | */ |
466 | cx.entry_method = ACPI_CSTATE_HALT; | |
467 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
468 | } | |
4fcb2fcd VP |
469 | } else { |
470 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
471 | cx.address); | |
991528d7 | 472 | } |
1da177e4 | 473 | |
0fda6b40 VP |
474 | if (cx.type == ACPI_STATE_C1) { |
475 | cx.valid = 1; | |
476 | } | |
4fcb2fcd | 477 | |
50dd0969 | 478 | obj = &(element->package.elements[2]); |
1da177e4 LT |
479 | if (obj->type != ACPI_TYPE_INTEGER) |
480 | continue; | |
481 | ||
482 | cx.latency = obj->integer.value; | |
483 | ||
50dd0969 | 484 | obj = &(element->package.elements[3]); |
1da177e4 LT |
485 | if (obj->type != ACPI_TYPE_INTEGER) |
486 | continue; | |
487 | ||
cf824788 JM |
488 | current_count++; |
489 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
490 | ||
491 | /* | |
492 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
493 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
494 | */ | |
495 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
496 | printk(KERN_WARNING | |
497 | "Limiting number of power states to max (%d)\n", | |
498 | ACPI_PROCESSOR_MAX_POWER); | |
499 | printk(KERN_WARNING | |
500 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
501 | break; | |
502 | } | |
1da177e4 LT |
503 | } |
504 | ||
4be44fcd | 505 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 506 | current_count)); |
1da177e4 LT |
507 | |
508 | /* Validate number of power states discovered */ | |
cf824788 | 509 | if (current_count < 2) |
6d93c648 | 510 | status = -EFAULT; |
1da177e4 | 511 | |
4be44fcd | 512 | end: |
02438d87 | 513 | kfree(buffer.pointer); |
1da177e4 | 514 | |
d550d98d | 515 | return status; |
1da177e4 LT |
516 | } |
517 | ||
4be44fcd LB |
518 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
519 | struct acpi_processor_cx *cx) | |
1da177e4 | 520 | { |
ee1ca48f PV |
521 | static int bm_check_flag = -1; |
522 | static int bm_control_flag = -1; | |
02df8b93 | 523 | |
1da177e4 LT |
524 | |
525 | if (!cx->address) | |
d550d98d | 526 | return; |
1da177e4 | 527 | |
1da177e4 LT |
528 | /* |
529 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
530 | * DMA transfers are used by any ISA device to avoid livelock. | |
531 | * Note that we could disable Type-F DMA (as recommended by | |
532 | * the erratum), but this is known to disrupt certain ISA | |
533 | * devices thus we take the conservative approach. | |
534 | */ | |
535 | else if (errata.piix4.fdma) { | |
536 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 537 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 538 | return; |
1da177e4 LT |
539 | } |
540 | ||
02df8b93 | 541 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 542 | if (bm_check_flag == -1) { |
02df8b93 VP |
543 | /* Determine whether bm_check is needed based on CPU */ |
544 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
545 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 546 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
547 | } else { |
548 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 549 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
550 | } |
551 | ||
552 | if (pr->flags.bm_check) { | |
02df8b93 | 553 | if (!pr->flags.bm_control) { |
ed3110ef VP |
554 | if (pr->flags.has_cst != 1) { |
555 | /* bus mastering control is necessary */ | |
556 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
557 | "C3 support requires BM control\n")); | |
558 | return; | |
559 | } else { | |
560 | /* Here we enter C3 without bus mastering */ | |
561 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
562 | "C3 support without BM control\n")); | |
563 | } | |
02df8b93 VP |
564 | } |
565 | } else { | |
02df8b93 VP |
566 | /* |
567 | * WBINVD should be set in fadt, for C3 state to be | |
568 | * supported on when bm_check is not required. | |
569 | */ | |
cee324b1 | 570 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 571 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
572 | "Cache invalidation should work properly" |
573 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 574 | return; |
02df8b93 | 575 | } |
02df8b93 VP |
576 | } |
577 | ||
1da177e4 LT |
578 | /* |
579 | * Otherwise we've met all of our C3 requirements. | |
580 | * Normalize the C3 latency to expidite policy. Enable | |
581 | * checking of bus mastering status (bm_check) so we can | |
582 | * use this in our C3 policy | |
583 | */ | |
584 | cx->valid = 1; | |
4f86d3a8 | 585 | |
31878dd8 LB |
586 | /* |
587 | * On older chipsets, BM_RLD needs to be set | |
588 | * in order for Bus Master activity to wake the | |
589 | * system from C3. Newer chipsets handle DMA | |
590 | * during C3 automatically and BM_RLD is a NOP. | |
591 | * In either case, the proper way to | |
592 | * handle BM_RLD is to set it and leave it set. | |
593 | */ | |
50ffba1b | 594 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 595 | |
d550d98d | 596 | return; |
1da177e4 LT |
597 | } |
598 | ||
1da177e4 LT |
599 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
600 | { | |
601 | unsigned int i; | |
602 | unsigned int working = 0; | |
6eb0a0fd | 603 | |
169a0abb | 604 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 605 | |
a0bf284b | 606 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
607 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
608 | ||
609 | switch (cx->type) { | |
610 | case ACPI_STATE_C1: | |
611 | cx->valid = 1; | |
612 | break; | |
613 | ||
614 | case ACPI_STATE_C2: | |
d22edd29 LB |
615 | if (!cx->address) |
616 | break; | |
617 | cx->valid = 1; | |
1da177e4 LT |
618 | break; |
619 | ||
620 | case ACPI_STATE_C3: | |
621 | acpi_processor_power_verify_c3(pr, cx); | |
622 | break; | |
623 | } | |
7e275cc4 LB |
624 | if (!cx->valid) |
625 | continue; | |
1da177e4 | 626 | |
7e275cc4 LB |
627 | lapic_timer_check_state(i, pr, cx); |
628 | tsc_check_state(cx->type); | |
629 | working++; | |
1da177e4 | 630 | } |
bd663347 | 631 | |
918aae42 | 632 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
633 | |
634 | return (working); | |
635 | } | |
636 | ||
4be44fcd | 637 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
638 | { |
639 | unsigned int i; | |
640 | int result; | |
641 | ||
1da177e4 LT |
642 | |
643 | /* NOTE: the idle thread may not be running while calling | |
644 | * this function */ | |
645 | ||
991528d7 VP |
646 | /* Zero initialize all the C-states info. */ |
647 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
648 | ||
1da177e4 | 649 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 650 | if (result == -ENODEV) |
c5a114f1 | 651 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 652 | |
991528d7 VP |
653 | if (result) |
654 | return result; | |
655 | ||
656 | acpi_processor_get_power_info_default(pr); | |
657 | ||
cf824788 | 658 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 659 | |
1da177e4 LT |
660 | /* |
661 | * if one state of type C2 or C3 is available, mark this | |
662 | * CPU as being "idle manageable" | |
663 | */ | |
664 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 665 | if (pr->power.states[i].valid) { |
1da177e4 | 666 | pr->power.count = i; |
2203d6ed LT |
667 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
668 | pr->flags.power = 1; | |
acf05f4b | 669 | } |
1da177e4 LT |
670 | } |
671 | ||
d550d98d | 672 | return 0; |
1da177e4 LT |
673 | } |
674 | ||
4f86d3a8 LB |
675 | /** |
676 | * acpi_idle_bm_check - checks if bus master activity was detected | |
677 | */ | |
678 | static int acpi_idle_bm_check(void) | |
679 | { | |
680 | u32 bm_status = 0; | |
681 | ||
d3e7e99f LB |
682 | if (bm_check_disable) |
683 | return 0; | |
684 | ||
50ffba1b | 685 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 686 | if (bm_status) |
50ffba1b | 687 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
688 | /* |
689 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
690 | * the true state of bus mastering activity; forcing us to | |
691 | * manually check the BMIDEA bit of each IDE channel. | |
692 | */ | |
693 | else if (errata.piix4.bmisx) { | |
694 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
695 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
696 | bm_status = 1; | |
697 | } | |
698 | return bm_status; | |
699 | } | |
700 | ||
4f86d3a8 LB |
701 | /** |
702 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
703 | * @cx: cstate data | |
bc71bec9 | 704 | * |
705 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
706 | */ |
707 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
708 | { | |
dcf30997 SR |
709 | /* Don't trace irqs off for idle */ |
710 | stop_critical_timings(); | |
bc71bec9 | 711 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
712 | /* Call into architectural FFH based C-state */ |
713 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 714 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
715 | acpi_safe_halt(); | |
4f86d3a8 | 716 | } else { |
4f86d3a8 LB |
717 | /* IO port based C-state */ |
718 | inb(cx->address); | |
719 | /* Dummy wait op - must do something useless after P_LVL2 read | |
720 | because chipsets cannot guarantee that STPCLK# signal | |
721 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 722 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 723 | } |
dcf30997 | 724 | start_critical_timings(); |
4f86d3a8 LB |
725 | } |
726 | ||
727 | /** | |
728 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
729 | * @dev: the target CPU | |
46bcfad7 | 730 | * @drv: cpuidle driver containing cpuidle state info |
e978aa7d | 731 | * @index: index of target state |
4f86d3a8 LB |
732 | * |
733 | * This is equivalent to the HALT instruction. | |
734 | */ | |
735 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
46bcfad7 | 736 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
737 | { |
738 | struct acpi_processor *pr; | |
4202735e DD |
739 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
740 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
9b12e18c | 741 | |
4a6f4fe8 | 742 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
743 | |
744 | if (unlikely(!pr)) | |
e978aa7d | 745 | return -EINVAL; |
4f86d3a8 | 746 | |
7e275cc4 | 747 | lapic_timer_state_broadcast(pr, cx, 1); |
bc71bec9 | 748 | acpi_idle_do_entry(cx); |
e978aa7d | 749 | |
7e275cc4 | 750 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 751 | |
e978aa7d | 752 | return index; |
4f86d3a8 LB |
753 | } |
754 | ||
1a022e3f BO |
755 | |
756 | /** | |
757 | * acpi_idle_play_dead - enters an ACPI state for long-term idle (i.e. off-lining) | |
758 | * @dev: the target CPU | |
759 | * @index: the index of suggested state | |
760 | */ | |
761 | static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) | |
762 | { | |
763 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; | |
764 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
765 | ||
766 | ACPI_FLUSH_CPU_CACHE(); | |
767 | ||
768 | while (1) { | |
769 | ||
770 | if (cx->entry_method == ACPI_CSTATE_HALT) | |
54f70077 | 771 | safe_halt(); |
1a022e3f BO |
772 | else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { |
773 | inb(cx->address); | |
774 | /* See comment in acpi_idle_do_entry() */ | |
775 | inl(acpi_gbl_FADT.xpm_timer_block.address); | |
776 | } else | |
777 | return -ENODEV; | |
778 | } | |
779 | ||
780 | /* Never reached */ | |
781 | return 0; | |
782 | } | |
783 | ||
4f86d3a8 LB |
784 | /** |
785 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
786 | * @dev: the target CPU | |
46bcfad7 | 787 | * @drv: cpuidle driver with cpuidle state information |
e978aa7d | 788 | * @index: the index of suggested state |
4f86d3a8 LB |
789 | */ |
790 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
46bcfad7 | 791 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
792 | { |
793 | struct acpi_processor *pr; | |
4202735e DD |
794 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
795 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
50629118 | 796 | |
4a6f4fe8 | 797 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
798 | |
799 | if (unlikely(!pr)) | |
e978aa7d | 800 | return -EINVAL; |
e196441b | 801 | |
d306ebc2 PV |
802 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
803 | current_thread_info()->status &= ~TS_POLLING; | |
804 | /* | |
805 | * TS_POLLING-cleared state must be visible before we test | |
806 | * NEED_RESCHED: | |
807 | */ | |
808 | smp_mb(); | |
4f86d3a8 | 809 | |
02cf4f98 LB |
810 | if (unlikely(need_resched())) { |
811 | current_thread_info()->status |= TS_POLLING; | |
e978aa7d | 812 | return -EINVAL; |
02cf4f98 | 813 | } |
4f86d3a8 LB |
814 | } |
815 | ||
e17bcb43 TG |
816 | /* |
817 | * Must be done before busmaster disable as we might need to | |
818 | * access HPET ! | |
819 | */ | |
7e275cc4 | 820 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 821 | |
4f86d3a8 LB |
822 | if (cx->type == ACPI_STATE_C3) |
823 | ACPI_FLUSH_CPU_CACHE(); | |
824 | ||
50629118 VP |
825 | /* Tell the scheduler that we are going deep-idle: */ |
826 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 827 | acpi_idle_do_entry(cx); |
4f86d3a8 | 828 | |
a474a515 | 829 | sched_clock_idle_wakeup_event(0); |
e978aa7d | 830 | |
02cf4f98 LB |
831 | if (cx->entry_method != ACPI_CSTATE_FFH) |
832 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 | 833 | |
7e275cc4 | 834 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 835 | return index; |
4f86d3a8 LB |
836 | } |
837 | ||
838 | static int c3_cpu_count; | |
e12f65f7 | 839 | static DEFINE_RAW_SPINLOCK(c3_lock); |
4f86d3a8 LB |
840 | |
841 | /** | |
842 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
843 | * @dev: the target CPU | |
46bcfad7 | 844 | * @drv: cpuidle driver containing state data |
e978aa7d | 845 | * @index: the index of suggested state |
4f86d3a8 LB |
846 | * |
847 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
848 | */ | |
849 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
46bcfad7 | 850 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
851 | { |
852 | struct acpi_processor *pr; | |
4202735e DD |
853 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
854 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
50629118 | 855 | |
4a6f4fe8 | 856 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
857 | |
858 | if (unlikely(!pr)) | |
e978aa7d | 859 | return -EINVAL; |
4f86d3a8 | 860 | |
718be4aa | 861 | if (!cx->bm_sts_skip && acpi_idle_bm_check()) { |
46bcfad7 DD |
862 | if (drv->safe_state_index >= 0) { |
863 | return drv->states[drv->safe_state_index].enter(dev, | |
864 | drv, drv->safe_state_index); | |
ddc081a1 | 865 | } else { |
8651f97b | 866 | acpi_safe_halt(); |
75cc5235 | 867 | return -EBUSY; |
ddc081a1 VP |
868 | } |
869 | } | |
870 | ||
d306ebc2 PV |
871 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
872 | current_thread_info()->status &= ~TS_POLLING; | |
873 | /* | |
874 | * TS_POLLING-cleared state must be visible before we test | |
875 | * NEED_RESCHED: | |
876 | */ | |
877 | smp_mb(); | |
4f86d3a8 | 878 | |
02cf4f98 LB |
879 | if (unlikely(need_resched())) { |
880 | current_thread_info()->status |= TS_POLLING; | |
e978aa7d | 881 | return -EINVAL; |
02cf4f98 | 882 | } |
4f86d3a8 LB |
883 | } |
884 | ||
996520c1 VP |
885 | acpi_unlazy_tlb(smp_processor_id()); |
886 | ||
50629118 VP |
887 | /* Tell the scheduler that we are going deep-idle: */ |
888 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
889 | /* |
890 | * Must be done before busmaster disable as we might need to | |
891 | * access HPET ! | |
892 | */ | |
7e275cc4 | 893 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 894 | |
ddc081a1 VP |
895 | /* |
896 | * disable bus master | |
897 | * bm_check implies we need ARB_DIS | |
898 | * !bm_check implies we need cache flush | |
899 | * bm_control implies whether we can do ARB_DIS | |
900 | * | |
901 | * That leaves a case where bm_check is set and bm_control is | |
902 | * not set. In that case we cannot do much, we enter C3 | |
903 | * without doing anything. | |
904 | */ | |
905 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 906 | raw_spin_lock(&c3_lock); |
4f86d3a8 LB |
907 | c3_cpu_count++; |
908 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
909 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 910 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
e12f65f7 | 911 | raw_spin_unlock(&c3_lock); |
ddc081a1 VP |
912 | } else if (!pr->flags.bm_check) { |
913 | ACPI_FLUSH_CPU_CACHE(); | |
914 | } | |
4f86d3a8 | 915 | |
ddc081a1 | 916 | acpi_idle_do_entry(cx); |
4f86d3a8 | 917 | |
ddc081a1 VP |
918 | /* Re-enable bus master arbitration */ |
919 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 920 | raw_spin_lock(&c3_lock); |
50ffba1b | 921 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 | 922 | c3_cpu_count--; |
e12f65f7 | 923 | raw_spin_unlock(&c3_lock); |
4f86d3a8 | 924 | } |
e978aa7d | 925 | |
a474a515 | 926 | sched_clock_idle_wakeup_event(0); |
4f86d3a8 | 927 | |
02cf4f98 LB |
928 | if (cx->entry_method != ACPI_CSTATE_FFH) |
929 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 | 930 | |
7e275cc4 | 931 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 932 | return index; |
4f86d3a8 LB |
933 | } |
934 | ||
935 | struct cpuidle_driver acpi_idle_driver = { | |
936 | .name = "acpi_idle", | |
937 | .owner = THIS_MODULE, | |
a474a515 | 938 | .en_core_tk_irqen = 1, |
4f86d3a8 LB |
939 | }; |
940 | ||
941 | /** | |
46bcfad7 DD |
942 | * acpi_processor_setup_cpuidle_cx - prepares and configures CPUIDLE |
943 | * device i.e. per-cpu data | |
944 | * | |
4f86d3a8 LB |
945 | * @pr: the ACPI processor |
946 | */ | |
46bcfad7 | 947 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr) |
4f86d3a8 | 948 | { |
9a0b8415 | 949 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 | 950 | struct acpi_processor_cx *cx; |
4202735e | 951 | struct cpuidle_state_usage *state_usage; |
3d339dcb | 952 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 LB |
953 | |
954 | if (!pr->flags.power_setup_done) | |
955 | return -EINVAL; | |
956 | ||
957 | if (pr->flags.power == 0) { | |
958 | return -EINVAL; | |
959 | } | |
960 | ||
dcb84f33 | 961 | dev->cpu = pr->id; |
4fcb2fcd | 962 | |
615dfd93 LB |
963 | if (max_cstate == 0) |
964 | max_cstate = 1; | |
965 | ||
4f86d3a8 LB |
966 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
967 | cx = &pr->power.states[i]; | |
4202735e | 968 | state_usage = &dev->states_usage[count]; |
4f86d3a8 LB |
969 | |
970 | if (!cx->valid) | |
971 | continue; | |
972 | ||
973 | #ifdef CONFIG_HOTPLUG_CPU | |
974 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
975 | !pr->flags.has_cst && | |
976 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
977 | continue; | |
1fec74a9 | 978 | #endif |
46bcfad7 | 979 | |
4202735e | 980 | cpuidle_set_statedata(state_usage, cx); |
4f86d3a8 | 981 | |
46bcfad7 DD |
982 | count++; |
983 | if (count == CPUIDLE_STATE_MAX) | |
984 | break; | |
985 | } | |
986 | ||
987 | dev->state_count = count; | |
988 | ||
989 | if (!count) | |
990 | return -EINVAL; | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | /** | |
996 | * acpi_processor_setup_cpuidle states- prepares and configures cpuidle | |
997 | * global state data i.e. idle routines | |
998 | * | |
999 | * @pr: the ACPI processor | |
1000 | */ | |
1001 | static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr) | |
1002 | { | |
1003 | int i, count = CPUIDLE_DRIVER_STATE_START; | |
1004 | struct acpi_processor_cx *cx; | |
1005 | struct cpuidle_state *state; | |
1006 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
1007 | ||
1008 | if (!pr->flags.power_setup_done) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | if (pr->flags.power == 0) | |
1012 | return -EINVAL; | |
1013 | ||
1014 | drv->safe_state_index = -1; | |
4fcb2fcd | 1015 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
46bcfad7 DD |
1016 | drv->states[i].name[0] = '\0'; |
1017 | drv->states[i].desc[0] = '\0'; | |
4fcb2fcd VP |
1018 | } |
1019 | ||
615dfd93 LB |
1020 | if (max_cstate == 0) |
1021 | max_cstate = 1; | |
1022 | ||
4f86d3a8 LB |
1023 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1024 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
1025 | |
1026 | if (!cx->valid) | |
1027 | continue; | |
1028 | ||
1029 | #ifdef CONFIG_HOTPLUG_CPU | |
1030 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1031 | !pr->flags.has_cst && | |
1032 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1033 | continue; | |
1fec74a9 | 1034 | #endif |
4f86d3a8 | 1035 | |
46bcfad7 | 1036 | state = &drv->states[count]; |
4f86d3a8 | 1037 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
4fcb2fcd | 1038 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1039 | state->exit_latency = cx->latency; |
4963f620 | 1040 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1041 | |
1042 | state->flags = 0; | |
1043 | switch (cx->type) { | |
1044 | case ACPI_STATE_C1: | |
8e92b660 VP |
1045 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1046 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1047 | ||
4f86d3a8 | 1048 | state->enter = acpi_idle_enter_c1; |
1a022e3f | 1049 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1050 | drv->safe_state_index = count; |
4f86d3a8 LB |
1051 | break; |
1052 | ||
1053 | case ACPI_STATE_C2: | |
4f86d3a8 LB |
1054 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1055 | state->enter = acpi_idle_enter_simple; | |
1a022e3f | 1056 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1057 | drv->safe_state_index = count; |
4f86d3a8 LB |
1058 | break; |
1059 | ||
1060 | case ACPI_STATE_C3: | |
4f86d3a8 | 1061 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
4f86d3a8 LB |
1062 | state->enter = pr->flags.bm_check ? |
1063 | acpi_idle_enter_bm : | |
1064 | acpi_idle_enter_simple; | |
1065 | break; | |
1066 | } | |
1067 | ||
1068 | count++; | |
9a0b8415 | 1069 | if (count == CPUIDLE_STATE_MAX) |
1070 | break; | |
4f86d3a8 LB |
1071 | } |
1072 | ||
46bcfad7 | 1073 | drv->state_count = count; |
4f86d3a8 LB |
1074 | |
1075 | if (!count) | |
1076 | return -EINVAL; | |
1077 | ||
4f86d3a8 LB |
1078 | return 0; |
1079 | } | |
1080 | ||
46bcfad7 | 1081 | int acpi_processor_hotplug(struct acpi_processor *pr) |
4f86d3a8 | 1082 | { |
dcb84f33 | 1083 | int ret = 0; |
e8b1b59d | 1084 | struct cpuidle_device *dev; |
4f86d3a8 | 1085 | |
d1896049 | 1086 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1087 | return 0; |
1088 | ||
4f86d3a8 LB |
1089 | if (!pr) |
1090 | return -EINVAL; | |
1091 | ||
1092 | if (nocst) { | |
1093 | return -ENODEV; | |
1094 | } | |
1095 | ||
1096 | if (!pr->flags.power_setup_done) | |
1097 | return -ENODEV; | |
1098 | ||
e8b1b59d | 1099 | dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 | 1100 | cpuidle_pause_and_lock(); |
3d339dcb | 1101 | cpuidle_disable_device(dev); |
4f86d3a8 | 1102 | acpi_processor_get_power_info(pr); |
dcb84f33 | 1103 | if (pr->flags.power) { |
46bcfad7 | 1104 | acpi_processor_setup_cpuidle_cx(pr); |
3d339dcb | 1105 | ret = cpuidle_enable_device(dev); |
dcb84f33 | 1106 | } |
4f86d3a8 LB |
1107 | cpuidle_resume_and_unlock(); |
1108 | ||
1109 | return ret; | |
1110 | } | |
1111 | ||
46bcfad7 DD |
1112 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1113 | { | |
1114 | int cpu; | |
1115 | struct acpi_processor *_pr; | |
3d339dcb | 1116 | struct cpuidle_device *dev; |
46bcfad7 DD |
1117 | |
1118 | if (disabled_by_idle_boot_param()) | |
1119 | return 0; | |
1120 | ||
1121 | if (!pr) | |
1122 | return -EINVAL; | |
1123 | ||
1124 | if (nocst) | |
1125 | return -ENODEV; | |
1126 | ||
1127 | if (!pr->flags.power_setup_done) | |
1128 | return -ENODEV; | |
1129 | ||
1130 | /* | |
1131 | * FIXME: Design the ACPI notification to make it once per | |
1132 | * system instead of once per-cpu. This condition is a hack | |
1133 | * to make the code that updates C-States be called once. | |
1134 | */ | |
1135 | ||
9505626d | 1136 | if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) { |
46bcfad7 DD |
1137 | |
1138 | cpuidle_pause_and_lock(); | |
1139 | /* Protect against cpu-hotplug */ | |
1140 | get_online_cpus(); | |
1141 | ||
1142 | /* Disable all cpuidle devices */ | |
1143 | for_each_online_cpu(cpu) { | |
1144 | _pr = per_cpu(processors, cpu); | |
1145 | if (!_pr || !_pr->flags.power_setup_done) | |
1146 | continue; | |
3d339dcb DL |
1147 | dev = per_cpu(acpi_cpuidle_device, cpu); |
1148 | cpuidle_disable_device(dev); | |
46bcfad7 DD |
1149 | } |
1150 | ||
1151 | /* Populate Updated C-state information */ | |
1152 | acpi_processor_setup_cpuidle_states(pr); | |
1153 | ||
1154 | /* Enable all cpuidle devices */ | |
1155 | for_each_online_cpu(cpu) { | |
1156 | _pr = per_cpu(processors, cpu); | |
1157 | if (!_pr || !_pr->flags.power_setup_done) | |
1158 | continue; | |
1159 | acpi_processor_get_power_info(_pr); | |
1160 | if (_pr->flags.power) { | |
1161 | acpi_processor_setup_cpuidle_cx(_pr); | |
3d339dcb DL |
1162 | dev = per_cpu(acpi_cpuidle_device, cpu); |
1163 | cpuidle_enable_device(dev); | |
46bcfad7 DD |
1164 | } |
1165 | } | |
1166 | put_online_cpus(); | |
1167 | cpuidle_resume_and_unlock(); | |
1168 | } | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static int acpi_processor_registered; | |
1174 | ||
38a991b6 | 1175 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr) |
1da177e4 | 1176 | { |
4be44fcd | 1177 | acpi_status status = 0; |
46bcfad7 | 1178 | int retval; |
3d339dcb | 1179 | struct cpuidle_device *dev; |
b6835052 | 1180 | static int first_run; |
1da177e4 | 1181 | |
d1896049 | 1182 | if (disabled_by_idle_boot_param()) |
36a91358 | 1183 | return 0; |
1da177e4 LT |
1184 | |
1185 | if (!first_run) { | |
1186 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1187 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1188 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1189 | printk(KERN_NOTICE |
1190 | "ACPI: processor limited to max C-state %d\n", | |
1191 | max_cstate); | |
1da177e4 LT |
1192 | first_run++; |
1193 | } | |
1194 | ||
02df8b93 | 1195 | if (!pr) |
d550d98d | 1196 | return -EINVAL; |
02df8b93 | 1197 | |
cee324b1 | 1198 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1199 | status = |
cee324b1 | 1200 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1201 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1202 | ACPI_EXCEPTION((AE_INFO, status, |
1203 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1204 | } |
1205 | } | |
1206 | ||
1207 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1208 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1209 | |
1210 | /* | |
1211 | * Install the idle handler if processor power management is supported. | |
1212 | * Note that we use previously set idle handler will be used on | |
1213 | * platforms that only support C1. | |
1214 | */ | |
36a91358 | 1215 | if (pr->flags.power) { |
46bcfad7 DD |
1216 | /* Register acpi_idle_driver if not already registered */ |
1217 | if (!acpi_processor_registered) { | |
1218 | acpi_processor_setup_cpuidle_states(pr); | |
1219 | retval = cpuidle_register_driver(&acpi_idle_driver); | |
1220 | if (retval) | |
1221 | return retval; | |
1222 | printk(KERN_DEBUG "ACPI: %s registered with cpuidle\n", | |
1223 | acpi_idle_driver.name); | |
1224 | } | |
3d339dcb DL |
1225 | |
1226 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1227 | if (!dev) | |
1228 | return -ENOMEM; | |
1229 | per_cpu(acpi_cpuidle_device, pr->id) = dev; | |
1230 | ||
1231 | acpi_processor_setup_cpuidle_cx(pr); | |
1232 | ||
46bcfad7 DD |
1233 | /* Register per-cpu cpuidle_device. Cpuidle driver |
1234 | * must already be registered before registering device | |
1235 | */ | |
3d339dcb | 1236 | retval = cpuidle_register_device(dev); |
46bcfad7 DD |
1237 | if (retval) { |
1238 | if (acpi_processor_registered == 0) | |
1239 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1240 | return retval; | |
1241 | } | |
1242 | acpi_processor_registered++; | |
1da177e4 | 1243 | } |
d550d98d | 1244 | return 0; |
1da177e4 LT |
1245 | } |
1246 | ||
38a991b6 | 1247 | int acpi_processor_power_exit(struct acpi_processor *pr) |
1da177e4 | 1248 | { |
3d339dcb DL |
1249 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
1250 | ||
d1896049 | 1251 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1252 | return 0; |
1253 | ||
46bcfad7 | 1254 | if (pr->flags.power) { |
3d339dcb | 1255 | cpuidle_unregister_device(dev); |
46bcfad7 DD |
1256 | acpi_processor_registered--; |
1257 | if (acpi_processor_registered == 0) | |
1258 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1259 | } | |
1da177e4 | 1260 | |
46bcfad7 | 1261 | pr->flags.power_setup_done = 0; |
d550d98d | 1262 | return 0; |
1da177e4 | 1263 | } |