Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * processor_idle - idle state submodule to the ACPI processor driver | |
4 | * | |
5 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
6 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 7 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
8 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
9 | * - Added processor hotplug support | |
02df8b93 VP |
10 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
11 | * - Added support for C3 on SMP | |
1da177e4 | 12 | */ |
b6ec26fb | 13 | #define pr_fmt(fmt) "ACPI: " fmt |
1da177e4 | 14 | |
1da177e4 | 15 | #include <linux/module.h> |
1da177e4 LT |
16 | #include <linux/acpi.h> |
17 | #include <linux/dmi.h> | |
e2668fb5 | 18 | #include <linux/sched.h> /* need_resched() */ |
ee41eebf | 19 | #include <linux/tick.h> |
4f86d3a8 | 20 | #include <linux/cpuidle.h> |
6727ad9e | 21 | #include <linux/cpu.h> |
8b48463f | 22 | #include <acpi/processor.h> |
1da177e4 | 23 | |
3434933b TG |
24 | /* |
25 | * Include the apic definitions for x86 to have the APIC timer related defines | |
26 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
27 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
28 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
29 | */ | |
30 | #ifdef CONFIG_X86 | |
31 | #include <asm/apic.h> | |
32 | #endif | |
33 | ||
1da177e4 | 34 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 35 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 36 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 37 | |
dc2251bf RW |
38 | #define ACPI_IDLE_STATE_START (IS_ENABLED(CONFIG_ARCH_HAS_CPU_RELAX) ? 1 : 0) |
39 | ||
4f86d3a8 LB |
40 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
41 | module_param(max_cstate, uint, 0000); | |
b6835052 | 42 | static unsigned int nocst __read_mostly; |
1da177e4 | 43 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
44 | static int bm_check_disable __read_mostly; |
45 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 46 | |
25de5718 | 47 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 48 | module_param(latency_factor, uint, 0644); |
1da177e4 | 49 | |
3d339dcb DL |
50 | static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); |
51 | ||
35ae7133 SH |
52 | struct cpuidle_driver acpi_idle_driver = { |
53 | .name = "acpi_idle", | |
54 | .owner = THIS_MODULE, | |
55 | }; | |
56 | ||
57 | #ifdef CONFIG_ACPI_PROCESSOR_CSTATE | |
25528213 PZ |
58 | static |
59 | DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], acpi_cstate); | |
ac3ebafa | 60 | |
d1896049 TR |
61 | static int disabled_by_idle_boot_param(void) |
62 | { | |
63 | return boot_option_idle_override == IDLE_POLL || | |
d1896049 TR |
64 | boot_option_idle_override == IDLE_HALT; |
65 | } | |
66 | ||
1da177e4 LT |
67 | /* |
68 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
69 | * For now disable this. Probably a bug somewhere else. | |
70 | * | |
71 | * To skip this limit, boot/load with a large max_cstate limit. | |
72 | */ | |
1855256c | 73 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
74 | { |
75 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
76 | return 0; | |
77 | ||
b6ec26fb SH |
78 | pr_notice("%s detected - limiting to C%ld max_cstate." |
79 | " Override with \"processor.max_cstate=%d\"\n", id->ident, | |
80 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 81 | |
3d35600a | 82 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
83 | |
84 | return 0; | |
85 | } | |
86 | ||
b0346688 | 87 | static const struct dmi_system_id processor_power_dmi_table[] = { |
876c184b TR |
88 | { set_max_cstate, "Clevo 5600D", { |
89 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
90 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 91 | (void *)2}, |
370d5cd8 AV |
92 | { set_max_cstate, "Pavilion zv5000", { |
93 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
94 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
95 | (void *)1}, | |
96 | { set_max_cstate, "Asus L8400B", { | |
97 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
98 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
99 | (void *)1}, | |
1da177e4 LT |
100 | {}, |
101 | }; | |
102 | ||
4f86d3a8 | 103 | |
2e906655 | 104 | /* |
105 | * Callers should disable interrupts before the call and enable | |
106 | * interrupts after return. | |
107 | */ | |
6727ad9e | 108 | static void __cpuidle acpi_safe_halt(void) |
ddc081a1 | 109 | { |
ea811747 | 110 | if (!tif_need_resched()) { |
ddc081a1 | 111 | safe_halt(); |
71e93d15 VP |
112 | local_irq_disable(); |
113 | } | |
ddc081a1 VP |
114 | } |
115 | ||
169a0abb TG |
116 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
117 | ||
118 | /* | |
119 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
120 | * This seems to be a common problem on AMD boxen, but other vendors |
121 | * are affected too. We pick the most conservative approach: we assume | |
122 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 123 | */ |
7e275cc4 | 124 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
125 | struct acpi_processor_cx *cx) |
126 | { | |
127 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 128 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 129 | |
db954b58 VP |
130 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
131 | return; | |
132 | ||
07c94a38 | 133 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) |
87ad57ba SL |
134 | type = ACPI_STATE_C1; |
135 | ||
169a0abb TG |
136 | /* |
137 | * Check, if one of the previous states already marked the lapic | |
138 | * unstable | |
139 | */ | |
140 | if (pwr->timer_broadcast_on_state < state) | |
141 | return; | |
142 | ||
e585bef8 | 143 | if (cx->type >= type) |
296d93cd | 144 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
145 | } |
146 | ||
918aae42 | 147 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 148 | { |
f833bab8 | 149 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 | 150 | |
ee41eebf TG |
151 | if (pr->power.timer_broadcast_on_state < INT_MAX) |
152 | tick_broadcast_enable(); | |
153 | else | |
154 | tick_broadcast_disable(); | |
e9e2cdb4 TG |
155 | } |
156 | ||
918aae42 HS |
157 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
158 | { | |
159 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
160 | (void *)pr, 1); | |
161 | } | |
162 | ||
e9e2cdb4 | 163 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 164 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
165 | struct acpi_processor_cx *cx, |
166 | int broadcast) | |
167 | { | |
e9e2cdb4 TG |
168 | int state = cx - pr->power.states; |
169 | ||
170 | if (state >= pr->power.timer_broadcast_on_state) { | |
7815701c TG |
171 | if (broadcast) |
172 | tick_broadcast_enter(); | |
173 | else | |
174 | tick_broadcast_exit(); | |
e9e2cdb4 | 175 | } |
169a0abb TG |
176 | } |
177 | ||
178 | #else | |
179 | ||
7e275cc4 | 180 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 181 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
182 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
183 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
184 | struct acpi_processor_cx *cx, |
185 | int broadcast) | |
186 | { | |
187 | } | |
169a0abb TG |
188 | |
189 | #endif | |
190 | ||
592913ec | 191 | #if defined(CONFIG_X86) |
520daf72 | 192 | static void tsc_check_state(int state) |
ddb25f9a AK |
193 | { |
194 | switch (boot_cpu_data.x86_vendor) { | |
7377ed4b | 195 | case X86_VENDOR_HYGON: |
ddb25f9a | 196 | case X86_VENDOR_AMD: |
40fb1715 | 197 | case X86_VENDOR_INTEL: |
fe6daab1 | 198 | case X86_VENDOR_CENTAUR: |
773b2f30 | 199 | case X86_VENDOR_ZHAOXIN: |
ddb25f9a AK |
200 | /* |
201 | * AMD Fam10h TSC will tick in all | |
202 | * C/P/S0/S1 states when this bit is set. | |
203 | */ | |
40fb1715 | 204 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 205 | return; |
40fb1715 | 206 | |
ddb25f9a | 207 | /*FALL THROUGH*/ |
ddb25f9a | 208 | default: |
520daf72 LB |
209 | /* TSC could halt in idle, so notify users */ |
210 | if (state > ACPI_STATE_C1) | |
211 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
212 | } |
213 | } | |
520daf72 LB |
214 | #else |
215 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
216 | #endif |
217 | ||
4be44fcd | 218 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 219 | { |
1da177e4 | 220 | |
1da177e4 | 221 | if (!pr->pblk) |
d550d98d | 222 | return -ENODEV; |
1da177e4 | 223 | |
1da177e4 | 224 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
225 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
226 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
227 | ||
4c033552 VP |
228 | #ifndef CONFIG_HOTPLUG_CPU |
229 | /* | |
230 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 231 | * an SMP system. |
4c033552 | 232 | */ |
ad71860a | 233 | if ((num_online_cpus() > 1) && |
cee324b1 | 234 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 235 | return -ENODEV; |
4c033552 VP |
236 | #endif |
237 | ||
1da177e4 LT |
238 | /* determine C2 and C3 address from pblk */ |
239 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
240 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
241 | ||
242 | /* determine latencies from FADT */ | |
ba494bee BM |
243 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; |
244 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; | |
1da177e4 | 245 | |
5d76b6f6 LB |
246 | /* |
247 | * FADT specified C2 latency must be less than or equal to | |
248 | * 100 microseconds. | |
249 | */ | |
ba494bee | 250 | if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
5d76b6f6 | 251 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 252 | "C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency)); |
5d76b6f6 LB |
253 | /* invalidate C2 */ |
254 | pr->power.states[ACPI_STATE_C2].address = 0; | |
255 | } | |
256 | ||
a6d72c18 LB |
257 | /* |
258 | * FADT supplied C3 latency must be less than or equal to | |
259 | * 1000 microseconds. | |
260 | */ | |
ba494bee | 261 | if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
a6d72c18 | 262 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 263 | "C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency)); |
a6d72c18 LB |
264 | /* invalidate C3 */ |
265 | pr->power.states[ACPI_STATE_C3].address = 0; | |
266 | } | |
267 | ||
1da177e4 LT |
268 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
269 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
270 | pr->power.states[ACPI_STATE_C2].address, | |
271 | pr->power.states[ACPI_STATE_C3].address)); | |
272 | ||
34a62cd0 YG |
273 | snprintf(pr->power.states[ACPI_STATE_C2].desc, |
274 | ACPI_CX_DESC_LEN, "ACPI P_LVL2 IOPORT 0x%x", | |
275 | pr->power.states[ACPI_STATE_C2].address); | |
276 | snprintf(pr->power.states[ACPI_STATE_C3].desc, | |
277 | ACPI_CX_DESC_LEN, "ACPI P_LVL3 IOPORT 0x%x", | |
278 | pr->power.states[ACPI_STATE_C3].address); | |
279 | ||
d550d98d | 280 | return 0; |
1da177e4 LT |
281 | } |
282 | ||
991528d7 | 283 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 284 | { |
991528d7 VP |
285 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
286 | /* set the first C-State to C1 */ | |
287 | /* all processors need to support C1 */ | |
288 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
289 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 290 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
248e8841 YG |
291 | |
292 | snprintf(pr->power.states[ACPI_STATE_C1].desc, | |
293 | ACPI_CX_DESC_LEN, "ACPI HLT"); | |
991528d7 VP |
294 | } |
295 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 296 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 297 | return 0; |
acf05f4b VP |
298 | } |
299 | ||
987c7853 RW |
300 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
301 | { | |
302 | int ret; | |
303 | ||
304 | if (nocst) | |
305 | return -ENODEV; | |
306 | ||
307 | ret = acpi_processor_evaluate_cst(pr->handle, pr->id, &pr->power); | |
308 | if (ret) | |
309 | return ret; | |
310 | ||
311 | /* | |
312 | * It is expected that there will be at least 2 states, C1 and | |
313 | * something else (C2 or C3), so fail if that is not the case. | |
314 | */ | |
315 | if (pr->power.count < 2) | |
316 | return -EFAULT; | |
317 | ||
318 | pr->flags.has_cst = 1; | |
319 | return 0; | |
320 | } | |
321 | ||
4be44fcd LB |
322 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
323 | struct acpi_processor_cx *cx) | |
1da177e4 | 324 | { |
ee1ca48f PV |
325 | static int bm_check_flag = -1; |
326 | static int bm_control_flag = -1; | |
02df8b93 | 327 | |
1da177e4 LT |
328 | |
329 | if (!cx->address) | |
d550d98d | 330 | return; |
1da177e4 | 331 | |
1da177e4 LT |
332 | /* |
333 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
334 | * DMA transfers are used by any ISA device to avoid livelock. | |
335 | * Note that we could disable Type-F DMA (as recommended by | |
336 | * the erratum), but this is known to disrupt certain ISA | |
337 | * devices thus we take the conservative approach. | |
338 | */ | |
339 | else if (errata.piix4.fdma) { | |
340 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 341 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 342 | return; |
1da177e4 LT |
343 | } |
344 | ||
02df8b93 | 345 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 346 | if (bm_check_flag == -1) { |
02df8b93 VP |
347 | /* Determine whether bm_check is needed based on CPU */ |
348 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
349 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 350 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
351 | } else { |
352 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 353 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
354 | } |
355 | ||
356 | if (pr->flags.bm_check) { | |
02df8b93 | 357 | if (!pr->flags.bm_control) { |
ed3110ef VP |
358 | if (pr->flags.has_cst != 1) { |
359 | /* bus mastering control is necessary */ | |
360 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
361 | "C3 support requires BM control\n")); | |
362 | return; | |
363 | } else { | |
364 | /* Here we enter C3 without bus mastering */ | |
365 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
366 | "C3 support without BM control\n")); | |
367 | } | |
02df8b93 VP |
368 | } |
369 | } else { | |
02df8b93 VP |
370 | /* |
371 | * WBINVD should be set in fadt, for C3 state to be | |
372 | * supported on when bm_check is not required. | |
373 | */ | |
cee324b1 | 374 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 375 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
376 | "Cache invalidation should work properly" |
377 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 378 | return; |
02df8b93 | 379 | } |
02df8b93 VP |
380 | } |
381 | ||
1da177e4 LT |
382 | /* |
383 | * Otherwise we've met all of our C3 requirements. | |
384 | * Normalize the C3 latency to expidite policy. Enable | |
385 | * checking of bus mastering status (bm_check) so we can | |
386 | * use this in our C3 policy | |
387 | */ | |
388 | cx->valid = 1; | |
4f86d3a8 | 389 | |
31878dd8 LB |
390 | /* |
391 | * On older chipsets, BM_RLD needs to be set | |
392 | * in order for Bus Master activity to wake the | |
393 | * system from C3. Newer chipsets handle DMA | |
394 | * during C3 automatically and BM_RLD is a NOP. | |
395 | * In either case, the proper way to | |
396 | * handle BM_RLD is to set it and leave it set. | |
397 | */ | |
50ffba1b | 398 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 399 | |
d550d98d | 400 | return; |
1da177e4 LT |
401 | } |
402 | ||
1da177e4 LT |
403 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
404 | { | |
405 | unsigned int i; | |
406 | unsigned int working = 0; | |
6eb0a0fd | 407 | |
169a0abb | 408 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 409 | |
a0bf284b | 410 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
411 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
412 | ||
413 | switch (cx->type) { | |
414 | case ACPI_STATE_C1: | |
415 | cx->valid = 1; | |
416 | break; | |
417 | ||
418 | case ACPI_STATE_C2: | |
d22edd29 LB |
419 | if (!cx->address) |
420 | break; | |
cad1525a | 421 | cx->valid = 1; |
1da177e4 LT |
422 | break; |
423 | ||
424 | case ACPI_STATE_C3: | |
425 | acpi_processor_power_verify_c3(pr, cx); | |
426 | break; | |
427 | } | |
7e275cc4 LB |
428 | if (!cx->valid) |
429 | continue; | |
1da177e4 | 430 | |
7e275cc4 LB |
431 | lapic_timer_check_state(i, pr, cx); |
432 | tsc_check_state(cx->type); | |
433 | working++; | |
1da177e4 | 434 | } |
bd663347 | 435 | |
918aae42 | 436 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
437 | |
438 | return (working); | |
439 | } | |
440 | ||
a36a7fec | 441 | static int acpi_processor_get_cstate_info(struct acpi_processor *pr) |
1da177e4 LT |
442 | { |
443 | unsigned int i; | |
444 | int result; | |
445 | ||
1da177e4 LT |
446 | |
447 | /* NOTE: the idle thread may not be running while calling | |
448 | * this function */ | |
449 | ||
991528d7 VP |
450 | /* Zero initialize all the C-states info. */ |
451 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
452 | ||
1da177e4 | 453 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 454 | if (result == -ENODEV) |
c5a114f1 | 455 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 456 | |
991528d7 VP |
457 | if (result) |
458 | return result; | |
459 | ||
460 | acpi_processor_get_power_info_default(pr); | |
461 | ||
cf824788 | 462 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 463 | |
1da177e4 LT |
464 | /* |
465 | * if one state of type C2 or C3 is available, mark this | |
466 | * CPU as being "idle manageable" | |
467 | */ | |
468 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 469 | if (pr->power.states[i].valid) { |
1da177e4 | 470 | pr->power.count = i; |
2203d6ed LT |
471 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
472 | pr->flags.power = 1; | |
acf05f4b | 473 | } |
1da177e4 LT |
474 | } |
475 | ||
d550d98d | 476 | return 0; |
1da177e4 LT |
477 | } |
478 | ||
4f86d3a8 LB |
479 | /** |
480 | * acpi_idle_bm_check - checks if bus master activity was detected | |
481 | */ | |
482 | static int acpi_idle_bm_check(void) | |
483 | { | |
484 | u32 bm_status = 0; | |
485 | ||
d3e7e99f LB |
486 | if (bm_check_disable) |
487 | return 0; | |
488 | ||
50ffba1b | 489 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 490 | if (bm_status) |
50ffba1b | 491 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
492 | /* |
493 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
494 | * the true state of bus mastering activity; forcing us to | |
495 | * manually check the BMIDEA bit of each IDE channel. | |
496 | */ | |
497 | else if (errata.piix4.bmisx) { | |
498 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
499 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
500 | bm_status = 1; | |
501 | } | |
502 | return bm_status; | |
503 | } | |
504 | ||
fa583f71 YF |
505 | static void wait_for_freeze(void) |
506 | { | |
507 | #ifdef CONFIG_X86 | |
508 | /* No delay is needed if we are in guest */ | |
509 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
510 | return; | |
511 | #endif | |
512 | /* Dummy wait op - must do something useless after P_LVL2 read | |
513 | because chipsets cannot guarantee that STPCLK# signal | |
514 | gets asserted in time to freeze execution properly. */ | |
515 | inl(acpi_gbl_FADT.xpm_timer_block.address); | |
516 | } | |
517 | ||
4f86d3a8 | 518 | /** |
b00783fd | 519 | * acpi_idle_do_entry - enter idle state using the appropriate method |
4f86d3a8 | 520 | * @cx: cstate data |
bc71bec9 | 521 | * |
522 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 | 523 | */ |
6727ad9e | 524 | static void __cpuidle acpi_idle_do_entry(struct acpi_processor_cx *cx) |
4f86d3a8 | 525 | { |
bc71bec9 | 526 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
527 | /* Call into architectural FFH based C-state */ |
528 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 529 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
530 | acpi_safe_halt(); | |
4f86d3a8 | 531 | } else { |
4f86d3a8 LB |
532 | /* IO port based C-state */ |
533 | inb(cx->address); | |
fa583f71 | 534 | wait_for_freeze(); |
4f86d3a8 LB |
535 | } |
536 | } | |
537 | ||
1a022e3f BO |
538 | /** |
539 | * acpi_idle_play_dead - enters an ACPI state for long-term idle (i.e. off-lining) | |
540 | * @dev: the target CPU | |
541 | * @index: the index of suggested state | |
542 | */ | |
543 | static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) | |
544 | { | |
6240a10d | 545 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
1a022e3f BO |
546 | |
547 | ACPI_FLUSH_CPU_CACHE(); | |
548 | ||
549 | while (1) { | |
550 | ||
551 | if (cx->entry_method == ACPI_CSTATE_HALT) | |
54f70077 | 552 | safe_halt(); |
1a022e3f BO |
553 | else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { |
554 | inb(cx->address); | |
fa583f71 | 555 | wait_for_freeze(); |
1a022e3f BO |
556 | } else |
557 | return -ENODEV; | |
558 | } | |
559 | ||
560 | /* Never reached */ | |
561 | return 0; | |
562 | } | |
563 | ||
adcb2623 RW |
564 | static bool acpi_idle_fallback_to_c1(struct acpi_processor *pr) |
565 | { | |
5f508185 RW |
566 | return IS_ENABLED(CONFIG_HOTPLUG_CPU) && !pr->flags.has_cst && |
567 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED); | |
adcb2623 RW |
568 | } |
569 | ||
4f86d3a8 | 570 | static int c3_cpu_count; |
e12f65f7 | 571 | static DEFINE_RAW_SPINLOCK(c3_lock); |
4f86d3a8 LB |
572 | |
573 | /** | |
574 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
6491bc0c RW |
575 | * @pr: Target processor |
576 | * @cx: Target state context | |
5f508185 | 577 | * @timer_bc: Whether or not to change timer mode to broadcast |
4f86d3a8 | 578 | */ |
6491bc0c | 579 | static void acpi_idle_enter_bm(struct acpi_processor *pr, |
5f508185 | 580 | struct acpi_processor_cx *cx, bool timer_bc) |
4f86d3a8 | 581 | { |
67535736 AL |
582 | acpi_unlazy_tlb(smp_processor_id()); |
583 | ||
4f86d3a8 LB |
584 | /* |
585 | * Must be done before busmaster disable as we might need to | |
586 | * access HPET ! | |
587 | */ | |
5f508185 RW |
588 | if (timer_bc) |
589 | lapic_timer_state_broadcast(pr, cx, 1); | |
4f86d3a8 | 590 | |
ddc081a1 VP |
591 | /* |
592 | * disable bus master | |
593 | * bm_check implies we need ARB_DIS | |
ddc081a1 VP |
594 | * bm_control implies whether we can do ARB_DIS |
595 | * | |
596 | * That leaves a case where bm_check is set and bm_control is | |
597 | * not set. In that case we cannot do much, we enter C3 | |
598 | * without doing anything. | |
599 | */ | |
2a738352 | 600 | if (pr->flags.bm_control) { |
e12f65f7 | 601 | raw_spin_lock(&c3_lock); |
4f86d3a8 LB |
602 | c3_cpu_count++; |
603 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
604 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 605 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
e12f65f7 | 606 | raw_spin_unlock(&c3_lock); |
ddc081a1 | 607 | } |
4f86d3a8 | 608 | |
ddc081a1 | 609 | acpi_idle_do_entry(cx); |
4f86d3a8 | 610 | |
ddc081a1 | 611 | /* Re-enable bus master arbitration */ |
2a738352 | 612 | if (pr->flags.bm_control) { |
e12f65f7 | 613 | raw_spin_lock(&c3_lock); |
50ffba1b | 614 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 | 615 | c3_cpu_count--; |
e12f65f7 | 616 | raw_spin_unlock(&c3_lock); |
4f86d3a8 | 617 | } |
e978aa7d | 618 | |
5f508185 RW |
619 | if (timer_bc) |
620 | lapic_timer_state_broadcast(pr, cx, 0); | |
6491bc0c RW |
621 | } |
622 | ||
623 | static int acpi_idle_enter(struct cpuidle_device *dev, | |
624 | struct cpuidle_driver *drv, int index) | |
625 | { | |
626 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); | |
627 | struct acpi_processor *pr; | |
628 | ||
629 | pr = __this_cpu_read(processors); | |
630 | if (unlikely(!pr)) | |
631 | return -EINVAL; | |
632 | ||
633 | if (cx->type != ACPI_STATE_C1) { | |
5f508185 | 634 | if (acpi_idle_fallback_to_c1(pr) && num_online_cpus() > 1) { |
dc2251bf | 635 | index = ACPI_IDLE_STATE_START; |
6491bc0c RW |
636 | cx = per_cpu(acpi_cstate[index], dev->cpu); |
637 | } else if (cx->type == ACPI_STATE_C3 && pr->flags.bm_check) { | |
638 | if (cx->bm_sts_skip || !acpi_idle_bm_check()) { | |
5f508185 | 639 | acpi_idle_enter_bm(pr, cx, true); |
6491bc0c RW |
640 | return index; |
641 | } else if (drv->safe_state_index >= 0) { | |
642 | index = drv->safe_state_index; | |
643 | cx = per_cpu(acpi_cstate[index], dev->cpu); | |
644 | } else { | |
645 | acpi_safe_halt(); | |
646 | return -EBUSY; | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
651 | lapic_timer_state_broadcast(pr, cx, 1); | |
652 | ||
653 | if (cx->type == ACPI_STATE_C3) | |
654 | ACPI_FLUSH_CPU_CACHE(); | |
655 | ||
656 | acpi_idle_do_entry(cx); | |
657 | ||
658 | lapic_timer_state_broadcast(pr, cx, 0); | |
659 | ||
e978aa7d | 660 | return index; |
4f86d3a8 LB |
661 | } |
662 | ||
28ba086e | 663 | static void acpi_idle_enter_s2idle(struct cpuidle_device *dev, |
5f508185 RW |
664 | struct cpuidle_driver *drv, int index) |
665 | { | |
666 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); | |
667 | ||
668 | if (cx->type == ACPI_STATE_C3) { | |
669 | struct acpi_processor *pr = __this_cpu_read(processors); | |
670 | ||
671 | if (unlikely(!pr)) | |
672 | return; | |
673 | ||
674 | if (pr->flags.bm_check) { | |
675 | acpi_idle_enter_bm(pr, cx, false); | |
676 | return; | |
677 | } else { | |
678 | ACPI_FLUSH_CPU_CACHE(); | |
679 | } | |
680 | } | |
681 | acpi_idle_do_entry(cx); | |
682 | } | |
683 | ||
6ef0f086 DL |
684 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, |
685 | struct cpuidle_device *dev) | |
4f86d3a8 | 686 | { |
dc2251bf | 687 | int i, count = ACPI_IDLE_STATE_START; |
4f86d3a8 | 688 | struct acpi_processor_cx *cx; |
4f86d3a8 | 689 | |
615dfd93 LB |
690 | if (max_cstate == 0) |
691 | max_cstate = 1; | |
692 | ||
4f86d3a8 LB |
693 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
694 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
695 | |
696 | if (!cx->valid) | |
697 | continue; | |
698 | ||
6240a10d | 699 | per_cpu(acpi_cstate[count], dev->cpu) = cx; |
4f86d3a8 | 700 | |
46bcfad7 DD |
701 | count++; |
702 | if (count == CPUIDLE_STATE_MAX) | |
703 | break; | |
704 | } | |
705 | ||
46bcfad7 DD |
706 | if (!count) |
707 | return -EINVAL; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
a36a7fec | 712 | static int acpi_processor_setup_cstates(struct acpi_processor *pr) |
46bcfad7 | 713 | { |
1b39e3f8 | 714 | int i, count; |
46bcfad7 DD |
715 | struct acpi_processor_cx *cx; |
716 | struct cpuidle_state *state; | |
717 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
718 | ||
615dfd93 LB |
719 | if (max_cstate == 0) |
720 | max_cstate = 1; | |
721 | ||
1b39e3f8 RW |
722 | if (IS_ENABLED(CONFIG_ARCH_HAS_CPU_RELAX)) { |
723 | cpuidle_poll_state_init(drv); | |
724 | count = 1; | |
725 | } else { | |
726 | count = 0; | |
727 | } | |
728 | ||
4f86d3a8 LB |
729 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
730 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
731 | |
732 | if (!cx->valid) | |
733 | continue; | |
734 | ||
46bcfad7 | 735 | state = &drv->states[count]; |
4f86d3a8 | 736 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
a36a7fec | 737 | strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 738 | state->exit_latency = cx->latency; |
4963f620 | 739 | state->target_residency = cx->latency * latency_factor; |
6491bc0c | 740 | state->enter = acpi_idle_enter; |
4f86d3a8 LB |
741 | |
742 | state->flags = 0; | |
6491bc0c | 743 | if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2) { |
1a022e3f | 744 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 745 | drv->safe_state_index = count; |
4f86d3a8 | 746 | } |
5f508185 | 747 | /* |
28ba086e | 748 | * Halt-induced C1 is not good for ->enter_s2idle, because it |
5f508185 RW |
749 | * re-enables interrupts on exit. Moreover, C1 is generally not |
750 | * particularly interesting from the suspend-to-idle angle, so | |
751 | * avoid C1 and the situations in which we may need to fall back | |
752 | * to it altogether. | |
753 | */ | |
754 | if (cx->type != ACPI_STATE_C1 && !acpi_idle_fallback_to_c1(pr)) | |
28ba086e | 755 | state->enter_s2idle = acpi_idle_enter_s2idle; |
4f86d3a8 LB |
756 | |
757 | count++; | |
9a0b8415 | 758 | if (count == CPUIDLE_STATE_MAX) |
759 | break; | |
4f86d3a8 LB |
760 | } |
761 | ||
46bcfad7 | 762 | drv->state_count = count; |
4f86d3a8 LB |
763 | |
764 | if (!count) | |
765 | return -EINVAL; | |
766 | ||
4f86d3a8 LB |
767 | return 0; |
768 | } | |
769 | ||
35ae7133 SH |
770 | static inline void acpi_processor_cstate_first_run_checks(void) |
771 | { | |
35ae7133 SH |
772 | static int first_run; |
773 | ||
774 | if (first_run) | |
775 | return; | |
776 | dmi_check_system(processor_power_dmi_table); | |
777 | max_cstate = acpi_processor_cstate_check(max_cstate); | |
778 | if (max_cstate < ACPI_C_STATES_MAX) | |
779 | pr_notice("ACPI: processor limited to max C-state %d\n", | |
780 | max_cstate); | |
781 | first_run++; | |
782 | ||
bc946388 RW |
783 | if (nocst) |
784 | return; | |
785 | ||
786 | acpi_processor_claim_cst_control(); | |
35ae7133 SH |
787 | } |
788 | #else | |
789 | ||
790 | static inline int disabled_by_idle_boot_param(void) { return 0; } | |
791 | static inline void acpi_processor_cstate_first_run_checks(void) { } | |
a36a7fec | 792 | static int acpi_processor_get_cstate_info(struct acpi_processor *pr) |
35ae7133 SH |
793 | { |
794 | return -ENODEV; | |
795 | } | |
796 | ||
797 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, | |
798 | struct cpuidle_device *dev) | |
799 | { | |
800 | return -EINVAL; | |
801 | } | |
802 | ||
a36a7fec | 803 | static int acpi_processor_setup_cstates(struct acpi_processor *pr) |
35ae7133 SH |
804 | { |
805 | return -EINVAL; | |
806 | } | |
807 | ||
808 | #endif /* CONFIG_ACPI_PROCESSOR_CSTATE */ | |
809 | ||
a36a7fec SH |
810 | struct acpi_lpi_states_array { |
811 | unsigned int size; | |
812 | unsigned int composite_states_size; | |
813 | struct acpi_lpi_state *entries; | |
814 | struct acpi_lpi_state *composite_states[ACPI_PROCESSOR_MAX_POWER]; | |
815 | }; | |
816 | ||
817 | static int obj_get_integer(union acpi_object *obj, u32 *value) | |
818 | { | |
819 | if (obj->type != ACPI_TYPE_INTEGER) | |
820 | return -EINVAL; | |
821 | ||
822 | *value = obj->integer.value; | |
823 | return 0; | |
824 | } | |
825 | ||
826 | static int acpi_processor_evaluate_lpi(acpi_handle handle, | |
827 | struct acpi_lpi_states_array *info) | |
828 | { | |
829 | acpi_status status; | |
830 | int ret = 0; | |
831 | int pkg_count, state_idx = 1, loop; | |
832 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
833 | union acpi_object *lpi_data; | |
834 | struct acpi_lpi_state *lpi_state; | |
835 | ||
836 | status = acpi_evaluate_object(handle, "_LPI", NULL, &buffer); | |
837 | if (ACPI_FAILURE(status)) { | |
838 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _LPI, giving up\n")); | |
839 | return -ENODEV; | |
840 | } | |
841 | ||
842 | lpi_data = buffer.pointer; | |
843 | ||
844 | /* There must be at least 4 elements = 3 elements + 1 package */ | |
845 | if (!lpi_data || lpi_data->type != ACPI_TYPE_PACKAGE || | |
846 | lpi_data->package.count < 4) { | |
847 | pr_debug("not enough elements in _LPI\n"); | |
848 | ret = -ENODATA; | |
849 | goto end; | |
850 | } | |
851 | ||
852 | pkg_count = lpi_data->package.elements[2].integer.value; | |
853 | ||
854 | /* Validate number of power states. */ | |
855 | if (pkg_count < 1 || pkg_count != lpi_data->package.count - 3) { | |
856 | pr_debug("count given by _LPI is not valid\n"); | |
857 | ret = -ENODATA; | |
858 | goto end; | |
859 | } | |
860 | ||
861 | lpi_state = kcalloc(pkg_count, sizeof(*lpi_state), GFP_KERNEL); | |
862 | if (!lpi_state) { | |
863 | ret = -ENOMEM; | |
864 | goto end; | |
865 | } | |
866 | ||
867 | info->size = pkg_count; | |
868 | info->entries = lpi_state; | |
869 | ||
870 | /* LPI States start at index 3 */ | |
871 | for (loop = 3; state_idx <= pkg_count; loop++, state_idx++, lpi_state++) { | |
872 | union acpi_object *element, *pkg_elem, *obj; | |
873 | ||
874 | element = &lpi_data->package.elements[loop]; | |
875 | if (element->type != ACPI_TYPE_PACKAGE || element->package.count < 7) | |
876 | continue; | |
877 | ||
878 | pkg_elem = element->package.elements; | |
879 | ||
880 | obj = pkg_elem + 6; | |
881 | if (obj->type == ACPI_TYPE_BUFFER) { | |
882 | struct acpi_power_register *reg; | |
883 | ||
884 | reg = (struct acpi_power_register *)obj->buffer.pointer; | |
885 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
886 | reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) | |
887 | continue; | |
888 | ||
889 | lpi_state->address = reg->address; | |
890 | lpi_state->entry_method = | |
891 | reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE ? | |
892 | ACPI_CSTATE_FFH : ACPI_CSTATE_SYSTEMIO; | |
893 | } else if (obj->type == ACPI_TYPE_INTEGER) { | |
894 | lpi_state->entry_method = ACPI_CSTATE_INTEGER; | |
895 | lpi_state->address = obj->integer.value; | |
896 | } else { | |
897 | continue; | |
898 | } | |
899 | ||
900 | /* elements[7,8] skipped for now i.e. Residency/Usage counter*/ | |
901 | ||
902 | obj = pkg_elem + 9; | |
903 | if (obj->type == ACPI_TYPE_STRING) | |
904 | strlcpy(lpi_state->desc, obj->string.pointer, | |
905 | ACPI_CX_DESC_LEN); | |
906 | ||
907 | lpi_state->index = state_idx; | |
908 | if (obj_get_integer(pkg_elem + 0, &lpi_state->min_residency)) { | |
909 | pr_debug("No min. residency found, assuming 10 us\n"); | |
910 | lpi_state->min_residency = 10; | |
911 | } | |
912 | ||
913 | if (obj_get_integer(pkg_elem + 1, &lpi_state->wake_latency)) { | |
914 | pr_debug("No wakeup residency found, assuming 10 us\n"); | |
915 | lpi_state->wake_latency = 10; | |
916 | } | |
917 | ||
918 | if (obj_get_integer(pkg_elem + 2, &lpi_state->flags)) | |
919 | lpi_state->flags = 0; | |
920 | ||
921 | if (obj_get_integer(pkg_elem + 3, &lpi_state->arch_flags)) | |
922 | lpi_state->arch_flags = 0; | |
923 | ||
924 | if (obj_get_integer(pkg_elem + 4, &lpi_state->res_cnt_freq)) | |
925 | lpi_state->res_cnt_freq = 1; | |
926 | ||
927 | if (obj_get_integer(pkg_elem + 5, &lpi_state->enable_parent_state)) | |
928 | lpi_state->enable_parent_state = 0; | |
929 | } | |
930 | ||
931 | acpi_handle_debug(handle, "Found %d power states\n", state_idx); | |
932 | end: | |
933 | kfree(buffer.pointer); | |
934 | return ret; | |
935 | } | |
936 | ||
937 | /* | |
938 | * flat_state_cnt - the number of composite LPI states after the process of flattening | |
939 | */ | |
940 | static int flat_state_cnt; | |
941 | ||
942 | /** | |
943 | * combine_lpi_states - combine local and parent LPI states to form a composite LPI state | |
944 | * | |
945 | * @local: local LPI state | |
946 | * @parent: parent LPI state | |
947 | * @result: composite LPI state | |
948 | */ | |
949 | static bool combine_lpi_states(struct acpi_lpi_state *local, | |
950 | struct acpi_lpi_state *parent, | |
951 | struct acpi_lpi_state *result) | |
952 | { | |
953 | if (parent->entry_method == ACPI_CSTATE_INTEGER) { | |
954 | if (!parent->address) /* 0 means autopromotable */ | |
955 | return false; | |
956 | result->address = local->address + parent->address; | |
957 | } else { | |
958 | result->address = parent->address; | |
959 | } | |
960 | ||
961 | result->min_residency = max(local->min_residency, parent->min_residency); | |
962 | result->wake_latency = local->wake_latency + parent->wake_latency; | |
963 | result->enable_parent_state = parent->enable_parent_state; | |
964 | result->entry_method = local->entry_method; | |
965 | ||
966 | result->flags = parent->flags; | |
967 | result->arch_flags = parent->arch_flags; | |
968 | result->index = parent->index; | |
969 | ||
970 | strlcpy(result->desc, local->desc, ACPI_CX_DESC_LEN); | |
971 | strlcat(result->desc, "+", ACPI_CX_DESC_LEN); | |
972 | strlcat(result->desc, parent->desc, ACPI_CX_DESC_LEN); | |
973 | return true; | |
974 | } | |
975 | ||
976 | #define ACPI_LPI_STATE_FLAGS_ENABLED BIT(0) | |
977 | ||
978 | static void stash_composite_state(struct acpi_lpi_states_array *curr_level, | |
979 | struct acpi_lpi_state *t) | |
980 | { | |
981 | curr_level->composite_states[curr_level->composite_states_size++] = t; | |
982 | } | |
983 | ||
984 | static int flatten_lpi_states(struct acpi_processor *pr, | |
985 | struct acpi_lpi_states_array *curr_level, | |
986 | struct acpi_lpi_states_array *prev_level) | |
987 | { | |
988 | int i, j, state_count = curr_level->size; | |
989 | struct acpi_lpi_state *p, *t = curr_level->entries; | |
990 | ||
991 | curr_level->composite_states_size = 0; | |
992 | for (j = 0; j < state_count; j++, t++) { | |
993 | struct acpi_lpi_state *flpi; | |
994 | ||
995 | if (!(t->flags & ACPI_LPI_STATE_FLAGS_ENABLED)) | |
996 | continue; | |
997 | ||
998 | if (flat_state_cnt >= ACPI_PROCESSOR_MAX_POWER) { | |
999 | pr_warn("Limiting number of LPI states to max (%d)\n", | |
1000 | ACPI_PROCESSOR_MAX_POWER); | |
1001 | pr_warn("Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
1002 | break; | |
1003 | } | |
1004 | ||
1005 | flpi = &pr->power.lpi_states[flat_state_cnt]; | |
1006 | ||
1007 | if (!prev_level) { /* leaf/processor node */ | |
1008 | memcpy(flpi, t, sizeof(*t)); | |
1009 | stash_composite_state(curr_level, flpi); | |
1010 | flat_state_cnt++; | |
1011 | continue; | |
1012 | } | |
1013 | ||
1014 | for (i = 0; i < prev_level->composite_states_size; i++) { | |
1015 | p = prev_level->composite_states[i]; | |
1016 | if (t->index <= p->enable_parent_state && | |
1017 | combine_lpi_states(p, t, flpi)) { | |
1018 | stash_composite_state(curr_level, flpi); | |
1019 | flat_state_cnt++; | |
1020 | flpi++; | |
1021 | } | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | kfree(curr_level->entries); | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static int acpi_processor_get_lpi_info(struct acpi_processor *pr) | |
1030 | { | |
1031 | int ret, i; | |
1032 | acpi_status status; | |
1033 | acpi_handle handle = pr->handle, pr_ahandle; | |
1034 | struct acpi_device *d = NULL; | |
1035 | struct acpi_lpi_states_array info[2], *tmp, *prev, *curr; | |
1036 | ||
1037 | if (!osc_pc_lpi_support_confirmed) | |
1038 | return -EOPNOTSUPP; | |
1039 | ||
1040 | if (!acpi_has_method(handle, "_LPI")) | |
1041 | return -EINVAL; | |
1042 | ||
1043 | flat_state_cnt = 0; | |
1044 | prev = &info[0]; | |
1045 | curr = &info[1]; | |
1046 | handle = pr->handle; | |
1047 | ret = acpi_processor_evaluate_lpi(handle, prev); | |
1048 | if (ret) | |
1049 | return ret; | |
1050 | flatten_lpi_states(pr, prev, NULL); | |
1051 | ||
1052 | status = acpi_get_parent(handle, &pr_ahandle); | |
1053 | while (ACPI_SUCCESS(status)) { | |
1054 | acpi_bus_get_device(pr_ahandle, &d); | |
1055 | handle = pr_ahandle; | |
1056 | ||
1057 | if (strcmp(acpi_device_hid(d), ACPI_PROCESSOR_CONTAINER_HID)) | |
1058 | break; | |
1059 | ||
1060 | /* can be optional ? */ | |
1061 | if (!acpi_has_method(handle, "_LPI")) | |
1062 | break; | |
1063 | ||
1064 | ret = acpi_processor_evaluate_lpi(handle, curr); | |
1065 | if (ret) | |
1066 | break; | |
1067 | ||
1068 | /* flatten all the LPI states in this level of hierarchy */ | |
1069 | flatten_lpi_states(pr, curr, prev); | |
1070 | ||
1071 | tmp = prev, prev = curr, curr = tmp; | |
1072 | ||
1073 | status = acpi_get_parent(handle, &pr_ahandle); | |
1074 | } | |
1075 | ||
1076 | pr->power.count = flat_state_cnt; | |
1077 | /* reset the index after flattening */ | |
1078 | for (i = 0; i < pr->power.count; i++) | |
1079 | pr->power.lpi_states[i].index = i; | |
1080 | ||
1081 | /* Tell driver that _LPI is supported. */ | |
1082 | pr->flags.has_lpi = 1; | |
1083 | pr->flags.power = 1; | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | int __weak acpi_processor_ffh_lpi_probe(unsigned int cpu) | |
1089 | { | |
1090 | return -ENODEV; | |
1091 | } | |
1092 | ||
1093 | int __weak acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) | |
1094 | { | |
1095 | return -ENODEV; | |
1096 | } | |
1097 | ||
1098 | /** | |
1099 | * acpi_idle_lpi_enter - enters an ACPI any LPI state | |
1100 | * @dev: the target CPU | |
1101 | * @drv: cpuidle driver containing cpuidle state info | |
1102 | * @index: index of target state | |
1103 | * | |
1104 | * Return: 0 for success or negative value for error | |
1105 | */ | |
1106 | static int acpi_idle_lpi_enter(struct cpuidle_device *dev, | |
1107 | struct cpuidle_driver *drv, int index) | |
1108 | { | |
1109 | struct acpi_processor *pr; | |
1110 | struct acpi_lpi_state *lpi; | |
1111 | ||
1112 | pr = __this_cpu_read(processors); | |
1113 | ||
1114 | if (unlikely(!pr)) | |
1115 | return -EINVAL; | |
1116 | ||
1117 | lpi = &pr->power.lpi_states[index]; | |
1118 | if (lpi->entry_method == ACPI_CSTATE_FFH) | |
1119 | return acpi_processor_ffh_lpi_enter(lpi); | |
1120 | ||
1121 | return -EINVAL; | |
1122 | } | |
1123 | ||
1124 | static int acpi_processor_setup_lpi_states(struct acpi_processor *pr) | |
1125 | { | |
1126 | int i; | |
1127 | struct acpi_lpi_state *lpi; | |
1128 | struct cpuidle_state *state; | |
1129 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
1130 | ||
1131 | if (!pr->flags.has_lpi) | |
1132 | return -EOPNOTSUPP; | |
1133 | ||
1134 | for (i = 0; i < pr->power.count && i < CPUIDLE_STATE_MAX; i++) { | |
1135 | lpi = &pr->power.lpi_states[i]; | |
1136 | ||
1137 | state = &drv->states[i]; | |
1138 | snprintf(state->name, CPUIDLE_NAME_LEN, "LPI-%d", i); | |
1139 | strlcpy(state->desc, lpi->desc, CPUIDLE_DESC_LEN); | |
1140 | state->exit_latency = lpi->wake_latency; | |
1141 | state->target_residency = lpi->min_residency; | |
1142 | if (lpi->arch_flags) | |
1143 | state->flags |= CPUIDLE_FLAG_TIMER_STOP; | |
1144 | state->enter = acpi_idle_lpi_enter; | |
1145 | drv->safe_state_index = i; | |
1146 | } | |
1147 | ||
1148 | drv->state_count = i; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | /** | |
1154 | * acpi_processor_setup_cpuidle_states- prepares and configures cpuidle | |
1155 | * global state data i.e. idle routines | |
1156 | * | |
1157 | * @pr: the ACPI processor | |
1158 | */ | |
1159 | static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr) | |
1160 | { | |
1161 | int i; | |
1162 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
1163 | ||
1164 | if (!pr->flags.power_setup_done || !pr->flags.power) | |
1165 | return -EINVAL; | |
1166 | ||
1167 | drv->safe_state_index = -1; | |
dc2251bf | 1168 | for (i = ACPI_IDLE_STATE_START; i < CPUIDLE_STATE_MAX; i++) { |
a36a7fec SH |
1169 | drv->states[i].name[0] = '\0'; |
1170 | drv->states[i].desc[0] = '\0'; | |
1171 | } | |
1172 | ||
1173 | if (pr->flags.has_lpi) | |
1174 | return acpi_processor_setup_lpi_states(pr); | |
1175 | ||
1176 | return acpi_processor_setup_cstates(pr); | |
1177 | } | |
1178 | ||
1179 | /** | |
1180 | * acpi_processor_setup_cpuidle_dev - prepares and configures CPUIDLE | |
1181 | * device i.e. per-cpu data | |
1182 | * | |
1183 | * @pr: the ACPI processor | |
1184 | * @dev : the cpuidle device | |
1185 | */ | |
1186 | static int acpi_processor_setup_cpuidle_dev(struct acpi_processor *pr, | |
1187 | struct cpuidle_device *dev) | |
1188 | { | |
1189 | if (!pr->flags.power_setup_done || !pr->flags.power || !dev) | |
1190 | return -EINVAL; | |
1191 | ||
1192 | dev->cpu = pr->id; | |
1193 | if (pr->flags.has_lpi) | |
1194 | return acpi_processor_ffh_lpi_probe(pr->id); | |
1195 | ||
1196 | return acpi_processor_setup_cpuidle_cx(pr, dev); | |
1197 | } | |
1198 | ||
1199 | static int acpi_processor_get_power_info(struct acpi_processor *pr) | |
1200 | { | |
1201 | int ret; | |
1202 | ||
1203 | ret = acpi_processor_get_lpi_info(pr); | |
1204 | if (ret) | |
1205 | ret = acpi_processor_get_cstate_info(pr); | |
1206 | ||
1207 | return ret; | |
1208 | } | |
1209 | ||
46bcfad7 | 1210 | int acpi_processor_hotplug(struct acpi_processor *pr) |
4f86d3a8 | 1211 | { |
dcb84f33 | 1212 | int ret = 0; |
e8b1b59d | 1213 | struct cpuidle_device *dev; |
4f86d3a8 | 1214 | |
d1896049 | 1215 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1216 | return 0; |
1217 | ||
4f86d3a8 LB |
1218 | if (!pr->flags.power_setup_done) |
1219 | return -ENODEV; | |
1220 | ||
e8b1b59d | 1221 | dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 | 1222 | cpuidle_pause_and_lock(); |
3d339dcb | 1223 | cpuidle_disable_device(dev); |
a36a7fec SH |
1224 | ret = acpi_processor_get_power_info(pr); |
1225 | if (!ret && pr->flags.power) { | |
1226 | acpi_processor_setup_cpuidle_dev(pr, dev); | |
3d339dcb | 1227 | ret = cpuidle_enable_device(dev); |
dcb84f33 | 1228 | } |
4f86d3a8 LB |
1229 | cpuidle_resume_and_unlock(); |
1230 | ||
1231 | return ret; | |
1232 | } | |
1233 | ||
a36a7fec | 1234 | int acpi_processor_power_state_has_changed(struct acpi_processor *pr) |
46bcfad7 DD |
1235 | { |
1236 | int cpu; | |
1237 | struct acpi_processor *_pr; | |
3d339dcb | 1238 | struct cpuidle_device *dev; |
46bcfad7 DD |
1239 | |
1240 | if (disabled_by_idle_boot_param()) | |
1241 | return 0; | |
1242 | ||
46bcfad7 DD |
1243 | if (!pr->flags.power_setup_done) |
1244 | return -ENODEV; | |
1245 | ||
1246 | /* | |
1247 | * FIXME: Design the ACPI notification to make it once per | |
1248 | * system instead of once per-cpu. This condition is a hack | |
1249 | * to make the code that updates C-States be called once. | |
1250 | */ | |
1251 | ||
9505626d | 1252 | if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) { |
46bcfad7 | 1253 | |
46bcfad7 DD |
1254 | /* Protect against cpu-hotplug */ |
1255 | get_online_cpus(); | |
6726655d | 1256 | cpuidle_pause_and_lock(); |
46bcfad7 DD |
1257 | |
1258 | /* Disable all cpuidle devices */ | |
1259 | for_each_online_cpu(cpu) { | |
1260 | _pr = per_cpu(processors, cpu); | |
1261 | if (!_pr || !_pr->flags.power_setup_done) | |
1262 | continue; | |
3d339dcb DL |
1263 | dev = per_cpu(acpi_cpuidle_device, cpu); |
1264 | cpuidle_disable_device(dev); | |
46bcfad7 DD |
1265 | } |
1266 | ||
1267 | /* Populate Updated C-state information */ | |
f427e5f1 | 1268 | acpi_processor_get_power_info(pr); |
46bcfad7 DD |
1269 | acpi_processor_setup_cpuidle_states(pr); |
1270 | ||
1271 | /* Enable all cpuidle devices */ | |
1272 | for_each_online_cpu(cpu) { | |
1273 | _pr = per_cpu(processors, cpu); | |
1274 | if (!_pr || !_pr->flags.power_setup_done) | |
1275 | continue; | |
1276 | acpi_processor_get_power_info(_pr); | |
1277 | if (_pr->flags.power) { | |
3d339dcb | 1278 | dev = per_cpu(acpi_cpuidle_device, cpu); |
a36a7fec | 1279 | acpi_processor_setup_cpuidle_dev(_pr, dev); |
3d339dcb | 1280 | cpuidle_enable_device(dev); |
46bcfad7 DD |
1281 | } |
1282 | } | |
46bcfad7 | 1283 | cpuidle_resume_and_unlock(); |
6726655d | 1284 | put_online_cpus(); |
46bcfad7 DD |
1285 | } |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static int acpi_processor_registered; | |
1291 | ||
fe7bf106 | 1292 | int acpi_processor_power_init(struct acpi_processor *pr) |
1da177e4 | 1293 | { |
46bcfad7 | 1294 | int retval; |
3d339dcb | 1295 | struct cpuidle_device *dev; |
1da177e4 | 1296 | |
d1896049 | 1297 | if (disabled_by_idle_boot_param()) |
36a91358 | 1298 | return 0; |
1da177e4 | 1299 | |
35ae7133 | 1300 | acpi_processor_cstate_first_run_checks(); |
1da177e4 | 1301 | |
35ae7133 SH |
1302 | if (!acpi_processor_get_power_info(pr)) |
1303 | pr->flags.power_setup_done = 1; | |
1da177e4 LT |
1304 | |
1305 | /* | |
1306 | * Install the idle handler if processor power management is supported. | |
1307 | * Note that we use previously set idle handler will be used on | |
1308 | * platforms that only support C1. | |
1309 | */ | |
36a91358 | 1310 | if (pr->flags.power) { |
46bcfad7 DD |
1311 | /* Register acpi_idle_driver if not already registered */ |
1312 | if (!acpi_processor_registered) { | |
1313 | acpi_processor_setup_cpuidle_states(pr); | |
1314 | retval = cpuidle_register_driver(&acpi_idle_driver); | |
1315 | if (retval) | |
1316 | return retval; | |
b6ec26fb SH |
1317 | pr_debug("%s registered with cpuidle\n", |
1318 | acpi_idle_driver.name); | |
46bcfad7 | 1319 | } |
3d339dcb DL |
1320 | |
1321 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1322 | if (!dev) | |
1323 | return -ENOMEM; | |
1324 | per_cpu(acpi_cpuidle_device, pr->id) = dev; | |
1325 | ||
a36a7fec | 1326 | acpi_processor_setup_cpuidle_dev(pr, dev); |
3d339dcb | 1327 | |
46bcfad7 DD |
1328 | /* Register per-cpu cpuidle_device. Cpuidle driver |
1329 | * must already be registered before registering device | |
1330 | */ | |
3d339dcb | 1331 | retval = cpuidle_register_device(dev); |
46bcfad7 DD |
1332 | if (retval) { |
1333 | if (acpi_processor_registered == 0) | |
1334 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1335 | return retval; | |
1336 | } | |
1337 | acpi_processor_registered++; | |
1da177e4 | 1338 | } |
d550d98d | 1339 | return 0; |
1da177e4 LT |
1340 | } |
1341 | ||
38a991b6 | 1342 | int acpi_processor_power_exit(struct acpi_processor *pr) |
1da177e4 | 1343 | { |
3d339dcb DL |
1344 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
1345 | ||
d1896049 | 1346 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1347 | return 0; |
1348 | ||
46bcfad7 | 1349 | if (pr->flags.power) { |
3d339dcb | 1350 | cpuidle_unregister_device(dev); |
46bcfad7 DD |
1351 | acpi_processor_registered--; |
1352 | if (acpi_processor_registered == 0) | |
1353 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1354 | } | |
1da177e4 | 1355 | |
46bcfad7 | 1356 | pr->flags.power_setup_done = 0; |
d550d98d | 1357 | return 0; |
1da177e4 | 1358 | } |