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cb849fc5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
935c760e TN |
2 | /* |
3 | * Copyright (C) 2016 Broadcom | |
4 | * Author: Jayachandran C <jchandra@broadcom.com> | |
5 | * Copyright (C) 2016 Semihalf | |
6 | * Author: Tomasz Nowicki <tn@semihalf.com> | |
935c760e TN |
7 | */ |
8 | ||
9 | #define pr_fmt(fmt) "ACPI: " fmt | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/pci-acpi.h> | |
13983eb8 | 14 | #include <linux/pci-ecam.h> |
935c760e TN |
15 | |
16 | /* Structure to hold entries from the MCFG table */ | |
17 | struct mcfg_entry { | |
18 | struct list_head list; | |
19 | phys_addr_t addr; | |
20 | u16 segment; | |
21 | u8 bus_start; | |
22 | u8 bus_end; | |
23 | }; | |
24 | ||
5b69b85b TN |
25 | #ifdef CONFIG_PCI_QUIRKS |
26 | struct mcfg_fixup { | |
27 | char oem_id[ACPI_OEM_ID_SIZE + 1]; | |
28 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; | |
29 | u32 oem_revision; | |
30 | u16 segment; | |
31 | struct resource bus_range; | |
0b104773 | 32 | const struct pci_ecam_ops *ops; |
5b69b85b TN |
33 | struct resource cfgres; |
34 | }; | |
35 | ||
36 | #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \ | |
37 | ((end) - (start) + 1), \ | |
38 | NULL, IORESOURCE_BUS) | |
39 | #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff) | |
40 | ||
41 | static struct mcfg_fixup mcfg_quirks[] = { | |
42 | /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */ | |
2ca5b8dd | 43 | |
4166bfe5 JC |
44 | #define AL_ECAM(table_id, rev, seg, ops) \ |
45 | { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops } | |
46 | ||
47 | AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops), | |
48 | AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops), | |
49 | AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops), | |
50 | AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops), | |
51 | AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops), | |
52 | AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops), | |
53 | AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops), | |
54 | AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops), | |
55 | ||
2ca5b8dd CC |
56 | #define QCOM_ECAM32(seg) \ |
57 | { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops } | |
ced414a1 | 58 | |
2ca5b8dd CC |
59 | QCOM_ECAM32(0), |
60 | QCOM_ECAM32(1), | |
61 | QCOM_ECAM32(2), | |
62 | QCOM_ECAM32(3), | |
63 | QCOM_ECAM32(4), | |
64 | QCOM_ECAM32(5), | |
65 | QCOM_ECAM32(6), | |
66 | QCOM_ECAM32(7), | |
5f00f1a0 DL |
67 | |
68 | #define HISI_QUAD_DOM(table_id, seg, ops) \ | |
69 | { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \ | |
70 | { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \ | |
71 | { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \ | |
72 | { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops } | |
ced414a1 | 73 | |
5f00f1a0 DL |
74 | HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops), |
75 | HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops), | |
76 | HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops), | |
77 | HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops), | |
78 | HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops), | |
79 | HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops), | |
44f22bd9 TN |
80 | |
81 | #define THUNDER_PEM_RES(addr, node) \ | |
82 | DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M) | |
ced414a1 | 83 | |
44f22bd9 TN |
84 | #define THUNDER_PEM_QUIRK(rev, node) \ |
85 | { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \ | |
86 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ | |
87 | { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \ | |
88 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \ | |
89 | { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \ | |
90 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \ | |
91 | { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \ | |
92 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \ | |
93 | { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \ | |
94 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \ | |
95 | { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \ | |
96 | &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) } | |
648d93fc TN |
97 | |
98 | #define THUNDER_ECAM_QUIRK(rev, seg) \ | |
99 | { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \ | |
100 | &pci_thunder_ecam_ops } | |
ced414a1 BH |
101 | |
102 | /* SoC pass2.x */ | |
103 | THUNDER_PEM_QUIRK(1, 0), | |
104 | THUNDER_PEM_QUIRK(1, 1), | |
cd183740 | 105 | THUNDER_ECAM_QUIRK(1, 10), |
ced414a1 | 106 | |
648d93fc TN |
107 | /* SoC pass1.x */ |
108 | THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ | |
109 | THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */ | |
110 | THUNDER_ECAM_QUIRK(2, 0), | |
111 | THUNDER_ECAM_QUIRK(2, 1), | |
112 | THUNDER_ECAM_QUIRK(2, 2), | |
113 | THUNDER_ECAM_QUIRK(2, 3), | |
114 | THUNDER_ECAM_QUIRK(2, 10), | |
115 | THUNDER_ECAM_QUIRK(2, 11), | |
116 | THUNDER_ECAM_QUIRK(2, 12), | |
117 | THUNDER_ECAM_QUIRK(2, 13), | |
c5d46039 DD |
118 | |
119 | #define XGENE_V1_ECAM_MCFG(rev, seg) \ | |
120 | {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ | |
121 | &xgene_v1_pcie_ecam_ops } | |
ced414a1 | 122 | |
c5d46039 DD |
123 | #define XGENE_V2_ECAM_MCFG(rev, seg) \ |
124 | {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ | |
125 | &xgene_v2_pcie_ecam_ops } | |
ced414a1 | 126 | |
c5d46039 DD |
127 | /* X-Gene SoC with v1 PCIe controller */ |
128 | XGENE_V1_ECAM_MCFG(1, 0), | |
129 | XGENE_V1_ECAM_MCFG(1, 1), | |
130 | XGENE_V1_ECAM_MCFG(1, 2), | |
131 | XGENE_V1_ECAM_MCFG(1, 3), | |
132 | XGENE_V1_ECAM_MCFG(1, 4), | |
133 | XGENE_V1_ECAM_MCFG(2, 0), | |
134 | XGENE_V1_ECAM_MCFG(2, 1), | |
135 | XGENE_V1_ECAM_MCFG(2, 2), | |
136 | XGENE_V1_ECAM_MCFG(2, 3), | |
137 | XGENE_V1_ECAM_MCFG(2, 4), | |
138 | /* X-Gene SoC with v2.1 PCIe controller */ | |
139 | XGENE_V2_ECAM_MCFG(3, 0), | |
140 | XGENE_V2_ECAM_MCFG(3, 1), | |
141 | /* X-Gene SoC with v2.2 PCIe controller */ | |
142 | XGENE_V2_ECAM_MCFG(4, 0), | |
143 | XGENE_V2_ECAM_MCFG(4, 1), | |
144 | XGENE_V2_ECAM_MCFG(4, 2), | |
877c1a5f TP |
145 | |
146 | #define ALTRA_ECAM_QUIRK(rev, seg) \ | |
147 | { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops } | |
148 | ||
149 | ALTRA_ECAM_QUIRK(1, 0), | |
150 | ALTRA_ECAM_QUIRK(1, 1), | |
151 | ALTRA_ECAM_QUIRK(1, 2), | |
152 | ALTRA_ECAM_QUIRK(1, 3), | |
153 | ALTRA_ECAM_QUIRK(1, 4), | |
154 | ALTRA_ECAM_QUIRK(1, 5), | |
155 | ALTRA_ECAM_QUIRK(1, 6), | |
156 | ALTRA_ECAM_QUIRK(1, 7), | |
157 | ALTRA_ECAM_QUIRK(1, 8), | |
158 | ALTRA_ECAM_QUIRK(1, 9), | |
159 | ALTRA_ECAM_QUIRK(1, 10), | |
160 | ALTRA_ECAM_QUIRK(1, 11), | |
161 | ALTRA_ECAM_QUIRK(1, 12), | |
162 | ALTRA_ECAM_QUIRK(1, 13), | |
163 | ALTRA_ECAM_QUIRK(1, 14), | |
164 | ALTRA_ECAM_QUIRK(1, 15), | |
5b69b85b TN |
165 | }; |
166 | ||
167 | static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; | |
168 | static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
169 | static u32 mcfg_oem_revision; | |
170 | ||
171 | static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment, | |
172 | struct resource *bus_range) | |
173 | { | |
174 | if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) && | |
175 | !memcmp(f->oem_table_id, mcfg_oem_table_id, | |
c6237b21 | 176 | ACPI_OEM_TABLE_ID_SIZE) && |
5b69b85b TN |
177 | f->oem_revision == mcfg_oem_revision && |
178 | f->segment == segment && | |
179 | resource_contains(&f->bus_range, bus_range)) | |
180 | return 1; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | #endif | |
185 | ||
186 | static void pci_mcfg_apply_quirks(struct acpi_pci_root *root, | |
187 | struct resource *cfgres, | |
0b104773 | 188 | const struct pci_ecam_ops **ecam_ops) |
5b69b85b TN |
189 | { |
190 | #ifdef CONFIG_PCI_QUIRKS | |
191 | u16 segment = root->segment; | |
192 | struct resource *bus_range = &root->secondary; | |
193 | struct mcfg_fixup *f; | |
194 | int i; | |
195 | ||
196 | for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) { | |
197 | if (pci_mcfg_quirk_matches(f, segment, bus_range)) { | |
198 | if (f->cfgres.start) | |
199 | *cfgres = f->cfgres; | |
200 | if (f->ops) | |
201 | *ecam_ops = f->ops; | |
202 | dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n", | |
203 | cfgres, bus_range, *ecam_ops); | |
204 | return; | |
205 | } | |
206 | } | |
207 | #endif | |
208 | } | |
209 | ||
935c760e TN |
210 | /* List to save MCFG entries */ |
211 | static LIST_HEAD(pci_mcfg_list); | |
212 | ||
13983eb8 | 213 | int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, |
0b104773 | 214 | const struct pci_ecam_ops **ecam_ops) |
935c760e | 215 | { |
0b104773 | 216 | const struct pci_ecam_ops *ops = &pci_generic_ecam_ops; |
13983eb8 TN |
217 | struct resource *bus_res = &root->secondary; |
218 | u16 seg = root->segment; | |
935c760e | 219 | struct mcfg_entry *e; |
13983eb8 TN |
220 | struct resource res; |
221 | ||
222 | /* Use address from _CBA if present, otherwise lookup MCFG */ | |
223 | if (root->mcfg_addr) | |
224 | goto skip_lookup; | |
935c760e TN |
225 | |
226 | /* | |
53762ba8 | 227 | * We expect the range in bus_res in the coverage of MCFG bus range. |
935c760e TN |
228 | */ |
229 | list_for_each_entry(e, &pci_mcfg_list, list) { | |
53762ba8 | 230 | if (e->segment == seg && e->bus_start <= bus_res->start && |
13983eb8 TN |
231 | e->bus_end >= bus_res->end) { |
232 | root->mcfg_addr = e->addr; | |
233 | } | |
234 | ||
935c760e TN |
235 | } |
236 | ||
13983eb8 TN |
237 | skip_lookup: |
238 | memset(&res, 0, sizeof(res)); | |
5b69b85b TN |
239 | if (root->mcfg_addr) { |
240 | res.start = root->mcfg_addr + (bus_res->start << 20); | |
241 | res.end = res.start + (resource_size(bus_res) << 20) - 1; | |
242 | res.flags = IORESOURCE_MEM; | |
243 | } | |
244 | ||
245 | /* | |
246 | * Allow quirks to override default ECAM ops and CFG resource | |
247 | * range. This may even fabricate a CFG resource range in case | |
248 | * MCFG does not have it. Invalid CFG start address means MCFG | |
249 | * firmware bug or we need another quirk in array. | |
250 | */ | |
251 | pci_mcfg_apply_quirks(root, &res, &ops); | |
252 | if (!res.start) | |
253 | return -ENXIO; | |
254 | ||
13983eb8 TN |
255 | *cfgres = res; |
256 | *ecam_ops = ops; | |
935c760e TN |
257 | return 0; |
258 | } | |
259 | ||
260 | static __init int pci_mcfg_parse(struct acpi_table_header *header) | |
261 | { | |
262 | struct acpi_table_mcfg *mcfg; | |
263 | struct acpi_mcfg_allocation *mptr; | |
264 | struct mcfg_entry *e, *arr; | |
265 | int i, n; | |
266 | ||
267 | if (header->length < sizeof(struct acpi_table_mcfg)) | |
268 | return -EINVAL; | |
269 | ||
270 | n = (header->length - sizeof(struct acpi_table_mcfg)) / | |
271 | sizeof(struct acpi_mcfg_allocation); | |
272 | mcfg = (struct acpi_table_mcfg *)header; | |
273 | mptr = (struct acpi_mcfg_allocation *) &mcfg[1]; | |
274 | ||
275 | arr = kcalloc(n, sizeof(*arr), GFP_KERNEL); | |
276 | if (!arr) | |
277 | return -ENOMEM; | |
278 | ||
279 | for (i = 0, e = arr; i < n; i++, mptr++, e++) { | |
280 | e->segment = mptr->pci_segment; | |
281 | e->addr = mptr->address; | |
282 | e->bus_start = mptr->start_bus_number; | |
283 | e->bus_end = mptr->end_bus_number; | |
284 | list_add(&e->list, &pci_mcfg_list); | |
285 | } | |
286 | ||
5b69b85b TN |
287 | #ifdef CONFIG_PCI_QUIRKS |
288 | /* Save MCFG IDs and revision for quirks matching */ | |
289 | memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE); | |
290 | memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE); | |
291 | mcfg_oem_revision = header->oem_revision; | |
292 | #endif | |
293 | ||
935c760e TN |
294 | pr_info("MCFG table detected, %d entries\n", n); |
295 | return 0; | |
296 | } | |
297 | ||
298 | /* Interface called by ACPI - parse and save MCFG table */ | |
299 | void __init pci_mmcfg_late_init(void) | |
300 | { | |
301 | int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse); | |
302 | if (err) | |
d24e1245 | 303 | pr_debug("Failed to parse MCFG (%d)\n", err); |
935c760e | 304 | } |