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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
337aadff AC |
2 | /* |
3 | * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. | |
4 | * | |
5 | * (C) Copyright 2014, 2015 Linaro Ltd. | |
6 | * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> | |
7 | * | |
337aadff AC |
8 | * CPPC describes a few methods for controlling CPU performance using |
9 | * information from a per CPU table called CPC. This table is described in | |
10 | * the ACPI v5.0+ specification. The table consists of a list of | |
11 | * registers which may be memory mapped or hardware registers and also may | |
12 | * include some static integer values. | |
13 | * | |
14 | * CPU performance is on an abstract continuous scale as against a discretized | |
15 | * P-state scale which is tied to CPU frequency only. In brief, the basic | |
16 | * operation involves: | |
17 | * | |
18 | * - OS makes a CPU performance request. (Can provide min and max bounds) | |
19 | * | |
20 | * - Platform (such as BMC) is free to optimize request within requested bounds | |
21 | * depending on power/thermal budgets etc. | |
22 | * | |
23 | * - Platform conveys its decision back to OS | |
24 | * | |
25 | * The communication between OS and platform occurs through another medium | |
26 | * called (PCC) Platform Communication Channel. This is a generic mailbox like | |
27 | * mechanism which includes doorbell semantics to indicate register updates. | |
28 | * See drivers/mailbox/pcc.c for details on PCC. | |
29 | * | |
30 | * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and | |
31 | * above specifications. | |
32 | */ | |
33 | ||
34 | #define pr_fmt(fmt) "ACPI CPPC: " fmt | |
35 | ||
36 | #include <linux/cpufreq.h> | |
37 | #include <linux/delay.h> | |
58e1c035 | 38 | #include <linux/iopoll.h> |
ad62e1e6 | 39 | #include <linux/ktime.h> |
80b8286a PP |
40 | #include <linux/rwsem.h> |
41 | #include <linux/wait.h> | |
41ea6672 | 42 | #include <linux/topology.h> |
337aadff AC |
43 | |
44 | #include <acpi/cppc_acpi.h> | |
80b8286a | 45 | |
8482ef8c PP |
46 | struct cppc_pcc_data { |
47 | struct mbox_chan *pcc_channel; | |
48 | void __iomem *pcc_comm_addr; | |
8482ef8c | 49 | bool pcc_channel_acquired; |
58e1c035 | 50 | unsigned int deadline_us; |
8482ef8c | 51 | unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; |
80b8286a | 52 | |
8482ef8c | 53 | bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ |
139aee73 | 54 | bool platform_owns_pcc; /* Ownership of PCC subspace */ |
8482ef8c | 55 | unsigned int pcc_write_cnt; /* Running count of PCC write commands */ |
80b8286a | 56 | |
8482ef8c PP |
57 | /* |
58 | * Lock to provide controlled access to the PCC channel. | |
59 | * | |
60 | * For performance critical usecases(currently cppc_set_perf) | |
61 | * We need to take read_lock and check if channel belongs to OSPM | |
62 | * before reading or writing to PCC subspace | |
63 | * We need to take write_lock before transferring the channel | |
64 | * ownership to the platform via a Doorbell | |
65 | * This allows us to batch a number of CPPC requests if they happen | |
66 | * to originate in about the same time | |
67 | * | |
68 | * For non-performance critical usecases(init) | |
69 | * Take write_lock for all purposes which gives exclusive access | |
70 | */ | |
71 | struct rw_semaphore pcc_lock; | |
72 | ||
73 | /* Wait queue for CPUs whose requests were batched */ | |
74 | wait_queue_head_t pcc_write_wait_q; | |
85b1407b GC |
75 | ktime_t last_cmd_cmpl_time; |
76 | ktime_t last_mpar_reset; | |
77 | int mpar_count; | |
78 | int refcount; | |
8482ef8c | 79 | }; |
80b8286a | 80 | |
603fadf3 | 81 | /* Array to represent the PCC channel per subspace ID */ |
85b1407b | 82 | static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; |
603fadf3 | 83 | /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ |
85b1407b | 84 | static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); |
337aadff AC |
85 | |
86 | /* | |
87 | * The cpc_desc structure contains the ACPI register details | |
88 | * as described in the per CPU _CPC tables. The details | |
89 | * include the type of register (e.g. PCC, System IO, FFH etc.) | |
90 | * and destination addresses which lets us READ/WRITE CPU performance | |
91 | * information using the appropriate I/O methods. | |
92 | */ | |
93 | static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); | |
94 | ||
77e3d86f | 95 | /* pcc mapped address + header size + offset within PCC subspace */ |
85b1407b GC |
96 | #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ |
97 | 0x8 + (offs)) | |
77e3d86f | 98 | |
ad61dd30 | 99 | /* Check if a CPC register is in PCC */ |
80b8286a PP |
100 | #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ |
101 | (cpc)->cpc_entry.reg.space_id == \ | |
102 | ACPI_ADR_SPACE_PLATFORM_COMM) | |
103 | ||
158c998e AC |
104 | /* Evalutes to True if reg is a NULL register descriptor */ |
105 | #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ | |
106 | (reg)->address == 0 && \ | |
107 | (reg)->bit_width == 0 && \ | |
108 | (reg)->bit_offset == 0 && \ | |
109 | (reg)->access_width == 0) | |
110 | ||
111 | /* Evalutes to True if an optional cpc field is supported */ | |
112 | #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ | |
113 | !!(cpc)->cpc_entry.int_value : \ | |
114 | !IS_NULL_REG(&(cpc)->cpc_entry.reg)) | |
337aadff AC |
115 | /* |
116 | * Arbitrary Retries in case the remote processor is slow to respond | |
ad62e1e6 AC |
117 | * to PCC commands. Keeping it high enough to cover emulators where |
118 | * the processors run painfully slow. | |
337aadff | 119 | */ |
b52f4511 | 120 | #define NUM_RETRIES 500ULL |
337aadff | 121 | |
158c998e AC |
122 | struct cppc_attr { |
123 | struct attribute attr; | |
124 | ssize_t (*show)(struct kobject *kobj, | |
125 | struct attribute *attr, char *buf); | |
126 | ssize_t (*store)(struct kobject *kobj, | |
127 | struct attribute *attr, const char *c, ssize_t count); | |
128 | }; | |
129 | ||
130 | #define define_one_cppc_ro(_name) \ | |
131 | static struct cppc_attr _name = \ | |
132 | __ATTR(_name, 0444, show_##_name, NULL) | |
133 | ||
134 | #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) | |
135 | ||
2c74d847 PP |
136 | #define show_cppc_data(access_fn, struct_name, member_name) \ |
137 | static ssize_t show_##member_name(struct kobject *kobj, \ | |
138 | struct attribute *attr, char *buf) \ | |
139 | { \ | |
140 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ | |
141 | struct struct_name st_name = {0}; \ | |
142 | int ret; \ | |
143 | \ | |
144 | ret = access_fn(cpc_ptr->cpu_id, &st_name); \ | |
145 | if (ret) \ | |
146 | return ret; \ | |
147 | \ | |
148 | return scnprintf(buf, PAGE_SIZE, "%llu\n", \ | |
149 | (u64)st_name.member_name); \ | |
150 | } \ | |
151 | define_one_cppc_ro(member_name) | |
152 | ||
153 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); | |
154 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); | |
155 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); | |
156 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); | |
4773e77c PP |
157 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); |
158 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); | |
159 | ||
2c74d847 PP |
160 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); |
161 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); | |
162 | ||
158c998e AC |
163 | static ssize_t show_feedback_ctrs(struct kobject *kobj, |
164 | struct attribute *attr, char *buf) | |
165 | { | |
166 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
167 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
2c74d847 | 168 | int ret; |
158c998e | 169 | |
2c74d847 PP |
170 | ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); |
171 | if (ret) | |
172 | return ret; | |
158c998e AC |
173 | |
174 | return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", | |
175 | fb_ctrs.reference, fb_ctrs.delivered); | |
176 | } | |
177 | define_one_cppc_ro(feedback_ctrs); | |
178 | ||
158c998e AC |
179 | static struct attribute *cppc_attrs[] = { |
180 | &feedback_ctrs.attr, | |
181 | &reference_perf.attr, | |
182 | &wraparound_time.attr, | |
2c74d847 PP |
183 | &highest_perf.attr, |
184 | &lowest_perf.attr, | |
185 | &lowest_nonlinear_perf.attr, | |
186 | &nominal_perf.attr, | |
4773e77c PP |
187 | &nominal_freq.attr, |
188 | &lowest_freq.attr, | |
158c998e AC |
189 | NULL |
190 | }; | |
191 | ||
192 | static struct kobj_type cppc_ktype = { | |
193 | .sysfs_ops = &kobj_sysfs_ops, | |
194 | .default_attrs = cppc_attrs, | |
195 | }; | |
196 | ||
85b1407b | 197 | static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) |
ad62e1e6 | 198 | { |
58e1c035 | 199 | int ret, status; |
85b1407b GC |
200 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
201 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = | |
202 | pcc_ss_data->pcc_comm_addr; | |
ad62e1e6 | 203 | |
85b1407b | 204 | if (!pcc_ss_data->platform_owns_pcc) |
139aee73 PP |
205 | return 0; |
206 | ||
58e1c035 PP |
207 | /* |
208 | * Poll PCC status register every 3us(delay_us) for maximum of | |
209 | * deadline_us(timeout_us) until PCC command complete bit is set(cond) | |
210 | */ | |
211 | ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, | |
212 | status & PCC_CMD_COMPLETE_MASK, 3, | |
213 | pcc_ss_data->deadline_us); | |
ad62e1e6 | 214 | |
58e1c035 | 215 | if (likely(!ret)) { |
85b1407b | 216 | pcc_ss_data->platform_owns_pcc = false; |
58e1c035 PP |
217 | if (chk_err_bit && (status & PCC_ERROR_MASK)) |
218 | ret = -EIO; | |
219 | } | |
220 | ||
221 | if (unlikely(ret)) | |
222 | pr_err("PCC check channel failed for ss: %d. ret=%d\n", | |
223 | pcc_ss_id, ret); | |
139aee73 | 224 | |
ad62e1e6 AC |
225 | return ret; |
226 | } | |
227 | ||
80b8286a PP |
228 | /* |
229 | * This function transfers the ownership of the PCC to the platform | |
230 | * So it must be called while holding write_lock(pcc_lock) | |
231 | */ | |
85b1407b | 232 | static int send_pcc_cmd(int pcc_ss_id, u16 cmd) |
337aadff | 233 | { |
80b8286a | 234 | int ret = -EIO, i; |
85b1407b | 235 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
337aadff | 236 | struct acpi_pcct_shared_memory *generic_comm_base = |
85b1407b | 237 | (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr; |
f387e5b9 | 238 | unsigned int time_delta; |
337aadff | 239 | |
ad62e1e6 AC |
240 | /* |
241 | * For CMD_WRITE we know for a fact the caller should have checked | |
242 | * the channel before writing to PCC space | |
243 | */ | |
244 | if (cmd == CMD_READ) { | |
80b8286a PP |
245 | /* |
246 | * If there are pending cpc_writes, then we stole the channel | |
247 | * before write completion, so first send a WRITE command to | |
248 | * platform | |
249 | */ | |
85b1407b GC |
250 | if (pcc_ss_data->pending_pcc_write_cmd) |
251 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
80b8286a | 252 | |
85b1407b | 253 | ret = check_pcc_chan(pcc_ss_id, false); |
ad62e1e6 | 254 | if (ret) |
80b8286a PP |
255 | goto end; |
256 | } else /* CMD_WRITE */ | |
85b1407b | 257 | pcc_ss_data->pending_pcc_write_cmd = FALSE; |
337aadff | 258 | |
f387e5b9 PP |
259 | /* |
260 | * Handle the Minimum Request Turnaround Time(MRTT) | |
261 | * "The minimum amount of time that OSPM must wait after the completion | |
262 | * of a command before issuing the next command, in microseconds" | |
263 | */ | |
85b1407b GC |
264 | if (pcc_ss_data->pcc_mrtt) { |
265 | time_delta = ktime_us_delta(ktime_get(), | |
266 | pcc_ss_data->last_cmd_cmpl_time); | |
267 | if (pcc_ss_data->pcc_mrtt > time_delta) | |
268 | udelay(pcc_ss_data->pcc_mrtt - time_delta); | |
f387e5b9 PP |
269 | } |
270 | ||
271 | /* | |
272 | * Handle the non-zero Maximum Periodic Access Rate(MPAR) | |
273 | * "The maximum number of periodic requests that the subspace channel can | |
274 | * support, reported in commands per minute. 0 indicates no limitation." | |
275 | * | |
276 | * This parameter should be ideally zero or large enough so that it can | |
277 | * handle maximum number of requests that all the cores in the system can | |
278 | * collectively generate. If it is not, we will follow the spec and just | |
279 | * not send the request to the platform after hitting the MPAR limit in | |
280 | * any 60s window | |
281 | */ | |
85b1407b GC |
282 | if (pcc_ss_data->pcc_mpar) { |
283 | if (pcc_ss_data->mpar_count == 0) { | |
284 | time_delta = ktime_ms_delta(ktime_get(), | |
285 | pcc_ss_data->last_mpar_reset); | |
286 | if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { | |
d29abc83 GC |
287 | pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", |
288 | pcc_ss_id); | |
80b8286a PP |
289 | ret = -EIO; |
290 | goto end; | |
f387e5b9 | 291 | } |
85b1407b GC |
292 | pcc_ss_data->last_mpar_reset = ktime_get(); |
293 | pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; | |
f387e5b9 | 294 | } |
85b1407b | 295 | pcc_ss_data->mpar_count--; |
f387e5b9 PP |
296 | } |
297 | ||
337aadff | 298 | /* Write to the shared comm region. */ |
beee23ae | 299 | writew_relaxed(cmd, &generic_comm_base->command); |
337aadff AC |
300 | |
301 | /* Flip CMD COMPLETE bit */ | |
beee23ae | 302 | writew_relaxed(0, &generic_comm_base->status); |
337aadff | 303 | |
85b1407b | 304 | pcc_ss_data->platform_owns_pcc = true; |
139aee73 | 305 | |
337aadff | 306 | /* Ring doorbell */ |
85b1407b | 307 | ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd); |
ad62e1e6 | 308 | if (ret < 0) { |
d29abc83 GC |
309 | pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", |
310 | pcc_ss_id, cmd, ret); | |
80b8286a | 311 | goto end; |
337aadff AC |
312 | } |
313 | ||
139aee73 | 314 | /* wait for completion and check for PCC errro bit */ |
85b1407b | 315 | ret = check_pcc_chan(pcc_ss_id, true); |
139aee73 | 316 | |
85b1407b GC |
317 | if (pcc_ss_data->pcc_mrtt) |
318 | pcc_ss_data->last_cmd_cmpl_time = ktime_get(); | |
337aadff | 319 | |
85b1407b GC |
320 | if (pcc_ss_data->pcc_channel->mbox->txdone_irq) |
321 | mbox_chan_txdone(pcc_ss_data->pcc_channel, ret); | |
b59c4b3d | 322 | else |
85b1407b | 323 | mbox_client_txdone(pcc_ss_data->pcc_channel, ret); |
80b8286a PP |
324 | |
325 | end: | |
326 | if (cmd == CMD_WRITE) { | |
327 | if (unlikely(ret)) { | |
328 | for_each_possible_cpu(i) { | |
329 | struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); | |
330 | if (!desc) | |
331 | continue; | |
332 | ||
85b1407b | 333 | if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) |
80b8286a PP |
334 | desc->write_cmd_status = ret; |
335 | } | |
336 | } | |
85b1407b GC |
337 | pcc_ss_data->pcc_write_cnt++; |
338 | wake_up_all(&pcc_ss_data->pcc_write_wait_q); | |
80b8286a PP |
339 | } |
340 | ||
ad62e1e6 | 341 | return ret; |
337aadff AC |
342 | } |
343 | ||
344 | static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) | |
345 | { | |
ad62e1e6 | 346 | if (ret < 0) |
337aadff AC |
347 | pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", |
348 | *(u16 *)msg, ret); | |
349 | else | |
350 | pr_debug("TX completed. CMD sent:%x, ret:%d\n", | |
351 | *(u16 *)msg, ret); | |
352 | } | |
353 | ||
5c447c18 | 354 | static struct mbox_client cppc_mbox_cl = { |
337aadff AC |
355 | .tx_done = cppc_chan_tx_done, |
356 | .knows_txdone = true, | |
357 | }; | |
358 | ||
359 | static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) | |
360 | { | |
361 | int result = -EFAULT; | |
362 | acpi_status status = AE_OK; | |
363 | struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; | |
364 | struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; | |
365 | struct acpi_buffer state = {0, NULL}; | |
366 | union acpi_object *psd = NULL; | |
367 | struct acpi_psd_package *pdomain; | |
368 | ||
4c4cdc4c AS |
369 | status = acpi_evaluate_object_typed(handle, "_PSD", NULL, |
370 | &buffer, ACPI_TYPE_PACKAGE); | |
371 | if (status == AE_NOT_FOUND) /* _PSD is optional */ | |
372 | return 0; | |
337aadff AC |
373 | if (ACPI_FAILURE(status)) |
374 | return -ENODEV; | |
375 | ||
376 | psd = buffer.pointer; | |
377 | if (!psd || psd->package.count != 1) { | |
378 | pr_debug("Invalid _PSD data\n"); | |
379 | goto end; | |
380 | } | |
381 | ||
382 | pdomain = &(cpc_ptr->domain_info); | |
383 | ||
384 | state.length = sizeof(struct acpi_psd_package); | |
385 | state.pointer = pdomain; | |
386 | ||
387 | status = acpi_extract_package(&(psd->package.elements[0]), | |
388 | &format, &state); | |
389 | if (ACPI_FAILURE(status)) { | |
390 | pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); | |
391 | goto end; | |
392 | } | |
393 | ||
394 | if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { | |
395 | pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); | |
396 | goto end; | |
397 | } | |
398 | ||
399 | if (pdomain->revision != ACPI_PSD_REV0_REVISION) { | |
400 | pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); | |
401 | goto end; | |
402 | } | |
403 | ||
404 | if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && | |
405 | pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && | |
406 | pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { | |
407 | pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); | |
408 | goto end; | |
409 | } | |
410 | ||
411 | result = 0; | |
412 | end: | |
413 | kfree(buffer.pointer); | |
414 | return result; | |
415 | } | |
416 | ||
a28b2bfc IV |
417 | bool acpi_cpc_valid(void) |
418 | { | |
419 | struct cpc_desc *cpc_ptr; | |
420 | int cpu; | |
421 | ||
422 | for_each_possible_cpu(cpu) { | |
423 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); | |
424 | if (!cpc_ptr) | |
425 | return false; | |
426 | } | |
427 | ||
428 | return true; | |
429 | } | |
430 | EXPORT_SYMBOL_GPL(acpi_cpc_valid); | |
431 | ||
337aadff | 432 | /** |
a28b2bfc IV |
433 | * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu |
434 | * @cpu: Find all CPUs that share a domain with cpu. | |
435 | * @cpu_data: Pointer to CPU specific CPPC data including PSD info. | |
337aadff AC |
436 | * |
437 | * Return: 0 for success or negative value for err. | |
438 | */ | |
a28b2bfc | 439 | int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) |
337aadff | 440 | { |
337aadff | 441 | struct cpc_desc *cpc_ptr, *match_cpc_ptr; |
a28b2bfc IV |
442 | struct acpi_psd_package *match_pdomain; |
443 | struct acpi_psd_package *pdomain; | |
444 | int count_target, i; | |
337aadff AC |
445 | |
446 | /* | |
603fadf3 | 447 | * Now that we have _PSD data from all CPUs, let's setup P-state |
337aadff AC |
448 | * domain info. |
449 | */ | |
a28b2bfc IV |
450 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); |
451 | if (!cpc_ptr) | |
452 | return -EFAULT; | |
337aadff | 453 | |
a28b2bfc IV |
454 | pdomain = &(cpc_ptr->domain_info); |
455 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
456 | if (pdomain->num_processors <= 1) | |
457 | return 0; | |
337aadff | 458 | |
a28b2bfc IV |
459 | /* Validate the Domain info */ |
460 | count_target = pdomain->num_processors; | |
461 | if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) | |
462 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
463 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) | |
464 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW; | |
465 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) | |
466 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
337aadff | 467 | |
a28b2bfc IV |
468 | for_each_possible_cpu(i) { |
469 | if (i == cpu) | |
470 | continue; | |
337aadff | 471 | |
a28b2bfc IV |
472 | match_cpc_ptr = per_cpu(cpc_desc_ptr, i); |
473 | if (!match_cpc_ptr) | |
474 | goto err_fault; | |
337aadff | 475 | |
a28b2bfc IV |
476 | match_pdomain = &(match_cpc_ptr->domain_info); |
477 | if (match_pdomain->domain != pdomain->domain) | |
478 | continue; | |
337aadff | 479 | |
a28b2bfc IV |
480 | /* Here i and cpu are in the same domain */ |
481 | if (match_pdomain->num_processors != count_target) | |
482 | goto err_fault; | |
337aadff | 483 | |
a28b2bfc IV |
484 | if (pdomain->coord_type != match_pdomain->coord_type) |
485 | goto err_fault; | |
337aadff | 486 | |
a28b2bfc | 487 | cpumask_set_cpu(i, cpu_data->shared_cpu_map); |
337aadff AC |
488 | } |
489 | ||
a28b2bfc | 490 | return 0; |
337aadff | 491 | |
a28b2bfc IV |
492 | err_fault: |
493 | /* Assume no coordination on any error parsing domain info */ | |
494 | cpumask_clear(cpu_data->shared_cpu_map); | |
495 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
496 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE; | |
497 | ||
498 | return -EFAULT; | |
337aadff AC |
499 | } |
500 | EXPORT_SYMBOL_GPL(acpi_get_psd_map); | |
501 | ||
85b1407b | 502 | static int register_pcc_channel(int pcc_ss_idx) |
337aadff | 503 | { |
d29d6735 | 504 | struct acpi_pcct_hw_reduced *cppc_ss; |
ad62e1e6 | 505 | u64 usecs_lat; |
337aadff | 506 | |
85b1407b GC |
507 | if (pcc_ss_idx >= 0) { |
508 | pcc_data[pcc_ss_idx]->pcc_channel = | |
509 | pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); | |
337aadff | 510 | |
85b1407b | 511 | if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) { |
d29abc83 GC |
512 | pr_err("Failed to find PCC channel for subspace %d\n", |
513 | pcc_ss_idx); | |
337aadff AC |
514 | return -ENODEV; |
515 | } | |
516 | ||
517 | /* | |
518 | * The PCC mailbox controller driver should | |
519 | * have parsed the PCCT (global table of all | |
520 | * PCC channels) and stored pointers to the | |
521 | * subspace communication region in con_priv. | |
522 | */ | |
85b1407b | 523 | cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv; |
337aadff AC |
524 | |
525 | if (!cppc_ss) { | |
d29abc83 GC |
526 | pr_err("No PCC subspace found for %d CPPC\n", |
527 | pcc_ss_idx); | |
337aadff AC |
528 | return -ENODEV; |
529 | } | |
530 | ||
ad62e1e6 AC |
531 | /* |
532 | * cppc_ss->latency is just a Nominal value. In reality | |
533 | * the remote processor could be much slower to reply. | |
534 | * So add an arbitrary amount of wait on top of Nominal. | |
535 | */ | |
536 | usecs_lat = NUM_RETRIES * cppc_ss->latency; | |
58e1c035 | 537 | pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; |
85b1407b GC |
538 | pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time; |
539 | pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate; | |
540 | pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency; | |
541 | ||
542 | pcc_data[pcc_ss_idx]->pcc_comm_addr = | |
543 | acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length); | |
544 | if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { | |
d29abc83 GC |
545 | pr_err("Failed to ioremap PCC comm region mem for %d\n", |
546 | pcc_ss_idx); | |
337aadff AC |
547 | return -ENOMEM; |
548 | } | |
549 | ||
603fadf3 | 550 | /* Set flag so that we don't come here for each CPU. */ |
85b1407b | 551 | pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; |
337aadff AC |
552 | } |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
a6cbcdd5 SP |
557 | /** |
558 | * cpc_ffh_supported() - check if FFH reading supported | |
559 | * | |
560 | * Check if the architecture has support for functional fixed hardware | |
561 | * read/write capability. | |
562 | * | |
563 | * Return: true for supported, false for not supported | |
564 | */ | |
565 | bool __weak cpc_ffh_supported(void) | |
566 | { | |
567 | return false; | |
568 | } | |
569 | ||
85b1407b GC |
570 | /** |
571 | * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace | |
572 | * | |
573 | * Check and allocate the cppc_pcc_data memory. | |
574 | * In some processor configurations it is possible that same subspace | |
603fadf3 | 575 | * is shared between multiple CPUs. This is seen especially in CPUs |
85b1407b GC |
576 | * with hardware multi-threading support. |
577 | * | |
578 | * Return: 0 for success, errno for failure | |
579 | */ | |
5c447c18 | 580 | static int pcc_data_alloc(int pcc_ss_id) |
85b1407b GC |
581 | { |
582 | if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) | |
583 | return -EINVAL; | |
584 | ||
585 | if (pcc_data[pcc_ss_id]) { | |
586 | pcc_data[pcc_ss_id]->refcount++; | |
587 | } else { | |
588 | pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), | |
589 | GFP_KERNEL); | |
590 | if (!pcc_data[pcc_ss_id]) | |
591 | return -ENOMEM; | |
592 | pcc_data[pcc_ss_id]->refcount++; | |
593 | } | |
594 | ||
595 | return 0; | |
596 | } | |
4773e77c PP |
597 | |
598 | /* Check if CPPC revision + num_ent combination is supported */ | |
599 | static bool is_cppc_supported(int revision, int num_ent) | |
600 | { | |
601 | int expected_num_ent; | |
602 | ||
603 | switch (revision) { | |
604 | case CPPC_V2_REV: | |
605 | expected_num_ent = CPPC_V2_NUM_ENT; | |
606 | break; | |
607 | case CPPC_V3_REV: | |
608 | expected_num_ent = CPPC_V3_NUM_ENT; | |
609 | break; | |
610 | default: | |
611 | pr_debug("Firmware exports unsupported CPPC revision: %d\n", | |
612 | revision); | |
613 | return false; | |
614 | } | |
615 | ||
616 | if (expected_num_ent != num_ent) { | |
617 | pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n", | |
618 | num_ent, expected_num_ent, revision); | |
619 | return false; | |
620 | } | |
621 | ||
622 | return true; | |
623 | } | |
624 | ||
337aadff AC |
625 | /* |
626 | * An example CPC table looks like the following. | |
627 | * | |
628 | * Name(_CPC, Package() | |
629 | * { | |
630 | * 17, | |
631 | * NumEntries | |
632 | * 1, | |
633 | * // Revision | |
634 | * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, | |
635 | * // Highest Performance | |
636 | * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, | |
637 | * // Nominal Performance | |
638 | * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, | |
639 | * // Lowest Nonlinear Performance | |
640 | * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, | |
641 | * // Lowest Performance | |
642 | * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, | |
643 | * // Guaranteed Performance Register | |
644 | * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, | |
645 | * // Desired Performance Register | |
646 | * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, | |
647 | * .. | |
648 | * .. | |
649 | * .. | |
650 | * | |
651 | * } | |
652 | * Each Register() encodes how to access that specific register. | |
653 | * e.g. a sample PCC entry has the following encoding: | |
654 | * | |
655 | * Register ( | |
656 | * PCC, | |
657 | * AddressSpaceKeyword | |
658 | * 8, | |
659 | * //RegisterBitWidth | |
660 | * 8, | |
661 | * //RegisterBitOffset | |
662 | * 0x30, | |
663 | * //RegisterAddress | |
664 | * 9 | |
665 | * //AccessSize (subspace ID) | |
666 | * 0 | |
667 | * ) | |
668 | * } | |
669 | */ | |
670 | ||
41ea6672 NF |
671 | #ifndef init_freq_invariance_cppc |
672 | static inline void init_freq_invariance_cppc(void) { } | |
673 | #endif | |
674 | ||
337aadff AC |
675 | /** |
676 | * acpi_cppc_processor_probe - Search for per CPU _CPC objects. | |
603fadf3 | 677 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
678 | * |
679 | * Return: 0 for success or negative value for err. | |
680 | */ | |
681 | int acpi_cppc_processor_probe(struct acpi_processor *pr) | |
682 | { | |
683 | struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; | |
684 | union acpi_object *out_obj, *cpc_obj; | |
685 | struct cpc_desc *cpc_ptr; | |
686 | struct cpc_reg *gas_t; | |
158c998e | 687 | struct device *cpu_dev; |
337aadff AC |
688 | acpi_handle handle = pr->handle; |
689 | unsigned int num_ent, i, cpc_rev; | |
85b1407b | 690 | int pcc_subspace_id = -1; |
337aadff AC |
691 | acpi_status status; |
692 | int ret = -EFAULT; | |
693 | ||
603fadf3 | 694 | /* Parse the ACPI _CPC table for this CPU. */ |
337aadff AC |
695 | status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, |
696 | ACPI_TYPE_PACKAGE); | |
697 | if (ACPI_FAILURE(status)) { | |
698 | ret = -ENODEV; | |
699 | goto out_buf_free; | |
700 | } | |
701 | ||
702 | out_obj = (union acpi_object *) output.pointer; | |
703 | ||
704 | cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); | |
705 | if (!cpc_ptr) { | |
706 | ret = -ENOMEM; | |
707 | goto out_buf_free; | |
708 | } | |
709 | ||
710 | /* First entry is NumEntries. */ | |
711 | cpc_obj = &out_obj->package.elements[0]; | |
712 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
713 | num_ent = cpc_obj->integer.value; | |
714 | } else { | |
715 | pr_debug("Unexpected entry type(%d) for NumEntries\n", | |
716 | cpc_obj->type); | |
717 | goto out_free; | |
718 | } | |
5bbb86aa AC |
719 | cpc_ptr->num_entries = num_ent; |
720 | ||
337aadff AC |
721 | /* Second entry should be revision. */ |
722 | cpc_obj = &out_obj->package.elements[1]; | |
723 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
724 | cpc_rev = cpc_obj->integer.value; | |
725 | } else { | |
726 | pr_debug("Unexpected entry type(%d) for Revision\n", | |
727 | cpc_obj->type); | |
728 | goto out_free; | |
729 | } | |
4773e77c | 730 | cpc_ptr->version = cpc_rev; |
337aadff | 731 | |
4773e77c | 732 | if (!is_cppc_supported(cpc_rev, num_ent)) |
337aadff | 733 | goto out_free; |
337aadff AC |
734 | |
735 | /* Iterate through remaining entries in _CPC */ | |
736 | for (i = 2; i < num_ent; i++) { | |
737 | cpc_obj = &out_obj->package.elements[i]; | |
738 | ||
739 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
740 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; | |
741 | cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; | |
742 | } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { | |
743 | gas_t = (struct cpc_reg *) | |
744 | cpc_obj->buffer.pointer; | |
745 | ||
746 | /* | |
747 | * The PCC Subspace index is encoded inside | |
748 | * the CPC table entries. The same PCC index | |
749 | * will be used for all the PCC entries, | |
750 | * so extract it only once. | |
751 | */ | |
752 | if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { | |
85b1407b GC |
753 | if (pcc_subspace_id < 0) { |
754 | pcc_subspace_id = gas_t->access_width; | |
755 | if (pcc_data_alloc(pcc_subspace_id)) | |
756 | goto out_free; | |
757 | } else if (pcc_subspace_id != gas_t->access_width) { | |
337aadff AC |
758 | pr_debug("Mismatched PCC ids.\n"); |
759 | goto out_free; | |
760 | } | |
5bbb86aa AC |
761 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
762 | if (gas_t->address) { | |
763 | void __iomem *addr; | |
764 | ||
765 | addr = ioremap(gas_t->address, gas_t->bit_width/8); | |
766 | if (!addr) | |
767 | goto out_free; | |
768 | cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; | |
769 | } | |
770 | } else { | |
a6cbcdd5 SP |
771 | if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { |
772 | /* Support only PCC ,SYS MEM and FFH type regs */ | |
773 | pr_debug("Unsupported register type: %d\n", gas_t->space_id); | |
774 | goto out_free; | |
775 | } | |
337aadff AC |
776 | } |
777 | ||
778 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; | |
779 | memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); | |
780 | } else { | |
781 | pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); | |
782 | goto out_free; | |
783 | } | |
784 | } | |
85b1407b | 785 | per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; |
4773e77c PP |
786 | |
787 | /* | |
788 | * Initialize the remaining cpc_regs as unsupported. | |
789 | * Example: In case FW exposes CPPC v2, the below loop will initialize | |
790 | * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported | |
791 | */ | |
792 | for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { | |
793 | cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; | |
794 | cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; | |
795 | } | |
796 | ||
797 | ||
337aadff AC |
798 | /* Store CPU Logical ID */ |
799 | cpc_ptr->cpu_id = pr->id; | |
800 | ||
337aadff AC |
801 | /* Parse PSD data for this CPU */ |
802 | ret = acpi_get_psd(cpc_ptr, handle); | |
803 | if (ret) | |
804 | goto out_free; | |
805 | ||
603fadf3 | 806 | /* Register PCC channel once for all PCC subspace ID. */ |
85b1407b GC |
807 | if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { |
808 | ret = register_pcc_channel(pcc_subspace_id); | |
337aadff AC |
809 | if (ret) |
810 | goto out_free; | |
8482ef8c | 811 | |
85b1407b GC |
812 | init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); |
813 | init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); | |
337aadff AC |
814 | } |
815 | ||
816 | /* Everything looks okay */ | |
817 | pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); | |
818 | ||
158c998e AC |
819 | /* Add per logical CPU nodes for reading its feedback counters. */ |
820 | cpu_dev = get_cpu_device(pr->id); | |
50163475 DC |
821 | if (!cpu_dev) { |
822 | ret = -EINVAL; | |
158c998e | 823 | goto out_free; |
50163475 | 824 | } |
158c998e | 825 | |
603fadf3 | 826 | /* Plug PSD data into this CPU's CPC descriptor. */ |
28076483 RW |
827 | per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; |
828 | ||
158c998e AC |
829 | ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, |
830 | "acpi_cppc"); | |
28076483 RW |
831 | if (ret) { |
832 | per_cpu(cpc_desc_ptr, pr->id) = NULL; | |
4d8be4bc | 833 | kobject_put(&cpc_ptr->kobj); |
158c998e | 834 | goto out_free; |
28076483 | 835 | } |
158c998e | 836 | |
41ea6672 NF |
837 | init_freq_invariance_cppc(); |
838 | ||
337aadff AC |
839 | kfree(output.pointer); |
840 | return 0; | |
841 | ||
842 | out_free: | |
5bbb86aa AC |
843 | /* Free all the mapped sys mem areas for this CPU */ |
844 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
845 | void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
846 | ||
847 | if (addr) | |
848 | iounmap(addr); | |
849 | } | |
337aadff AC |
850 | kfree(cpc_ptr); |
851 | ||
852 | out_buf_free: | |
853 | kfree(output.pointer); | |
854 | return ret; | |
855 | } | |
856 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); | |
857 | ||
858 | /** | |
859 | * acpi_cppc_processor_exit - Cleanup CPC structs. | |
603fadf3 | 860 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
861 | * |
862 | * Return: Void | |
863 | */ | |
864 | void acpi_cppc_processor_exit(struct acpi_processor *pr) | |
865 | { | |
866 | struct cpc_desc *cpc_ptr; | |
5bbb86aa AC |
867 | unsigned int i; |
868 | void __iomem *addr; | |
85b1407b GC |
869 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); |
870 | ||
871 | if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) { | |
872 | if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { | |
873 | pcc_data[pcc_ss_id]->refcount--; | |
874 | if (!pcc_data[pcc_ss_id]->refcount) { | |
875 | pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); | |
85b1407b | 876 | kfree(pcc_data[pcc_ss_id]); |
56a0b978 | 877 | pcc_data[pcc_ss_id] = NULL; |
85b1407b GC |
878 | } |
879 | } | |
880 | } | |
158c998e | 881 | |
337aadff | 882 | cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); |
9e9d68da SAS |
883 | if (!cpc_ptr) |
884 | return; | |
5bbb86aa AC |
885 | |
886 | /* Free all the mapped sys mem areas for this CPU */ | |
887 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
888 | addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
889 | if (addr) | |
890 | iounmap(addr); | |
891 | } | |
892 | ||
158c998e | 893 | kobject_put(&cpc_ptr->kobj); |
337aadff AC |
894 | kfree(cpc_ptr); |
895 | } | |
896 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); | |
897 | ||
a6cbcdd5 SP |
898 | /** |
899 | * cpc_read_ffh() - Read FFH register | |
603fadf3 | 900 | * @cpunum: CPU number to read |
a6cbcdd5 SP |
901 | * @reg: cppc register information |
902 | * @val: place holder for return value | |
903 | * | |
904 | * Read bit_width bits from a specified address and bit_offset | |
905 | * | |
906 | * Return: 0 for success and error code | |
907 | */ | |
908 | int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | |
909 | { | |
910 | return -ENOTSUPP; | |
911 | } | |
912 | ||
913 | /** | |
914 | * cpc_write_ffh() - Write FFH register | |
603fadf3 | 915 | * @cpunum: CPU number to write |
a6cbcdd5 SP |
916 | * @reg: cppc register information |
917 | * @val: value to write | |
918 | * | |
919 | * Write value of bit_width bits to a specified address and bit_offset | |
920 | * | |
921 | * Return: 0 for success and error code | |
922 | */ | |
923 | int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | |
924 | { | |
925 | return -ENOTSUPP; | |
926 | } | |
927 | ||
77e3d86f PP |
928 | /* |
929 | * Since cpc_read and cpc_write are called while holding pcc_lock, it should be | |
930 | * as fast as possible. We have already mapped the PCC subspace during init, so | |
931 | * we can directly write to it. | |
932 | */ | |
337aadff | 933 | |
a6cbcdd5 | 934 | static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) |
337aadff | 935 | { |
77e3d86f | 936 | int ret_val = 0; |
5bbb86aa | 937 | void __iomem *vaddr = 0; |
85b1407b | 938 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa AC |
939 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
940 | ||
941 | if (reg_res->type == ACPI_TYPE_INTEGER) { | |
942 | *val = reg_res->cpc_entry.int_value; | |
943 | return ret_val; | |
944 | } | |
77e3d86f PP |
945 | |
946 | *val = 0; | |
1ecbd717 | 947 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) |
85b1407b | 948 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
949 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
950 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
951 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
952 | return cpc_read_ffh(cpu, reg, val); | |
5bbb86aa AC |
953 | else |
954 | return acpi_os_read_memory((acpi_physical_address)reg->address, | |
955 | val, reg->bit_width); | |
337aadff | 956 | |
5bbb86aa | 957 | switch (reg->bit_width) { |
77e3d86f | 958 | case 8: |
beee23ae | 959 | *val = readb_relaxed(vaddr); |
77e3d86f PP |
960 | break; |
961 | case 16: | |
beee23ae | 962 | *val = readw_relaxed(vaddr); |
77e3d86f PP |
963 | break; |
964 | case 32: | |
beee23ae | 965 | *val = readl_relaxed(vaddr); |
77e3d86f PP |
966 | break; |
967 | case 64: | |
beee23ae | 968 | *val = readq_relaxed(vaddr); |
77e3d86f PP |
969 | break; |
970 | default: | |
d29abc83 GC |
971 | pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", |
972 | reg->bit_width, pcc_ss_id); | |
77e3d86f | 973 | ret_val = -EFAULT; |
5bbb86aa AC |
974 | } |
975 | ||
77e3d86f | 976 | return ret_val; |
337aadff AC |
977 | } |
978 | ||
a6cbcdd5 | 979 | static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) |
337aadff | 980 | { |
77e3d86f | 981 | int ret_val = 0; |
5bbb86aa | 982 | void __iomem *vaddr = 0; |
85b1407b | 983 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa | 984 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
77e3d86f | 985 | |
1ecbd717 | 986 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) |
85b1407b | 987 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
988 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
989 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
990 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
991 | return cpc_write_ffh(cpu, reg, val); | |
5bbb86aa AC |
992 | else |
993 | return acpi_os_write_memory((acpi_physical_address)reg->address, | |
994 | val, reg->bit_width); | |
337aadff | 995 | |
5bbb86aa | 996 | switch (reg->bit_width) { |
77e3d86f | 997 | case 8: |
beee23ae | 998 | writeb_relaxed(val, vaddr); |
77e3d86f PP |
999 | break; |
1000 | case 16: | |
beee23ae | 1001 | writew_relaxed(val, vaddr); |
77e3d86f PP |
1002 | break; |
1003 | case 32: | |
beee23ae | 1004 | writel_relaxed(val, vaddr); |
77e3d86f PP |
1005 | break; |
1006 | case 64: | |
beee23ae | 1007 | writeq_relaxed(val, vaddr); |
77e3d86f PP |
1008 | break; |
1009 | default: | |
d29abc83 GC |
1010 | pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", |
1011 | reg->bit_width, pcc_ss_id); | |
77e3d86f PP |
1012 | ret_val = -EFAULT; |
1013 | break; | |
5bbb86aa AC |
1014 | } |
1015 | ||
77e3d86f | 1016 | return ret_val; |
337aadff AC |
1017 | } |
1018 | ||
1757d05f XW |
1019 | /** |
1020 | * cppc_get_desired_perf - Get the value of desired performance register. | |
1021 | * @cpunum: CPU from which to get desired performance. | |
1022 | * @desired_perf: address of a variable to store the returned desired performance | |
1023 | * | |
1024 | * Return: 0 for success, -EIO otherwise. | |
1025 | */ | |
1026 | int cppc_get_desired_perf(int cpunum, u64 *desired_perf) | |
1027 | { | |
1028 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
1029 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); | |
1030 | struct cpc_register_resource *desired_reg; | |
1031 | struct cppc_pcc_data *pcc_ss_data = NULL; | |
1032 | ||
1033 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1034 | ||
1035 | if (CPC_IN_PCC(desired_reg)) { | |
1036 | int ret = 0; | |
1037 | ||
1038 | if (pcc_ss_id < 0) | |
1039 | return -EIO; | |
1040 | ||
1041 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
1042 | ||
1043 | down_write(&pcc_ss_data->pcc_lock); | |
1044 | ||
1045 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) | |
1046 | cpc_read(cpunum, desired_reg, desired_perf); | |
1047 | else | |
1048 | ret = -EIO; | |
1049 | ||
1050 | up_write(&pcc_ss_data->pcc_lock); | |
1051 | ||
1052 | return ret; | |
1053 | } | |
1054 | ||
1055 | cpc_read(cpunum, desired_reg, desired_perf); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | EXPORT_SYMBOL_GPL(cppc_get_desired_perf); | |
1060 | ||
337aadff | 1061 | /** |
603fadf3 | 1062 | * cppc_get_perf_caps - Get a CPU's performance capabilities. |
337aadff AC |
1063 | * @cpunum: CPU from which to get capabilities info. |
1064 | * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h | |
1065 | * | |
1066 | * Return: 0 for success with perf_caps populated else -ERRNO. | |
1067 | */ | |
1068 | int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) | |
1069 | { | |
1070 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
368520a6 | 1071 | struct cpc_register_resource *highest_reg, *lowest_reg, |
29523f09 | 1072 | *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, |
4773e77c | 1073 | *low_freq_reg = NULL, *nom_freq_reg = NULL; |
29523f09 | 1074 | u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; |
85b1407b | 1075 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1076 | struct cppc_pcc_data *pcc_ss_data = NULL; |
850d64a4 | 1077 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1078 | |
6fa12d58 | 1079 | if (!cpc_desc) { |
337aadff AC |
1080 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1081 | return -ENODEV; | |
1082 | } | |
1083 | ||
1084 | highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; | |
1085 | lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; | |
368520a6 PP |
1086 | lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; |
1087 | nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
4773e77c PP |
1088 | low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; |
1089 | nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; | |
29523f09 | 1090 | guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; |
337aadff | 1091 | |
337aadff | 1092 | /* Are any of the regs PCC ?*/ |
80b8286a | 1093 | if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || |
4773e77c PP |
1094 | CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || |
1095 | CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { | |
6fa12d58 PP |
1096 | if (pcc_ss_id < 0) { |
1097 | pr_debug("Invalid pcc_ss_id\n"); | |
1098 | return -ENODEV; | |
1099 | } | |
1100 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
850d64a4 | 1101 | regs_in_pcc = 1; |
85b1407b | 1102 | down_write(&pcc_ss_data->pcc_lock); |
337aadff | 1103 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1104 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1105 | ret = -EIO; |
1106 | goto out_err; | |
1107 | } | |
1108 | } | |
1109 | ||
a6cbcdd5 | 1110 | cpc_read(cpunum, highest_reg, &high); |
337aadff AC |
1111 | perf_caps->highest_perf = high; |
1112 | ||
a6cbcdd5 | 1113 | cpc_read(cpunum, lowest_reg, &low); |
337aadff AC |
1114 | perf_caps->lowest_perf = low; |
1115 | ||
368520a6 | 1116 | cpc_read(cpunum, nominal_reg, &nom); |
337aadff AC |
1117 | perf_caps->nominal_perf = nom; |
1118 | ||
edef1ef1 SP |
1119 | if (guaranteed_reg->type != ACPI_TYPE_BUFFER || |
1120 | IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { | |
1121 | perf_caps->guaranteed_perf = 0; | |
1122 | } else { | |
1123 | cpc_read(cpunum, guaranteed_reg, &guaranteed); | |
1124 | perf_caps->guaranteed_perf = guaranteed; | |
1125 | } | |
29523f09 | 1126 | |
368520a6 PP |
1127 | cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); |
1128 | perf_caps->lowest_nonlinear_perf = min_nonlinear; | |
1129 | ||
1130 | if (!high || !low || !nom || !min_nonlinear) | |
337aadff AC |
1131 | ret = -EFAULT; |
1132 | ||
4773e77c PP |
1133 | /* Read optional lowest and nominal frequencies if present */ |
1134 | if (CPC_SUPPORTED(low_freq_reg)) | |
1135 | cpc_read(cpunum, low_freq_reg, &low_f); | |
1136 | ||
1137 | if (CPC_SUPPORTED(nom_freq_reg)) | |
1138 | cpc_read(cpunum, nom_freq_reg, &nom_f); | |
1139 | ||
1140 | perf_caps->lowest_freq = low_f; | |
1141 | perf_caps->nominal_freq = nom_f; | |
1142 | ||
1143 | ||
337aadff | 1144 | out_err: |
850d64a4 | 1145 | if (regs_in_pcc) |
85b1407b | 1146 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1147 | return ret; |
1148 | } | |
1149 | EXPORT_SYMBOL_GPL(cppc_get_perf_caps); | |
1150 | ||
1151 | /** | |
603fadf3 | 1152 | * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. |
337aadff AC |
1153 | * @cpunum: CPU from which to read counters. |
1154 | * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h | |
1155 | * | |
1156 | * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. | |
1157 | */ | |
1158 | int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) | |
1159 | { | |
1160 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
158c998e AC |
1161 | struct cpc_register_resource *delivered_reg, *reference_reg, |
1162 | *ref_perf_reg, *ctr_wrap_reg; | |
85b1407b | 1163 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1164 | struct cppc_pcc_data *pcc_ss_data = NULL; |
158c998e | 1165 | u64 delivered, reference, ref_perf, ctr_wrap_time; |
850d64a4 | 1166 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1167 | |
6fa12d58 | 1168 | if (!cpc_desc) { |
337aadff AC |
1169 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1170 | return -ENODEV; | |
1171 | } | |
1172 | ||
1173 | delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; | |
1174 | reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; | |
158c998e AC |
1175 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; |
1176 | ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; | |
1177 | ||
1178 | /* | |
603fadf3 | 1179 | * If reference perf register is not supported then we should |
158c998e AC |
1180 | * use the nominal perf value |
1181 | */ | |
1182 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1183 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
337aadff | 1184 | |
337aadff | 1185 | /* Are any of the regs PCC ?*/ |
158c998e AC |
1186 | if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || |
1187 | CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { | |
6fa12d58 PP |
1188 | if (pcc_ss_id < 0) { |
1189 | pr_debug("Invalid pcc_ss_id\n"); | |
1190 | return -ENODEV; | |
1191 | } | |
1192 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b | 1193 | down_write(&pcc_ss_data->pcc_lock); |
850d64a4 | 1194 | regs_in_pcc = 1; |
337aadff | 1195 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1196 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1197 | ret = -EIO; |
1198 | goto out_err; | |
1199 | } | |
1200 | } | |
1201 | ||
a6cbcdd5 SP |
1202 | cpc_read(cpunum, delivered_reg, &delivered); |
1203 | cpc_read(cpunum, reference_reg, &reference); | |
1204 | cpc_read(cpunum, ref_perf_reg, &ref_perf); | |
158c998e AC |
1205 | |
1206 | /* | |
1207 | * Per spec, if ctr_wrap_time optional register is unsupported, then the | |
1208 | * performance counters are assumed to never wrap during the lifetime of | |
1209 | * platform | |
1210 | */ | |
1211 | ctr_wrap_time = (u64)(~((u64)0)); | |
1212 | if (CPC_SUPPORTED(ctr_wrap_reg)) | |
a6cbcdd5 | 1213 | cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); |
337aadff | 1214 | |
158c998e | 1215 | if (!delivered || !reference || !ref_perf) { |
337aadff AC |
1216 | ret = -EFAULT; |
1217 | goto out_err; | |
1218 | } | |
1219 | ||
1220 | perf_fb_ctrs->delivered = delivered; | |
1221 | perf_fb_ctrs->reference = reference; | |
158c998e | 1222 | perf_fb_ctrs->reference_perf = ref_perf; |
2c74d847 | 1223 | perf_fb_ctrs->wraparound_time = ctr_wrap_time; |
337aadff | 1224 | out_err: |
850d64a4 | 1225 | if (regs_in_pcc) |
85b1407b | 1226 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1227 | return ret; |
1228 | } | |
1229 | EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); | |
1230 | ||
1231 | /** | |
603fadf3 | 1232 | * cppc_set_perf - Set a CPU's performance controls. |
337aadff AC |
1233 | * @cpu: CPU for which to set performance controls. |
1234 | * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h | |
1235 | * | |
1236 | * Return: 0 for success, -ERRNO otherwise. | |
1237 | */ | |
1238 | int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) | |
1239 | { | |
1240 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1241 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1242 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
6fa12d58 | 1243 | struct cppc_pcc_data *pcc_ss_data = NULL; |
337aadff AC |
1244 | int ret = 0; |
1245 | ||
6fa12d58 | 1246 | if (!cpc_desc) { |
337aadff AC |
1247 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); |
1248 | return -ENODEV; | |
1249 | } | |
1250 | ||
1251 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1252 | ||
80b8286a PP |
1253 | /* |
1254 | * This is Phase-I where we want to write to CPC registers | |
1255 | * -> We want all CPUs to be able to execute this phase in parallel | |
1256 | * | |
1257 | * Since read_lock can be acquired by multiple CPUs simultaneously we | |
1258 | * achieve that goal here | |
1259 | */ | |
1260 | if (CPC_IN_PCC(desired_reg)) { | |
6fa12d58 PP |
1261 | if (pcc_ss_id < 0) { |
1262 | pr_debug("Invalid pcc_ss_id\n"); | |
1263 | return -ENODEV; | |
1264 | } | |
1265 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1266 | down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ |
1267 | if (pcc_ss_data->platform_owns_pcc) { | |
1268 | ret = check_pcc_chan(pcc_ss_id, false); | |
80b8286a | 1269 | if (ret) { |
85b1407b | 1270 | up_read(&pcc_ss_data->pcc_lock); |
80b8286a PP |
1271 | return ret; |
1272 | } | |
80b8286a | 1273 | } |
139aee73 PP |
1274 | /* |
1275 | * Update the pending_write to make sure a PCC CMD_READ will not | |
1276 | * arrive and steal the channel during the switch to write lock | |
1277 | */ | |
85b1407b GC |
1278 | pcc_ss_data->pending_pcc_write_cmd = true; |
1279 | cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; | |
80b8286a | 1280 | cpc_desc->write_cmd_status = 0; |
ad62e1e6 AC |
1281 | } |
1282 | ||
337aadff AC |
1283 | /* |
1284 | * Skip writing MIN/MAX until Linux knows how to come up with | |
1285 | * useful values. | |
1286 | */ | |
a6cbcdd5 | 1287 | cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); |
337aadff | 1288 | |
80b8286a | 1289 | if (CPC_IN_PCC(desired_reg)) |
85b1407b | 1290 | up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ |
80b8286a PP |
1291 | /* |
1292 | * This is Phase-II where we transfer the ownership of PCC to Platform | |
1293 | * | |
1294 | * Short Summary: Basically if we think of a group of cppc_set_perf | |
1295 | * requests that happened in short overlapping interval. The last CPU to | |
1296 | * come out of Phase-I will enter Phase-II and ring the doorbell. | |
1297 | * | |
1298 | * We have the following requirements for Phase-II: | |
1299 | * 1. We want to execute Phase-II only when there are no CPUs | |
1300 | * currently executing in Phase-I | |
1301 | * 2. Once we start Phase-II we want to avoid all other CPUs from | |
1302 | * entering Phase-I. | |
1303 | * 3. We want only one CPU among all those who went through Phase-I | |
1304 | * to run phase-II | |
1305 | * | |
1306 | * If write_trylock fails to get the lock and doesn't transfer the | |
1307 | * PCC ownership to the platform, then one of the following will be TRUE | |
1308 | * 1. There is at-least one CPU in Phase-I which will later execute | |
1309 | * write_trylock, so the CPUs in Phase-I will be responsible for | |
1310 | * executing the Phase-II. | |
1311 | * 2. Some other CPU has beaten this CPU to successfully execute the | |
1312 | * write_trylock and has already acquired the write_lock. We know for a | |
603fadf3 | 1313 | * fact it (other CPU acquiring the write_lock) couldn't have happened |
80b8286a PP |
1314 | * before this CPU's Phase-I as we held the read_lock. |
1315 | * 3. Some other CPU executing pcc CMD_READ has stolen the | |
1316 | * down_write, in which case, send_pcc_cmd will check for pending | |
1317 | * CMD_WRITE commands by checking the pending_pcc_write_cmd. | |
1318 | * So this CPU can be certain that its request will be delivered | |
1319 | * So in all cases, this CPU knows that its request will be delivered | |
1320 | * by another CPU and can return | |
1321 | * | |
1322 | * After getting the down_write we still need to check for | |
1323 | * pending_pcc_write_cmd to take care of the following scenario | |
1324 | * The thread running this code could be scheduled out between | |
1325 | * Phase-I and Phase-II. Before it is scheduled back on, another CPU | |
1326 | * could have delivered the request to Platform by triggering the | |
1327 | * doorbell and transferred the ownership of PCC to platform. So this | |
1328 | * avoids triggering an unnecessary doorbell and more importantly before | |
1329 | * triggering the doorbell it makes sure that the PCC channel ownership | |
1330 | * is still with OSPM. | |
1331 | * pending_pcc_write_cmd can also be cleared by a different CPU, if | |
1332 | * there was a pcc CMD_READ waiting on down_write and it steals the lock | |
1333 | * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this | |
1334 | * case during a CMD_READ and if there are pending writes it delivers | |
1335 | * the write command before servicing the read command | |
1336 | */ | |
1337 | if (CPC_IN_PCC(desired_reg)) { | |
85b1407b | 1338 | if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ |
80b8286a | 1339 | /* Update only if there are pending write commands */ |
85b1407b GC |
1340 | if (pcc_ss_data->pending_pcc_write_cmd) |
1341 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
1342 | up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ | |
80b8286a PP |
1343 | } else |
1344 | /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ | |
85b1407b GC |
1345 | wait_event(pcc_ss_data->pcc_write_wait_q, |
1346 | cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); | |
80b8286a PP |
1347 | |
1348 | /* send_pcc_cmd updates the status in case of failure */ | |
1349 | ret = cpc_desc->write_cmd_status; | |
337aadff | 1350 | } |
337aadff AC |
1351 | return ret; |
1352 | } | |
1353 | EXPORT_SYMBOL_GPL(cppc_set_perf); | |
be8b88d7 PP |
1354 | |
1355 | /** | |
1356 | * cppc_get_transition_latency - returns frequency transition latency in ns | |
1357 | * | |
1358 | * ACPI CPPC does not explicitly specifiy how a platform can specify the | |
1359 | * transition latency for perfromance change requests. The closest we have | |
1360 | * is the timing information from the PCCT tables which provides the info | |
1361 | * on the number and frequency of PCC commands the platform can handle. | |
1362 | */ | |
1363 | unsigned int cppc_get_transition_latency(int cpu_num) | |
1364 | { | |
1365 | /* | |
1366 | * Expected transition latency is based on the PCCT timing values | |
1367 | * Below are definition from ACPI spec: | |
1368 | * pcc_nominal- Expected latency to process a command, in microseconds | |
1369 | * pcc_mpar - The maximum number of periodic requests that the subspace | |
1370 | * channel can support, reported in commands per minute. 0 | |
1371 | * indicates no limitation. | |
1372 | * pcc_mrtt - The minimum amount of time that OSPM must wait after the | |
1373 | * completion of a command before issuing the next command, | |
1374 | * in microseconds. | |
1375 | */ | |
1376 | unsigned int latency_ns = 0; | |
1377 | struct cpc_desc *cpc_desc; | |
1378 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1379 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); |
1ecbd717 | 1380 | struct cppc_pcc_data *pcc_ss_data; |
be8b88d7 PP |
1381 | |
1382 | cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); | |
1383 | if (!cpc_desc) | |
1384 | return CPUFREQ_ETERNAL; | |
1385 | ||
1386 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1387 | if (!CPC_IN_PCC(desired_reg)) | |
1388 | return CPUFREQ_ETERNAL; | |
1389 | ||
1ecbd717 GC |
1390 | if (pcc_ss_id < 0) |
1391 | return CPUFREQ_ETERNAL; | |
1392 | ||
1393 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1394 | if (pcc_ss_data->pcc_mpar) |
1395 | latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); | |
be8b88d7 | 1396 | |
85b1407b GC |
1397 | latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); |
1398 | latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); | |
be8b88d7 PP |
1399 | |
1400 | return latency_ns; | |
1401 | } | |
1402 | EXPORT_SYMBOL_GPL(cppc_get_transition_latency); |