Commit | Line | Data |
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337aadff AC |
1 | /* |
2 | * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. | |
3 | * | |
4 | * (C) Copyright 2014, 2015 Linaro Ltd. | |
5 | * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * CPPC describes a few methods for controlling CPU performance using | |
13 | * information from a per CPU table called CPC. This table is described in | |
14 | * the ACPI v5.0+ specification. The table consists of a list of | |
15 | * registers which may be memory mapped or hardware registers and also may | |
16 | * include some static integer values. | |
17 | * | |
18 | * CPU performance is on an abstract continuous scale as against a discretized | |
19 | * P-state scale which is tied to CPU frequency only. In brief, the basic | |
20 | * operation involves: | |
21 | * | |
22 | * - OS makes a CPU performance request. (Can provide min and max bounds) | |
23 | * | |
24 | * - Platform (such as BMC) is free to optimize request within requested bounds | |
25 | * depending on power/thermal budgets etc. | |
26 | * | |
27 | * - Platform conveys its decision back to OS | |
28 | * | |
29 | * The communication between OS and platform occurs through another medium | |
30 | * called (PCC) Platform Communication Channel. This is a generic mailbox like | |
31 | * mechanism which includes doorbell semantics to indicate register updates. | |
32 | * See drivers/mailbox/pcc.c for details on PCC. | |
33 | * | |
34 | * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and | |
35 | * above specifications. | |
36 | */ | |
37 | ||
38 | #define pr_fmt(fmt) "ACPI CPPC: " fmt | |
39 | ||
40 | #include <linux/cpufreq.h> | |
41 | #include <linux/delay.h> | |
ad62e1e6 | 42 | #include <linux/ktime.h> |
80b8286a PP |
43 | #include <linux/rwsem.h> |
44 | #include <linux/wait.h> | |
337aadff AC |
45 | |
46 | #include <acpi/cppc_acpi.h> | |
80b8286a | 47 | |
8482ef8c PP |
48 | struct cppc_pcc_data { |
49 | struct mbox_chan *pcc_channel; | |
50 | void __iomem *pcc_comm_addr; | |
8482ef8c PP |
51 | bool pcc_channel_acquired; |
52 | ktime_t deadline; | |
53 | unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; | |
80b8286a | 54 | |
8482ef8c | 55 | bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ |
139aee73 | 56 | bool platform_owns_pcc; /* Ownership of PCC subspace */ |
8482ef8c | 57 | unsigned int pcc_write_cnt; /* Running count of PCC write commands */ |
80b8286a | 58 | |
8482ef8c PP |
59 | /* |
60 | * Lock to provide controlled access to the PCC channel. | |
61 | * | |
62 | * For performance critical usecases(currently cppc_set_perf) | |
63 | * We need to take read_lock and check if channel belongs to OSPM | |
64 | * before reading or writing to PCC subspace | |
65 | * We need to take write_lock before transferring the channel | |
66 | * ownership to the platform via a Doorbell | |
67 | * This allows us to batch a number of CPPC requests if they happen | |
68 | * to originate in about the same time | |
69 | * | |
70 | * For non-performance critical usecases(init) | |
71 | * Take write_lock for all purposes which gives exclusive access | |
72 | */ | |
73 | struct rw_semaphore pcc_lock; | |
74 | ||
75 | /* Wait queue for CPUs whose requests were batched */ | |
76 | wait_queue_head_t pcc_write_wait_q; | |
85b1407b GC |
77 | ktime_t last_cmd_cmpl_time; |
78 | ktime_t last_mpar_reset; | |
79 | int mpar_count; | |
80 | int refcount; | |
8482ef8c | 81 | }; |
80b8286a | 82 | |
85b1407b GC |
83 | /* Array to represent the PCC channel per subspace id */ |
84 | static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; | |
85 | /* The cpu_pcc_subspace_idx containsper CPU subspace id */ | |
86 | static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); | |
337aadff AC |
87 | |
88 | /* | |
89 | * The cpc_desc structure contains the ACPI register details | |
90 | * as described in the per CPU _CPC tables. The details | |
91 | * include the type of register (e.g. PCC, System IO, FFH etc.) | |
92 | * and destination addresses which lets us READ/WRITE CPU performance | |
93 | * information using the appropriate I/O methods. | |
94 | */ | |
95 | static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); | |
96 | ||
77e3d86f | 97 | /* pcc mapped address + header size + offset within PCC subspace */ |
85b1407b GC |
98 | #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ |
99 | 0x8 + (offs)) | |
77e3d86f | 100 | |
ad61dd30 | 101 | /* Check if a CPC register is in PCC */ |
80b8286a PP |
102 | #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ |
103 | (cpc)->cpc_entry.reg.space_id == \ | |
104 | ACPI_ADR_SPACE_PLATFORM_COMM) | |
105 | ||
158c998e AC |
106 | /* Evalutes to True if reg is a NULL register descriptor */ |
107 | #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ | |
108 | (reg)->address == 0 && \ | |
109 | (reg)->bit_width == 0 && \ | |
110 | (reg)->bit_offset == 0 && \ | |
111 | (reg)->access_width == 0) | |
112 | ||
113 | /* Evalutes to True if an optional cpc field is supported */ | |
114 | #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ | |
115 | !!(cpc)->cpc_entry.int_value : \ | |
116 | !IS_NULL_REG(&(cpc)->cpc_entry.reg)) | |
337aadff AC |
117 | /* |
118 | * Arbitrary Retries in case the remote processor is slow to respond | |
ad62e1e6 AC |
119 | * to PCC commands. Keeping it high enough to cover emulators where |
120 | * the processors run painfully slow. | |
337aadff | 121 | */ |
b52f4511 | 122 | #define NUM_RETRIES 500ULL |
337aadff | 123 | |
158c998e AC |
124 | struct cppc_attr { |
125 | struct attribute attr; | |
126 | ssize_t (*show)(struct kobject *kobj, | |
127 | struct attribute *attr, char *buf); | |
128 | ssize_t (*store)(struct kobject *kobj, | |
129 | struct attribute *attr, const char *c, ssize_t count); | |
130 | }; | |
131 | ||
132 | #define define_one_cppc_ro(_name) \ | |
133 | static struct cppc_attr _name = \ | |
134 | __ATTR(_name, 0444, show_##_name, NULL) | |
135 | ||
136 | #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) | |
137 | ||
2c74d847 PP |
138 | #define show_cppc_data(access_fn, struct_name, member_name) \ |
139 | static ssize_t show_##member_name(struct kobject *kobj, \ | |
140 | struct attribute *attr, char *buf) \ | |
141 | { \ | |
142 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ | |
143 | struct struct_name st_name = {0}; \ | |
144 | int ret; \ | |
145 | \ | |
146 | ret = access_fn(cpc_ptr->cpu_id, &st_name); \ | |
147 | if (ret) \ | |
148 | return ret; \ | |
149 | \ | |
150 | return scnprintf(buf, PAGE_SIZE, "%llu\n", \ | |
151 | (u64)st_name.member_name); \ | |
152 | } \ | |
153 | define_one_cppc_ro(member_name) | |
154 | ||
155 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); | |
156 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); | |
157 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); | |
158 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); | |
4773e77c PP |
159 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); |
160 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); | |
161 | ||
2c74d847 PP |
162 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); |
163 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); | |
164 | ||
158c998e AC |
165 | static ssize_t show_feedback_ctrs(struct kobject *kobj, |
166 | struct attribute *attr, char *buf) | |
167 | { | |
168 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
169 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
2c74d847 | 170 | int ret; |
158c998e | 171 | |
2c74d847 PP |
172 | ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); |
173 | if (ret) | |
174 | return ret; | |
158c998e AC |
175 | |
176 | return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", | |
177 | fb_ctrs.reference, fb_ctrs.delivered); | |
178 | } | |
179 | define_one_cppc_ro(feedback_ctrs); | |
180 | ||
158c998e AC |
181 | static struct attribute *cppc_attrs[] = { |
182 | &feedback_ctrs.attr, | |
183 | &reference_perf.attr, | |
184 | &wraparound_time.attr, | |
2c74d847 PP |
185 | &highest_perf.attr, |
186 | &lowest_perf.attr, | |
187 | &lowest_nonlinear_perf.attr, | |
188 | &nominal_perf.attr, | |
4773e77c PP |
189 | &nominal_freq.attr, |
190 | &lowest_freq.attr, | |
158c998e AC |
191 | NULL |
192 | }; | |
193 | ||
194 | static struct kobj_type cppc_ktype = { | |
195 | .sysfs_ops = &kobj_sysfs_ops, | |
196 | .default_attrs = cppc_attrs, | |
197 | }; | |
198 | ||
85b1407b | 199 | static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) |
ad62e1e6 | 200 | { |
139aee73 | 201 | int ret = -EIO, status = 0; |
85b1407b GC |
202 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
203 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = | |
204 | pcc_ss_data->pcc_comm_addr; | |
205 | ktime_t next_deadline = ktime_add(ktime_get(), | |
206 | pcc_ss_data->deadline); | |
ad62e1e6 | 207 | |
85b1407b | 208 | if (!pcc_ss_data->platform_owns_pcc) |
139aee73 PP |
209 | return 0; |
210 | ||
ad62e1e6 AC |
211 | /* Retry in case the remote processor was too slow to catch up. */ |
212 | while (!ktime_after(ktime_get(), next_deadline)) { | |
f387e5b9 PP |
213 | /* |
214 | * Per spec, prior to boot the PCC space wil be initialized by | |
215 | * platform and should have set the command completion bit when | |
216 | * PCC can be used by OSPM | |
217 | */ | |
139aee73 PP |
218 | status = readw_relaxed(&generic_comm_base->status); |
219 | if (status & PCC_CMD_COMPLETE_MASK) { | |
ad62e1e6 | 220 | ret = 0; |
139aee73 PP |
221 | if (chk_err_bit && (status & PCC_ERROR_MASK)) |
222 | ret = -EIO; | |
ad62e1e6 AC |
223 | break; |
224 | } | |
225 | /* | |
226 | * Reducing the bus traffic in case this loop takes longer than | |
227 | * a few retries. | |
228 | */ | |
229 | udelay(3); | |
230 | } | |
231 | ||
139aee73 | 232 | if (likely(!ret)) |
85b1407b | 233 | pcc_ss_data->platform_owns_pcc = false; |
139aee73 | 234 | else |
d29abc83 GC |
235 | pr_err("PCC check channel failed for ss: %d. Status=%x\n", |
236 | pcc_ss_id, status); | |
139aee73 | 237 | |
ad62e1e6 AC |
238 | return ret; |
239 | } | |
240 | ||
80b8286a PP |
241 | /* |
242 | * This function transfers the ownership of the PCC to the platform | |
243 | * So it must be called while holding write_lock(pcc_lock) | |
244 | */ | |
85b1407b | 245 | static int send_pcc_cmd(int pcc_ss_id, u16 cmd) |
337aadff | 246 | { |
80b8286a | 247 | int ret = -EIO, i; |
85b1407b | 248 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
337aadff | 249 | struct acpi_pcct_shared_memory *generic_comm_base = |
85b1407b | 250 | (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr; |
f387e5b9 | 251 | unsigned int time_delta; |
337aadff | 252 | |
ad62e1e6 AC |
253 | /* |
254 | * For CMD_WRITE we know for a fact the caller should have checked | |
255 | * the channel before writing to PCC space | |
256 | */ | |
257 | if (cmd == CMD_READ) { | |
80b8286a PP |
258 | /* |
259 | * If there are pending cpc_writes, then we stole the channel | |
260 | * before write completion, so first send a WRITE command to | |
261 | * platform | |
262 | */ | |
85b1407b GC |
263 | if (pcc_ss_data->pending_pcc_write_cmd) |
264 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
80b8286a | 265 | |
85b1407b | 266 | ret = check_pcc_chan(pcc_ss_id, false); |
ad62e1e6 | 267 | if (ret) |
80b8286a PP |
268 | goto end; |
269 | } else /* CMD_WRITE */ | |
85b1407b | 270 | pcc_ss_data->pending_pcc_write_cmd = FALSE; |
337aadff | 271 | |
f387e5b9 PP |
272 | /* |
273 | * Handle the Minimum Request Turnaround Time(MRTT) | |
274 | * "The minimum amount of time that OSPM must wait after the completion | |
275 | * of a command before issuing the next command, in microseconds" | |
276 | */ | |
85b1407b GC |
277 | if (pcc_ss_data->pcc_mrtt) { |
278 | time_delta = ktime_us_delta(ktime_get(), | |
279 | pcc_ss_data->last_cmd_cmpl_time); | |
280 | if (pcc_ss_data->pcc_mrtt > time_delta) | |
281 | udelay(pcc_ss_data->pcc_mrtt - time_delta); | |
f387e5b9 PP |
282 | } |
283 | ||
284 | /* | |
285 | * Handle the non-zero Maximum Periodic Access Rate(MPAR) | |
286 | * "The maximum number of periodic requests that the subspace channel can | |
287 | * support, reported in commands per minute. 0 indicates no limitation." | |
288 | * | |
289 | * This parameter should be ideally zero or large enough so that it can | |
290 | * handle maximum number of requests that all the cores in the system can | |
291 | * collectively generate. If it is not, we will follow the spec and just | |
292 | * not send the request to the platform after hitting the MPAR limit in | |
293 | * any 60s window | |
294 | */ | |
85b1407b GC |
295 | if (pcc_ss_data->pcc_mpar) { |
296 | if (pcc_ss_data->mpar_count == 0) { | |
297 | time_delta = ktime_ms_delta(ktime_get(), | |
298 | pcc_ss_data->last_mpar_reset); | |
299 | if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { | |
d29abc83 GC |
300 | pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", |
301 | pcc_ss_id); | |
80b8286a PP |
302 | ret = -EIO; |
303 | goto end; | |
f387e5b9 | 304 | } |
85b1407b GC |
305 | pcc_ss_data->last_mpar_reset = ktime_get(); |
306 | pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; | |
f387e5b9 | 307 | } |
85b1407b | 308 | pcc_ss_data->mpar_count--; |
f387e5b9 PP |
309 | } |
310 | ||
337aadff | 311 | /* Write to the shared comm region. */ |
beee23ae | 312 | writew_relaxed(cmd, &generic_comm_base->command); |
337aadff AC |
313 | |
314 | /* Flip CMD COMPLETE bit */ | |
beee23ae | 315 | writew_relaxed(0, &generic_comm_base->status); |
337aadff | 316 | |
85b1407b | 317 | pcc_ss_data->platform_owns_pcc = true; |
139aee73 | 318 | |
337aadff | 319 | /* Ring doorbell */ |
85b1407b | 320 | ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd); |
ad62e1e6 | 321 | if (ret < 0) { |
d29abc83 GC |
322 | pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", |
323 | pcc_ss_id, cmd, ret); | |
80b8286a | 324 | goto end; |
337aadff AC |
325 | } |
326 | ||
139aee73 | 327 | /* wait for completion and check for PCC errro bit */ |
85b1407b | 328 | ret = check_pcc_chan(pcc_ss_id, true); |
139aee73 | 329 | |
85b1407b GC |
330 | if (pcc_ss_data->pcc_mrtt) |
331 | pcc_ss_data->last_cmd_cmpl_time = ktime_get(); | |
337aadff | 332 | |
85b1407b GC |
333 | if (pcc_ss_data->pcc_channel->mbox->txdone_irq) |
334 | mbox_chan_txdone(pcc_ss_data->pcc_channel, ret); | |
b59c4b3d | 335 | else |
85b1407b | 336 | mbox_client_txdone(pcc_ss_data->pcc_channel, ret); |
80b8286a PP |
337 | |
338 | end: | |
339 | if (cmd == CMD_WRITE) { | |
340 | if (unlikely(ret)) { | |
341 | for_each_possible_cpu(i) { | |
342 | struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); | |
343 | if (!desc) | |
344 | continue; | |
345 | ||
85b1407b | 346 | if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) |
80b8286a PP |
347 | desc->write_cmd_status = ret; |
348 | } | |
349 | } | |
85b1407b GC |
350 | pcc_ss_data->pcc_write_cnt++; |
351 | wake_up_all(&pcc_ss_data->pcc_write_wait_q); | |
80b8286a PP |
352 | } |
353 | ||
ad62e1e6 | 354 | return ret; |
337aadff AC |
355 | } |
356 | ||
357 | static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) | |
358 | { | |
ad62e1e6 | 359 | if (ret < 0) |
337aadff AC |
360 | pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", |
361 | *(u16 *)msg, ret); | |
362 | else | |
363 | pr_debug("TX completed. CMD sent:%x, ret:%d\n", | |
364 | *(u16 *)msg, ret); | |
365 | } | |
366 | ||
367 | struct mbox_client cppc_mbox_cl = { | |
368 | .tx_done = cppc_chan_tx_done, | |
369 | .knows_txdone = true, | |
370 | }; | |
371 | ||
372 | static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) | |
373 | { | |
374 | int result = -EFAULT; | |
375 | acpi_status status = AE_OK; | |
376 | struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; | |
377 | struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; | |
378 | struct acpi_buffer state = {0, NULL}; | |
379 | union acpi_object *psd = NULL; | |
380 | struct acpi_psd_package *pdomain; | |
381 | ||
382 | status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer, | |
383 | ACPI_TYPE_PACKAGE); | |
384 | if (ACPI_FAILURE(status)) | |
385 | return -ENODEV; | |
386 | ||
387 | psd = buffer.pointer; | |
388 | if (!psd || psd->package.count != 1) { | |
389 | pr_debug("Invalid _PSD data\n"); | |
390 | goto end; | |
391 | } | |
392 | ||
393 | pdomain = &(cpc_ptr->domain_info); | |
394 | ||
395 | state.length = sizeof(struct acpi_psd_package); | |
396 | state.pointer = pdomain; | |
397 | ||
398 | status = acpi_extract_package(&(psd->package.elements[0]), | |
399 | &format, &state); | |
400 | if (ACPI_FAILURE(status)) { | |
401 | pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); | |
402 | goto end; | |
403 | } | |
404 | ||
405 | if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { | |
406 | pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); | |
407 | goto end; | |
408 | } | |
409 | ||
410 | if (pdomain->revision != ACPI_PSD_REV0_REVISION) { | |
411 | pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); | |
412 | goto end; | |
413 | } | |
414 | ||
415 | if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && | |
416 | pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && | |
417 | pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { | |
418 | pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); | |
419 | goto end; | |
420 | } | |
421 | ||
422 | result = 0; | |
423 | end: | |
424 | kfree(buffer.pointer); | |
425 | return result; | |
426 | } | |
427 | ||
428 | /** | |
429 | * acpi_get_psd_map - Map the CPUs in a common freq domain. | |
430 | * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info. | |
431 | * | |
432 | * Return: 0 for success or negative value for err. | |
433 | */ | |
41dd6403 | 434 | int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data) |
337aadff AC |
435 | { |
436 | int count_target; | |
437 | int retval = 0; | |
438 | unsigned int i, j; | |
439 | cpumask_var_t covered_cpus; | |
41dd6403 | 440 | struct cppc_cpudata *pr, *match_pr; |
337aadff AC |
441 | struct acpi_psd_package *pdomain; |
442 | struct acpi_psd_package *match_pdomain; | |
443 | struct cpc_desc *cpc_ptr, *match_cpc_ptr; | |
444 | ||
445 | if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) | |
446 | return -ENOMEM; | |
447 | ||
448 | /* | |
449 | * Now that we have _PSD data from all CPUs, lets setup P-state | |
450 | * domain info. | |
451 | */ | |
452 | for_each_possible_cpu(i) { | |
453 | pr = all_cpu_data[i]; | |
454 | if (!pr) | |
455 | continue; | |
456 | ||
457 | if (cpumask_test_cpu(i, covered_cpus)) | |
458 | continue; | |
459 | ||
460 | cpc_ptr = per_cpu(cpc_desc_ptr, i); | |
8343c40d HT |
461 | if (!cpc_ptr) { |
462 | retval = -EFAULT; | |
463 | goto err_ret; | |
464 | } | |
337aadff AC |
465 | |
466 | pdomain = &(cpc_ptr->domain_info); | |
467 | cpumask_set_cpu(i, pr->shared_cpu_map); | |
468 | cpumask_set_cpu(i, covered_cpus); | |
469 | if (pdomain->num_processors <= 1) | |
470 | continue; | |
471 | ||
472 | /* Validate the Domain info */ | |
473 | count_target = pdomain->num_processors; | |
474 | if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) | |
475 | pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
476 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) | |
477 | pr->shared_type = CPUFREQ_SHARED_TYPE_HW; | |
478 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) | |
479 | pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
480 | ||
481 | for_each_possible_cpu(j) { | |
482 | if (i == j) | |
483 | continue; | |
484 | ||
485 | match_cpc_ptr = per_cpu(cpc_desc_ptr, j); | |
8343c40d HT |
486 | if (!match_cpc_ptr) { |
487 | retval = -EFAULT; | |
488 | goto err_ret; | |
489 | } | |
337aadff AC |
490 | |
491 | match_pdomain = &(match_cpc_ptr->domain_info); | |
492 | if (match_pdomain->domain != pdomain->domain) | |
493 | continue; | |
494 | ||
495 | /* Here i and j are in the same domain */ | |
496 | if (match_pdomain->num_processors != count_target) { | |
497 | retval = -EFAULT; | |
498 | goto err_ret; | |
499 | } | |
500 | ||
501 | if (pdomain->coord_type != match_pdomain->coord_type) { | |
502 | retval = -EFAULT; | |
503 | goto err_ret; | |
504 | } | |
505 | ||
506 | cpumask_set_cpu(j, covered_cpus); | |
507 | cpumask_set_cpu(j, pr->shared_cpu_map); | |
508 | } | |
509 | ||
510 | for_each_possible_cpu(j) { | |
511 | if (i == j) | |
512 | continue; | |
513 | ||
514 | match_pr = all_cpu_data[j]; | |
515 | if (!match_pr) | |
516 | continue; | |
517 | ||
518 | match_cpc_ptr = per_cpu(cpc_desc_ptr, j); | |
8343c40d HT |
519 | if (!match_cpc_ptr) { |
520 | retval = -EFAULT; | |
521 | goto err_ret; | |
522 | } | |
337aadff AC |
523 | |
524 | match_pdomain = &(match_cpc_ptr->domain_info); | |
525 | if (match_pdomain->domain != pdomain->domain) | |
526 | continue; | |
527 | ||
528 | match_pr->shared_type = pr->shared_type; | |
529 | cpumask_copy(match_pr->shared_cpu_map, | |
530 | pr->shared_cpu_map); | |
531 | } | |
532 | } | |
533 | ||
534 | err_ret: | |
535 | for_each_possible_cpu(i) { | |
536 | pr = all_cpu_data[i]; | |
537 | if (!pr) | |
538 | continue; | |
539 | ||
540 | /* Assume no coordination on any error parsing domain info */ | |
541 | if (retval) { | |
542 | cpumask_clear(pr->shared_cpu_map); | |
543 | cpumask_set_cpu(i, pr->shared_cpu_map); | |
544 | pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
545 | } | |
546 | } | |
547 | ||
548 | free_cpumask_var(covered_cpus); | |
549 | return retval; | |
550 | } | |
551 | EXPORT_SYMBOL_GPL(acpi_get_psd_map); | |
552 | ||
85b1407b | 553 | static int register_pcc_channel(int pcc_ss_idx) |
337aadff | 554 | { |
d29d6735 | 555 | struct acpi_pcct_hw_reduced *cppc_ss; |
ad62e1e6 | 556 | u64 usecs_lat; |
337aadff | 557 | |
85b1407b GC |
558 | if (pcc_ss_idx >= 0) { |
559 | pcc_data[pcc_ss_idx]->pcc_channel = | |
560 | pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); | |
337aadff | 561 | |
85b1407b | 562 | if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) { |
d29abc83 GC |
563 | pr_err("Failed to find PCC channel for subspace %d\n", |
564 | pcc_ss_idx); | |
337aadff AC |
565 | return -ENODEV; |
566 | } | |
567 | ||
568 | /* | |
569 | * The PCC mailbox controller driver should | |
570 | * have parsed the PCCT (global table of all | |
571 | * PCC channels) and stored pointers to the | |
572 | * subspace communication region in con_priv. | |
573 | */ | |
85b1407b | 574 | cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv; |
337aadff AC |
575 | |
576 | if (!cppc_ss) { | |
d29abc83 GC |
577 | pr_err("No PCC subspace found for %d CPPC\n", |
578 | pcc_ss_idx); | |
337aadff AC |
579 | return -ENODEV; |
580 | } | |
581 | ||
ad62e1e6 AC |
582 | /* |
583 | * cppc_ss->latency is just a Nominal value. In reality | |
584 | * the remote processor could be much slower to reply. | |
585 | * So add an arbitrary amount of wait on top of Nominal. | |
586 | */ | |
587 | usecs_lat = NUM_RETRIES * cppc_ss->latency; | |
85b1407b GC |
588 | pcc_data[pcc_ss_idx]->deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC); |
589 | pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time; | |
590 | pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate; | |
591 | pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency; | |
592 | ||
593 | pcc_data[pcc_ss_idx]->pcc_comm_addr = | |
594 | acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length); | |
595 | if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { | |
d29abc83 GC |
596 | pr_err("Failed to ioremap PCC comm region mem for %d\n", |
597 | pcc_ss_idx); | |
337aadff AC |
598 | return -ENOMEM; |
599 | } | |
600 | ||
601 | /* Set flag so that we dont come here for each CPU. */ | |
85b1407b | 602 | pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; |
337aadff AC |
603 | } |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
a6cbcdd5 SP |
608 | /** |
609 | * cpc_ffh_supported() - check if FFH reading supported | |
610 | * | |
611 | * Check if the architecture has support for functional fixed hardware | |
612 | * read/write capability. | |
613 | * | |
614 | * Return: true for supported, false for not supported | |
615 | */ | |
616 | bool __weak cpc_ffh_supported(void) | |
617 | { | |
618 | return false; | |
619 | } | |
620 | ||
85b1407b GC |
621 | /** |
622 | * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace | |
623 | * | |
624 | * Check and allocate the cppc_pcc_data memory. | |
625 | * In some processor configurations it is possible that same subspace | |
626 | * is shared between multiple CPU's. This is seen especially in CPU's | |
627 | * with hardware multi-threading support. | |
628 | * | |
629 | * Return: 0 for success, errno for failure | |
630 | */ | |
631 | int pcc_data_alloc(int pcc_ss_id) | |
632 | { | |
633 | if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) | |
634 | return -EINVAL; | |
635 | ||
636 | if (pcc_data[pcc_ss_id]) { | |
637 | pcc_data[pcc_ss_id]->refcount++; | |
638 | } else { | |
639 | pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), | |
640 | GFP_KERNEL); | |
641 | if (!pcc_data[pcc_ss_id]) | |
642 | return -ENOMEM; | |
643 | pcc_data[pcc_ss_id]->refcount++; | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
4773e77c PP |
648 | |
649 | /* Check if CPPC revision + num_ent combination is supported */ | |
650 | static bool is_cppc_supported(int revision, int num_ent) | |
651 | { | |
652 | int expected_num_ent; | |
653 | ||
654 | switch (revision) { | |
655 | case CPPC_V2_REV: | |
656 | expected_num_ent = CPPC_V2_NUM_ENT; | |
657 | break; | |
658 | case CPPC_V3_REV: | |
659 | expected_num_ent = CPPC_V3_NUM_ENT; | |
660 | break; | |
661 | default: | |
662 | pr_debug("Firmware exports unsupported CPPC revision: %d\n", | |
663 | revision); | |
664 | return false; | |
665 | } | |
666 | ||
667 | if (expected_num_ent != num_ent) { | |
668 | pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n", | |
669 | num_ent, expected_num_ent, revision); | |
670 | return false; | |
671 | } | |
672 | ||
673 | return true; | |
674 | } | |
675 | ||
337aadff AC |
676 | /* |
677 | * An example CPC table looks like the following. | |
678 | * | |
679 | * Name(_CPC, Package() | |
680 | * { | |
681 | * 17, | |
682 | * NumEntries | |
683 | * 1, | |
684 | * // Revision | |
685 | * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, | |
686 | * // Highest Performance | |
687 | * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, | |
688 | * // Nominal Performance | |
689 | * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, | |
690 | * // Lowest Nonlinear Performance | |
691 | * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, | |
692 | * // Lowest Performance | |
693 | * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, | |
694 | * // Guaranteed Performance Register | |
695 | * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, | |
696 | * // Desired Performance Register | |
697 | * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, | |
698 | * .. | |
699 | * .. | |
700 | * .. | |
701 | * | |
702 | * } | |
703 | * Each Register() encodes how to access that specific register. | |
704 | * e.g. a sample PCC entry has the following encoding: | |
705 | * | |
706 | * Register ( | |
707 | * PCC, | |
708 | * AddressSpaceKeyword | |
709 | * 8, | |
710 | * //RegisterBitWidth | |
711 | * 8, | |
712 | * //RegisterBitOffset | |
713 | * 0x30, | |
714 | * //RegisterAddress | |
715 | * 9 | |
716 | * //AccessSize (subspace ID) | |
717 | * 0 | |
718 | * ) | |
719 | * } | |
720 | */ | |
721 | ||
722 | /** | |
723 | * acpi_cppc_processor_probe - Search for per CPU _CPC objects. | |
724 | * @pr: Ptr to acpi_processor containing this CPUs logical Id. | |
725 | * | |
726 | * Return: 0 for success or negative value for err. | |
727 | */ | |
728 | int acpi_cppc_processor_probe(struct acpi_processor *pr) | |
729 | { | |
730 | struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; | |
731 | union acpi_object *out_obj, *cpc_obj; | |
732 | struct cpc_desc *cpc_ptr; | |
733 | struct cpc_reg *gas_t; | |
158c998e | 734 | struct device *cpu_dev; |
337aadff AC |
735 | acpi_handle handle = pr->handle; |
736 | unsigned int num_ent, i, cpc_rev; | |
85b1407b | 737 | int pcc_subspace_id = -1; |
337aadff AC |
738 | acpi_status status; |
739 | int ret = -EFAULT; | |
740 | ||
741 | /* Parse the ACPI _CPC table for this cpu. */ | |
742 | status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, | |
743 | ACPI_TYPE_PACKAGE); | |
744 | if (ACPI_FAILURE(status)) { | |
745 | ret = -ENODEV; | |
746 | goto out_buf_free; | |
747 | } | |
748 | ||
749 | out_obj = (union acpi_object *) output.pointer; | |
750 | ||
751 | cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); | |
752 | if (!cpc_ptr) { | |
753 | ret = -ENOMEM; | |
754 | goto out_buf_free; | |
755 | } | |
756 | ||
757 | /* First entry is NumEntries. */ | |
758 | cpc_obj = &out_obj->package.elements[0]; | |
759 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
760 | num_ent = cpc_obj->integer.value; | |
761 | } else { | |
762 | pr_debug("Unexpected entry type(%d) for NumEntries\n", | |
763 | cpc_obj->type); | |
764 | goto out_free; | |
765 | } | |
5bbb86aa AC |
766 | cpc_ptr->num_entries = num_ent; |
767 | ||
337aadff AC |
768 | /* Second entry should be revision. */ |
769 | cpc_obj = &out_obj->package.elements[1]; | |
770 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
771 | cpc_rev = cpc_obj->integer.value; | |
772 | } else { | |
773 | pr_debug("Unexpected entry type(%d) for Revision\n", | |
774 | cpc_obj->type); | |
775 | goto out_free; | |
776 | } | |
4773e77c | 777 | cpc_ptr->version = cpc_rev; |
337aadff | 778 | |
4773e77c | 779 | if (!is_cppc_supported(cpc_rev, num_ent)) |
337aadff | 780 | goto out_free; |
337aadff AC |
781 | |
782 | /* Iterate through remaining entries in _CPC */ | |
783 | for (i = 2; i < num_ent; i++) { | |
784 | cpc_obj = &out_obj->package.elements[i]; | |
785 | ||
786 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
787 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; | |
788 | cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; | |
789 | } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { | |
790 | gas_t = (struct cpc_reg *) | |
791 | cpc_obj->buffer.pointer; | |
792 | ||
793 | /* | |
794 | * The PCC Subspace index is encoded inside | |
795 | * the CPC table entries. The same PCC index | |
796 | * will be used for all the PCC entries, | |
797 | * so extract it only once. | |
798 | */ | |
799 | if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { | |
85b1407b GC |
800 | if (pcc_subspace_id < 0) { |
801 | pcc_subspace_id = gas_t->access_width; | |
802 | if (pcc_data_alloc(pcc_subspace_id)) | |
803 | goto out_free; | |
804 | } else if (pcc_subspace_id != gas_t->access_width) { | |
337aadff AC |
805 | pr_debug("Mismatched PCC ids.\n"); |
806 | goto out_free; | |
807 | } | |
5bbb86aa AC |
808 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
809 | if (gas_t->address) { | |
810 | void __iomem *addr; | |
811 | ||
812 | addr = ioremap(gas_t->address, gas_t->bit_width/8); | |
813 | if (!addr) | |
814 | goto out_free; | |
815 | cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; | |
816 | } | |
817 | } else { | |
a6cbcdd5 SP |
818 | if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { |
819 | /* Support only PCC ,SYS MEM and FFH type regs */ | |
820 | pr_debug("Unsupported register type: %d\n", gas_t->space_id); | |
821 | goto out_free; | |
822 | } | |
337aadff AC |
823 | } |
824 | ||
825 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; | |
826 | memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); | |
827 | } else { | |
828 | pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); | |
829 | goto out_free; | |
830 | } | |
831 | } | |
85b1407b | 832 | per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; |
4773e77c PP |
833 | |
834 | /* | |
835 | * Initialize the remaining cpc_regs as unsupported. | |
836 | * Example: In case FW exposes CPPC v2, the below loop will initialize | |
837 | * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported | |
838 | */ | |
839 | for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { | |
840 | cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; | |
841 | cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; | |
842 | } | |
843 | ||
844 | ||
337aadff AC |
845 | /* Store CPU Logical ID */ |
846 | cpc_ptr->cpu_id = pr->id; | |
847 | ||
337aadff AC |
848 | /* Parse PSD data for this CPU */ |
849 | ret = acpi_get_psd(cpc_ptr, handle); | |
850 | if (ret) | |
851 | goto out_free; | |
852 | ||
85b1407b GC |
853 | /* Register PCC channel once for all PCC subspace id. */ |
854 | if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { | |
855 | ret = register_pcc_channel(pcc_subspace_id); | |
337aadff AC |
856 | if (ret) |
857 | goto out_free; | |
8482ef8c | 858 | |
85b1407b GC |
859 | init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); |
860 | init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); | |
337aadff AC |
861 | } |
862 | ||
863 | /* Everything looks okay */ | |
864 | pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); | |
865 | ||
158c998e AC |
866 | /* Add per logical CPU nodes for reading its feedback counters. */ |
867 | cpu_dev = get_cpu_device(pr->id); | |
50163475 DC |
868 | if (!cpu_dev) { |
869 | ret = -EINVAL; | |
158c998e | 870 | goto out_free; |
50163475 | 871 | } |
158c998e | 872 | |
28076483 RW |
873 | /* Plug PSD data into this CPUs CPC descriptor. */ |
874 | per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; | |
875 | ||
158c998e AC |
876 | ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, |
877 | "acpi_cppc"); | |
28076483 RW |
878 | if (ret) { |
879 | per_cpu(cpc_desc_ptr, pr->id) = NULL; | |
158c998e | 880 | goto out_free; |
28076483 | 881 | } |
158c998e | 882 | |
337aadff AC |
883 | kfree(output.pointer); |
884 | return 0; | |
885 | ||
886 | out_free: | |
5bbb86aa AC |
887 | /* Free all the mapped sys mem areas for this CPU */ |
888 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
889 | void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
890 | ||
891 | if (addr) | |
892 | iounmap(addr); | |
893 | } | |
337aadff AC |
894 | kfree(cpc_ptr); |
895 | ||
896 | out_buf_free: | |
897 | kfree(output.pointer); | |
898 | return ret; | |
899 | } | |
900 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); | |
901 | ||
902 | /** | |
903 | * acpi_cppc_processor_exit - Cleanup CPC structs. | |
904 | * @pr: Ptr to acpi_processor containing this CPUs logical Id. | |
905 | * | |
906 | * Return: Void | |
907 | */ | |
908 | void acpi_cppc_processor_exit(struct acpi_processor *pr) | |
909 | { | |
910 | struct cpc_desc *cpc_ptr; | |
5bbb86aa AC |
911 | unsigned int i; |
912 | void __iomem *addr; | |
85b1407b GC |
913 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); |
914 | ||
915 | if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) { | |
916 | if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { | |
917 | pcc_data[pcc_ss_id]->refcount--; | |
918 | if (!pcc_data[pcc_ss_id]->refcount) { | |
919 | pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); | |
920 | pcc_data[pcc_ss_id]->pcc_channel_acquired = 0; | |
921 | kfree(pcc_data[pcc_ss_id]); | |
922 | } | |
923 | } | |
924 | } | |
158c998e | 925 | |
337aadff | 926 | cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); |
9e9d68da SAS |
927 | if (!cpc_ptr) |
928 | return; | |
5bbb86aa AC |
929 | |
930 | /* Free all the mapped sys mem areas for this CPU */ | |
931 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
932 | addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
933 | if (addr) | |
934 | iounmap(addr); | |
935 | } | |
936 | ||
158c998e | 937 | kobject_put(&cpc_ptr->kobj); |
337aadff AC |
938 | kfree(cpc_ptr); |
939 | } | |
940 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); | |
941 | ||
a6cbcdd5 SP |
942 | /** |
943 | * cpc_read_ffh() - Read FFH register | |
944 | * @cpunum: cpu number to read | |
945 | * @reg: cppc register information | |
946 | * @val: place holder for return value | |
947 | * | |
948 | * Read bit_width bits from a specified address and bit_offset | |
949 | * | |
950 | * Return: 0 for success and error code | |
951 | */ | |
952 | int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | |
953 | { | |
954 | return -ENOTSUPP; | |
955 | } | |
956 | ||
957 | /** | |
958 | * cpc_write_ffh() - Write FFH register | |
959 | * @cpunum: cpu number to write | |
960 | * @reg: cppc register information | |
961 | * @val: value to write | |
962 | * | |
963 | * Write value of bit_width bits to a specified address and bit_offset | |
964 | * | |
965 | * Return: 0 for success and error code | |
966 | */ | |
967 | int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | |
968 | { | |
969 | return -ENOTSUPP; | |
970 | } | |
971 | ||
77e3d86f PP |
972 | /* |
973 | * Since cpc_read and cpc_write are called while holding pcc_lock, it should be | |
974 | * as fast as possible. We have already mapped the PCC subspace during init, so | |
975 | * we can directly write to it. | |
976 | */ | |
337aadff | 977 | |
a6cbcdd5 | 978 | static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) |
337aadff | 979 | { |
77e3d86f | 980 | int ret_val = 0; |
5bbb86aa | 981 | void __iomem *vaddr = 0; |
85b1407b | 982 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa AC |
983 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
984 | ||
985 | if (reg_res->type == ACPI_TYPE_INTEGER) { | |
986 | *val = reg_res->cpc_entry.int_value; | |
987 | return ret_val; | |
988 | } | |
77e3d86f PP |
989 | |
990 | *val = 0; | |
1ecbd717 | 991 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) |
85b1407b | 992 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
993 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
994 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
995 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
996 | return cpc_read_ffh(cpu, reg, val); | |
5bbb86aa AC |
997 | else |
998 | return acpi_os_read_memory((acpi_physical_address)reg->address, | |
999 | val, reg->bit_width); | |
337aadff | 1000 | |
5bbb86aa | 1001 | switch (reg->bit_width) { |
77e3d86f | 1002 | case 8: |
beee23ae | 1003 | *val = readb_relaxed(vaddr); |
77e3d86f PP |
1004 | break; |
1005 | case 16: | |
beee23ae | 1006 | *val = readw_relaxed(vaddr); |
77e3d86f PP |
1007 | break; |
1008 | case 32: | |
beee23ae | 1009 | *val = readl_relaxed(vaddr); |
77e3d86f PP |
1010 | break; |
1011 | case 64: | |
beee23ae | 1012 | *val = readq_relaxed(vaddr); |
77e3d86f PP |
1013 | break; |
1014 | default: | |
d29abc83 GC |
1015 | pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", |
1016 | reg->bit_width, pcc_ss_id); | |
77e3d86f | 1017 | ret_val = -EFAULT; |
5bbb86aa AC |
1018 | } |
1019 | ||
77e3d86f | 1020 | return ret_val; |
337aadff AC |
1021 | } |
1022 | ||
a6cbcdd5 | 1023 | static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) |
337aadff | 1024 | { |
77e3d86f | 1025 | int ret_val = 0; |
5bbb86aa | 1026 | void __iomem *vaddr = 0; |
85b1407b | 1027 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa | 1028 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
77e3d86f | 1029 | |
1ecbd717 | 1030 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) |
85b1407b | 1031 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
1032 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
1033 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
1034 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
1035 | return cpc_write_ffh(cpu, reg, val); | |
5bbb86aa AC |
1036 | else |
1037 | return acpi_os_write_memory((acpi_physical_address)reg->address, | |
1038 | val, reg->bit_width); | |
337aadff | 1039 | |
5bbb86aa | 1040 | switch (reg->bit_width) { |
77e3d86f | 1041 | case 8: |
beee23ae | 1042 | writeb_relaxed(val, vaddr); |
77e3d86f PP |
1043 | break; |
1044 | case 16: | |
beee23ae | 1045 | writew_relaxed(val, vaddr); |
77e3d86f PP |
1046 | break; |
1047 | case 32: | |
beee23ae | 1048 | writel_relaxed(val, vaddr); |
77e3d86f PP |
1049 | break; |
1050 | case 64: | |
beee23ae | 1051 | writeq_relaxed(val, vaddr); |
77e3d86f PP |
1052 | break; |
1053 | default: | |
d29abc83 GC |
1054 | pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", |
1055 | reg->bit_width, pcc_ss_id); | |
77e3d86f PP |
1056 | ret_val = -EFAULT; |
1057 | break; | |
5bbb86aa AC |
1058 | } |
1059 | ||
77e3d86f | 1060 | return ret_val; |
337aadff AC |
1061 | } |
1062 | ||
1063 | /** | |
1064 | * cppc_get_perf_caps - Get a CPUs performance capabilities. | |
1065 | * @cpunum: CPU from which to get capabilities info. | |
1066 | * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h | |
1067 | * | |
1068 | * Return: 0 for success with perf_caps populated else -ERRNO. | |
1069 | */ | |
1070 | int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) | |
1071 | { | |
1072 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
368520a6 | 1073 | struct cpc_register_resource *highest_reg, *lowest_reg, |
4773e77c PP |
1074 | *lowest_non_linear_reg, *nominal_reg, |
1075 | *low_freq_reg = NULL, *nom_freq_reg = NULL; | |
1076 | u64 high, low, nom, min_nonlinear, low_f = 0, nom_f = 0; | |
85b1407b | 1077 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
1ecbd717 | 1078 | struct cppc_pcc_data *pcc_ss_data; |
850d64a4 | 1079 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1080 | |
1ecbd717 | 1081 | if (!cpc_desc || pcc_ss_id < 0) { |
337aadff AC |
1082 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1083 | return -ENODEV; | |
1084 | } | |
1085 | ||
1ecbd717 | 1086 | pcc_ss_data = pcc_data[pcc_ss_id]; |
337aadff AC |
1087 | highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; |
1088 | lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; | |
368520a6 PP |
1089 | lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; |
1090 | nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
4773e77c PP |
1091 | low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; |
1092 | nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; | |
337aadff | 1093 | |
337aadff | 1094 | /* Are any of the regs PCC ?*/ |
80b8286a | 1095 | if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || |
4773e77c PP |
1096 | CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || |
1097 | CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { | |
850d64a4 | 1098 | regs_in_pcc = 1; |
85b1407b | 1099 | down_write(&pcc_ss_data->pcc_lock); |
337aadff | 1100 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1101 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1102 | ret = -EIO; |
1103 | goto out_err; | |
1104 | } | |
1105 | } | |
1106 | ||
a6cbcdd5 | 1107 | cpc_read(cpunum, highest_reg, &high); |
337aadff AC |
1108 | perf_caps->highest_perf = high; |
1109 | ||
a6cbcdd5 | 1110 | cpc_read(cpunum, lowest_reg, &low); |
337aadff AC |
1111 | perf_caps->lowest_perf = low; |
1112 | ||
368520a6 | 1113 | cpc_read(cpunum, nominal_reg, &nom); |
337aadff AC |
1114 | perf_caps->nominal_perf = nom; |
1115 | ||
368520a6 PP |
1116 | cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); |
1117 | perf_caps->lowest_nonlinear_perf = min_nonlinear; | |
1118 | ||
1119 | if (!high || !low || !nom || !min_nonlinear) | |
337aadff AC |
1120 | ret = -EFAULT; |
1121 | ||
4773e77c PP |
1122 | /* Read optional lowest and nominal frequencies if present */ |
1123 | if (CPC_SUPPORTED(low_freq_reg)) | |
1124 | cpc_read(cpunum, low_freq_reg, &low_f); | |
1125 | ||
1126 | if (CPC_SUPPORTED(nom_freq_reg)) | |
1127 | cpc_read(cpunum, nom_freq_reg, &nom_f); | |
1128 | ||
1129 | perf_caps->lowest_freq = low_f; | |
1130 | perf_caps->nominal_freq = nom_f; | |
1131 | ||
1132 | ||
337aadff | 1133 | out_err: |
850d64a4 | 1134 | if (regs_in_pcc) |
85b1407b | 1135 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1136 | return ret; |
1137 | } | |
1138 | EXPORT_SYMBOL_GPL(cppc_get_perf_caps); | |
1139 | ||
1140 | /** | |
1141 | * cppc_get_perf_ctrs - Read a CPUs performance feedback counters. | |
1142 | * @cpunum: CPU from which to read counters. | |
1143 | * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h | |
1144 | * | |
1145 | * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. | |
1146 | */ | |
1147 | int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) | |
1148 | { | |
1149 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
158c998e AC |
1150 | struct cpc_register_resource *delivered_reg, *reference_reg, |
1151 | *ref_perf_reg, *ctr_wrap_reg; | |
85b1407b | 1152 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
1ecbd717 | 1153 | struct cppc_pcc_data *pcc_ss_data; |
158c998e | 1154 | u64 delivered, reference, ref_perf, ctr_wrap_time; |
850d64a4 | 1155 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1156 | |
1ecbd717 | 1157 | if (!cpc_desc || pcc_ss_id < 0) { |
337aadff AC |
1158 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1159 | return -ENODEV; | |
1160 | } | |
1161 | ||
1ecbd717 | 1162 | pcc_ss_data = pcc_data[pcc_ss_id]; |
337aadff AC |
1163 | delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; |
1164 | reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; | |
158c998e AC |
1165 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; |
1166 | ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; | |
1167 | ||
1168 | /* | |
1169 | * If refernce perf register is not supported then we should | |
1170 | * use the nominal perf value | |
1171 | */ | |
1172 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1173 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
337aadff | 1174 | |
337aadff | 1175 | /* Are any of the regs PCC ?*/ |
158c998e AC |
1176 | if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || |
1177 | CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { | |
85b1407b | 1178 | down_write(&pcc_ss_data->pcc_lock); |
850d64a4 | 1179 | regs_in_pcc = 1; |
337aadff | 1180 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1181 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1182 | ret = -EIO; |
1183 | goto out_err; | |
1184 | } | |
1185 | } | |
1186 | ||
a6cbcdd5 SP |
1187 | cpc_read(cpunum, delivered_reg, &delivered); |
1188 | cpc_read(cpunum, reference_reg, &reference); | |
1189 | cpc_read(cpunum, ref_perf_reg, &ref_perf); | |
158c998e AC |
1190 | |
1191 | /* | |
1192 | * Per spec, if ctr_wrap_time optional register is unsupported, then the | |
1193 | * performance counters are assumed to never wrap during the lifetime of | |
1194 | * platform | |
1195 | */ | |
1196 | ctr_wrap_time = (u64)(~((u64)0)); | |
1197 | if (CPC_SUPPORTED(ctr_wrap_reg)) | |
a6cbcdd5 | 1198 | cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); |
337aadff | 1199 | |
158c998e | 1200 | if (!delivered || !reference || !ref_perf) { |
337aadff AC |
1201 | ret = -EFAULT; |
1202 | goto out_err; | |
1203 | } | |
1204 | ||
1205 | perf_fb_ctrs->delivered = delivered; | |
1206 | perf_fb_ctrs->reference = reference; | |
158c998e | 1207 | perf_fb_ctrs->reference_perf = ref_perf; |
2c74d847 | 1208 | perf_fb_ctrs->wraparound_time = ctr_wrap_time; |
337aadff | 1209 | out_err: |
850d64a4 | 1210 | if (regs_in_pcc) |
85b1407b | 1211 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1212 | return ret; |
1213 | } | |
1214 | EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); | |
1215 | ||
1216 | /** | |
1217 | * cppc_set_perf - Set a CPUs performance controls. | |
1218 | * @cpu: CPU for which to set performance controls. | |
1219 | * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h | |
1220 | * | |
1221 | * Return: 0 for success, -ERRNO otherwise. | |
1222 | */ | |
1223 | int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) | |
1224 | { | |
1225 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1226 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1227 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
951ef0e1 | 1228 | struct cppc_pcc_data *pcc_ss_data; |
337aadff AC |
1229 | int ret = 0; |
1230 | ||
1ecbd717 | 1231 | if (!cpc_desc || pcc_ss_id < 0) { |
337aadff AC |
1232 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); |
1233 | return -ENODEV; | |
1234 | } | |
1235 | ||
1ecbd717 | 1236 | pcc_ss_data = pcc_data[pcc_ss_id]; |
337aadff AC |
1237 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; |
1238 | ||
80b8286a PP |
1239 | /* |
1240 | * This is Phase-I where we want to write to CPC registers | |
1241 | * -> We want all CPUs to be able to execute this phase in parallel | |
1242 | * | |
1243 | * Since read_lock can be acquired by multiple CPUs simultaneously we | |
1244 | * achieve that goal here | |
1245 | */ | |
1246 | if (CPC_IN_PCC(desired_reg)) { | |
85b1407b GC |
1247 | down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ |
1248 | if (pcc_ss_data->platform_owns_pcc) { | |
1249 | ret = check_pcc_chan(pcc_ss_id, false); | |
80b8286a | 1250 | if (ret) { |
85b1407b | 1251 | up_read(&pcc_ss_data->pcc_lock); |
80b8286a PP |
1252 | return ret; |
1253 | } | |
80b8286a | 1254 | } |
139aee73 PP |
1255 | /* |
1256 | * Update the pending_write to make sure a PCC CMD_READ will not | |
1257 | * arrive and steal the channel during the switch to write lock | |
1258 | */ | |
85b1407b GC |
1259 | pcc_ss_data->pending_pcc_write_cmd = true; |
1260 | cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; | |
80b8286a | 1261 | cpc_desc->write_cmd_status = 0; |
ad62e1e6 AC |
1262 | } |
1263 | ||
337aadff AC |
1264 | /* |
1265 | * Skip writing MIN/MAX until Linux knows how to come up with | |
1266 | * useful values. | |
1267 | */ | |
a6cbcdd5 | 1268 | cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); |
337aadff | 1269 | |
80b8286a | 1270 | if (CPC_IN_PCC(desired_reg)) |
85b1407b | 1271 | up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ |
80b8286a PP |
1272 | /* |
1273 | * This is Phase-II where we transfer the ownership of PCC to Platform | |
1274 | * | |
1275 | * Short Summary: Basically if we think of a group of cppc_set_perf | |
1276 | * requests that happened in short overlapping interval. The last CPU to | |
1277 | * come out of Phase-I will enter Phase-II and ring the doorbell. | |
1278 | * | |
1279 | * We have the following requirements for Phase-II: | |
1280 | * 1. We want to execute Phase-II only when there are no CPUs | |
1281 | * currently executing in Phase-I | |
1282 | * 2. Once we start Phase-II we want to avoid all other CPUs from | |
1283 | * entering Phase-I. | |
1284 | * 3. We want only one CPU among all those who went through Phase-I | |
1285 | * to run phase-II | |
1286 | * | |
1287 | * If write_trylock fails to get the lock and doesn't transfer the | |
1288 | * PCC ownership to the platform, then one of the following will be TRUE | |
1289 | * 1. There is at-least one CPU in Phase-I which will later execute | |
1290 | * write_trylock, so the CPUs in Phase-I will be responsible for | |
1291 | * executing the Phase-II. | |
1292 | * 2. Some other CPU has beaten this CPU to successfully execute the | |
1293 | * write_trylock and has already acquired the write_lock. We know for a | |
1294 | * fact it(other CPU acquiring the write_lock) couldn't have happened | |
1295 | * before this CPU's Phase-I as we held the read_lock. | |
1296 | * 3. Some other CPU executing pcc CMD_READ has stolen the | |
1297 | * down_write, in which case, send_pcc_cmd will check for pending | |
1298 | * CMD_WRITE commands by checking the pending_pcc_write_cmd. | |
1299 | * So this CPU can be certain that its request will be delivered | |
1300 | * So in all cases, this CPU knows that its request will be delivered | |
1301 | * by another CPU and can return | |
1302 | * | |
1303 | * After getting the down_write we still need to check for | |
1304 | * pending_pcc_write_cmd to take care of the following scenario | |
1305 | * The thread running this code could be scheduled out between | |
1306 | * Phase-I and Phase-II. Before it is scheduled back on, another CPU | |
1307 | * could have delivered the request to Platform by triggering the | |
1308 | * doorbell and transferred the ownership of PCC to platform. So this | |
1309 | * avoids triggering an unnecessary doorbell and more importantly before | |
1310 | * triggering the doorbell it makes sure that the PCC channel ownership | |
1311 | * is still with OSPM. | |
1312 | * pending_pcc_write_cmd can also be cleared by a different CPU, if | |
1313 | * there was a pcc CMD_READ waiting on down_write and it steals the lock | |
1314 | * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this | |
1315 | * case during a CMD_READ and if there are pending writes it delivers | |
1316 | * the write command before servicing the read command | |
1317 | */ | |
1318 | if (CPC_IN_PCC(desired_reg)) { | |
85b1407b | 1319 | if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ |
80b8286a | 1320 | /* Update only if there are pending write commands */ |
85b1407b GC |
1321 | if (pcc_ss_data->pending_pcc_write_cmd) |
1322 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
1323 | up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ | |
80b8286a PP |
1324 | } else |
1325 | /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ | |
85b1407b GC |
1326 | wait_event(pcc_ss_data->pcc_write_wait_q, |
1327 | cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); | |
80b8286a PP |
1328 | |
1329 | /* send_pcc_cmd updates the status in case of failure */ | |
1330 | ret = cpc_desc->write_cmd_status; | |
337aadff | 1331 | } |
337aadff AC |
1332 | return ret; |
1333 | } | |
1334 | EXPORT_SYMBOL_GPL(cppc_set_perf); | |
be8b88d7 PP |
1335 | |
1336 | /** | |
1337 | * cppc_get_transition_latency - returns frequency transition latency in ns | |
1338 | * | |
1339 | * ACPI CPPC does not explicitly specifiy how a platform can specify the | |
1340 | * transition latency for perfromance change requests. The closest we have | |
1341 | * is the timing information from the PCCT tables which provides the info | |
1342 | * on the number and frequency of PCC commands the platform can handle. | |
1343 | */ | |
1344 | unsigned int cppc_get_transition_latency(int cpu_num) | |
1345 | { | |
1346 | /* | |
1347 | * Expected transition latency is based on the PCCT timing values | |
1348 | * Below are definition from ACPI spec: | |
1349 | * pcc_nominal- Expected latency to process a command, in microseconds | |
1350 | * pcc_mpar - The maximum number of periodic requests that the subspace | |
1351 | * channel can support, reported in commands per minute. 0 | |
1352 | * indicates no limitation. | |
1353 | * pcc_mrtt - The minimum amount of time that OSPM must wait after the | |
1354 | * completion of a command before issuing the next command, | |
1355 | * in microseconds. | |
1356 | */ | |
1357 | unsigned int latency_ns = 0; | |
1358 | struct cpc_desc *cpc_desc; | |
1359 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1360 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); |
1ecbd717 | 1361 | struct cppc_pcc_data *pcc_ss_data; |
be8b88d7 PP |
1362 | |
1363 | cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); | |
1364 | if (!cpc_desc) | |
1365 | return CPUFREQ_ETERNAL; | |
1366 | ||
1367 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1368 | if (!CPC_IN_PCC(desired_reg)) | |
1369 | return CPUFREQ_ETERNAL; | |
1370 | ||
1ecbd717 GC |
1371 | if (pcc_ss_id < 0) |
1372 | return CPUFREQ_ETERNAL; | |
1373 | ||
1374 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1375 | if (pcc_ss_data->pcc_mpar) |
1376 | latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); | |
be8b88d7 | 1377 | |
85b1407b GC |
1378 | latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); |
1379 | latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); | |
be8b88d7 PP |
1380 | |
1381 | return latency_ns; | |
1382 | } | |
1383 | EXPORT_SYMBOL_GPL(cppc_get_transition_latency); |