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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
337aadff AC |
2 | /* |
3 | * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. | |
4 | * | |
5 | * (C) Copyright 2014, 2015 Linaro Ltd. | |
6 | * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> | |
7 | * | |
337aadff AC |
8 | * CPPC describes a few methods for controlling CPU performance using |
9 | * information from a per CPU table called CPC. This table is described in | |
10 | * the ACPI v5.0+ specification. The table consists of a list of | |
11 | * registers which may be memory mapped or hardware registers and also may | |
12 | * include some static integer values. | |
13 | * | |
14 | * CPU performance is on an abstract continuous scale as against a discretized | |
15 | * P-state scale which is tied to CPU frequency only. In brief, the basic | |
16 | * operation involves: | |
17 | * | |
18 | * - OS makes a CPU performance request. (Can provide min and max bounds) | |
19 | * | |
20 | * - Platform (such as BMC) is free to optimize request within requested bounds | |
21 | * depending on power/thermal budgets etc. | |
22 | * | |
23 | * - Platform conveys its decision back to OS | |
24 | * | |
25 | * The communication between OS and platform occurs through another medium | |
26 | * called (PCC) Platform Communication Channel. This is a generic mailbox like | |
27 | * mechanism which includes doorbell semantics to indicate register updates. | |
28 | * See drivers/mailbox/pcc.c for details on PCC. | |
29 | * | |
30 | * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and | |
31 | * above specifications. | |
32 | */ | |
33 | ||
34 | #define pr_fmt(fmt) "ACPI CPPC: " fmt | |
35 | ||
337aadff | 36 | #include <linux/delay.h> |
58e1c035 | 37 | #include <linux/iopoll.h> |
ad62e1e6 | 38 | #include <linux/ktime.h> |
80b8286a PP |
39 | #include <linux/rwsem.h> |
40 | #include <linux/wait.h> | |
41ea6672 | 41 | #include <linux/topology.h> |
337aadff AC |
42 | |
43 | #include <acpi/cppc_acpi.h> | |
80b8286a | 44 | |
8482ef8c | 45 | struct cppc_pcc_data { |
7b6da7fe | 46 | struct pcc_mbox_chan *pcc_channel; |
8482ef8c | 47 | void __iomem *pcc_comm_addr; |
8482ef8c | 48 | bool pcc_channel_acquired; |
58e1c035 | 49 | unsigned int deadline_us; |
8482ef8c | 50 | unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; |
80b8286a | 51 | |
8482ef8c | 52 | bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ |
139aee73 | 53 | bool platform_owns_pcc; /* Ownership of PCC subspace */ |
8482ef8c | 54 | unsigned int pcc_write_cnt; /* Running count of PCC write commands */ |
80b8286a | 55 | |
8482ef8c PP |
56 | /* |
57 | * Lock to provide controlled access to the PCC channel. | |
58 | * | |
59 | * For performance critical usecases(currently cppc_set_perf) | |
60 | * We need to take read_lock and check if channel belongs to OSPM | |
61 | * before reading or writing to PCC subspace | |
62 | * We need to take write_lock before transferring the channel | |
63 | * ownership to the platform via a Doorbell | |
64 | * This allows us to batch a number of CPPC requests if they happen | |
65 | * to originate in about the same time | |
66 | * | |
67 | * For non-performance critical usecases(init) | |
68 | * Take write_lock for all purposes which gives exclusive access | |
69 | */ | |
70 | struct rw_semaphore pcc_lock; | |
71 | ||
72 | /* Wait queue for CPUs whose requests were batched */ | |
73 | wait_queue_head_t pcc_write_wait_q; | |
85b1407b GC |
74 | ktime_t last_cmd_cmpl_time; |
75 | ktime_t last_mpar_reset; | |
76 | int mpar_count; | |
77 | int refcount; | |
8482ef8c | 78 | }; |
80b8286a | 79 | |
603fadf3 | 80 | /* Array to represent the PCC channel per subspace ID */ |
85b1407b | 81 | static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; |
603fadf3 | 82 | /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ |
85b1407b | 83 | static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); |
337aadff AC |
84 | |
85 | /* | |
86 | * The cpc_desc structure contains the ACPI register details | |
87 | * as described in the per CPU _CPC tables. The details | |
88 | * include the type of register (e.g. PCC, System IO, FFH etc.) | |
89 | * and destination addresses which lets us READ/WRITE CPU performance | |
90 | * information using the appropriate I/O methods. | |
91 | */ | |
92 | static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); | |
93 | ||
77e3d86f | 94 | /* pcc mapped address + header size + offset within PCC subspace */ |
85b1407b GC |
95 | #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ |
96 | 0x8 + (offs)) | |
77e3d86f | 97 | |
ad61dd30 | 98 | /* Check if a CPC register is in PCC */ |
80b8286a PP |
99 | #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ |
100 | (cpc)->cpc_entry.reg.space_id == \ | |
101 | ACPI_ADR_SPACE_PLATFORM_COMM) | |
102 | ||
935ab850 | 103 | /* Evaluates to True if reg is a NULL register descriptor */ |
158c998e AC |
104 | #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ |
105 | (reg)->address == 0 && \ | |
106 | (reg)->bit_width == 0 && \ | |
107 | (reg)->bit_offset == 0 && \ | |
108 | (reg)->access_width == 0) | |
109 | ||
935ab850 | 110 | /* Evaluates to True if an optional cpc field is supported */ |
158c998e AC |
111 | #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ |
112 | !!(cpc)->cpc_entry.int_value : \ | |
113 | !IS_NULL_REG(&(cpc)->cpc_entry.reg)) | |
337aadff AC |
114 | /* |
115 | * Arbitrary Retries in case the remote processor is slow to respond | |
ad62e1e6 AC |
116 | * to PCC commands. Keeping it high enough to cover emulators where |
117 | * the processors run painfully slow. | |
337aadff | 118 | */ |
b52f4511 | 119 | #define NUM_RETRIES 500ULL |
337aadff | 120 | |
a2c8f92b SN |
121 | #define OVER_16BTS_MASK ~0xFFFFULL |
122 | ||
158c998e | 123 | #define define_one_cppc_ro(_name) \ |
2bc6262c | 124 | static struct kobj_attribute _name = \ |
158c998e AC |
125 | __ATTR(_name, 0444, show_##_name, NULL) |
126 | ||
127 | #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) | |
128 | ||
2c74d847 PP |
129 | #define show_cppc_data(access_fn, struct_name, member_name) \ |
130 | static ssize_t show_##member_name(struct kobject *kobj, \ | |
2bc6262c | 131 | struct kobj_attribute *attr, char *buf) \ |
2c74d847 PP |
132 | { \ |
133 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ | |
134 | struct struct_name st_name = {0}; \ | |
135 | int ret; \ | |
136 | \ | |
137 | ret = access_fn(cpc_ptr->cpu_id, &st_name); \ | |
138 | if (ret) \ | |
139 | return ret; \ | |
140 | \ | |
141 | return scnprintf(buf, PAGE_SIZE, "%llu\n", \ | |
142 | (u64)st_name.member_name); \ | |
143 | } \ | |
144 | define_one_cppc_ro(member_name) | |
145 | ||
146 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); | |
147 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); | |
148 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); | |
149 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); | |
4773e77c PP |
150 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); |
151 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); | |
152 | ||
2c74d847 PP |
153 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); |
154 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); | |
155 | ||
158c998e | 156 | static ssize_t show_feedback_ctrs(struct kobject *kobj, |
2bc6262c | 157 | struct kobj_attribute *attr, char *buf) |
158c998e AC |
158 | { |
159 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
160 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
2c74d847 | 161 | int ret; |
158c998e | 162 | |
2c74d847 PP |
163 | ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); |
164 | if (ret) | |
165 | return ret; | |
158c998e AC |
166 | |
167 | return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", | |
168 | fb_ctrs.reference, fb_ctrs.delivered); | |
169 | } | |
170 | define_one_cppc_ro(feedback_ctrs); | |
171 | ||
158c998e AC |
172 | static struct attribute *cppc_attrs[] = { |
173 | &feedback_ctrs.attr, | |
174 | &reference_perf.attr, | |
175 | &wraparound_time.attr, | |
2c74d847 PP |
176 | &highest_perf.attr, |
177 | &lowest_perf.attr, | |
178 | &lowest_nonlinear_perf.attr, | |
179 | &nominal_perf.attr, | |
4773e77c PP |
180 | &nominal_freq.attr, |
181 | &lowest_freq.attr, | |
158c998e AC |
182 | NULL |
183 | }; | |
184 | ||
185 | static struct kobj_type cppc_ktype = { | |
186 | .sysfs_ops = &kobj_sysfs_ops, | |
187 | .default_attrs = cppc_attrs, | |
188 | }; | |
189 | ||
85b1407b | 190 | static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) |
ad62e1e6 | 191 | { |
58e1c035 | 192 | int ret, status; |
85b1407b GC |
193 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
194 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = | |
195 | pcc_ss_data->pcc_comm_addr; | |
ad62e1e6 | 196 | |
85b1407b | 197 | if (!pcc_ss_data->platform_owns_pcc) |
139aee73 PP |
198 | return 0; |
199 | ||
58e1c035 PP |
200 | /* |
201 | * Poll PCC status register every 3us(delay_us) for maximum of | |
202 | * deadline_us(timeout_us) until PCC command complete bit is set(cond) | |
203 | */ | |
204 | ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, | |
205 | status & PCC_CMD_COMPLETE_MASK, 3, | |
206 | pcc_ss_data->deadline_us); | |
ad62e1e6 | 207 | |
58e1c035 | 208 | if (likely(!ret)) { |
85b1407b | 209 | pcc_ss_data->platform_owns_pcc = false; |
58e1c035 PP |
210 | if (chk_err_bit && (status & PCC_ERROR_MASK)) |
211 | ret = -EIO; | |
212 | } | |
213 | ||
214 | if (unlikely(ret)) | |
215 | pr_err("PCC check channel failed for ss: %d. ret=%d\n", | |
216 | pcc_ss_id, ret); | |
139aee73 | 217 | |
ad62e1e6 AC |
218 | return ret; |
219 | } | |
220 | ||
80b8286a PP |
221 | /* |
222 | * This function transfers the ownership of the PCC to the platform | |
223 | * So it must be called while holding write_lock(pcc_lock) | |
224 | */ | |
85b1407b | 225 | static int send_pcc_cmd(int pcc_ss_id, u16 cmd) |
337aadff | 226 | { |
80b8286a | 227 | int ret = -EIO, i; |
85b1407b | 228 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
1d9b4abe IV |
229 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = |
230 | pcc_ss_data->pcc_comm_addr; | |
f387e5b9 | 231 | unsigned int time_delta; |
337aadff | 232 | |
ad62e1e6 AC |
233 | /* |
234 | * For CMD_WRITE we know for a fact the caller should have checked | |
235 | * the channel before writing to PCC space | |
236 | */ | |
237 | if (cmd == CMD_READ) { | |
80b8286a PP |
238 | /* |
239 | * If there are pending cpc_writes, then we stole the channel | |
240 | * before write completion, so first send a WRITE command to | |
241 | * platform | |
242 | */ | |
85b1407b GC |
243 | if (pcc_ss_data->pending_pcc_write_cmd) |
244 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
80b8286a | 245 | |
85b1407b | 246 | ret = check_pcc_chan(pcc_ss_id, false); |
ad62e1e6 | 247 | if (ret) |
80b8286a PP |
248 | goto end; |
249 | } else /* CMD_WRITE */ | |
85b1407b | 250 | pcc_ss_data->pending_pcc_write_cmd = FALSE; |
337aadff | 251 | |
f387e5b9 PP |
252 | /* |
253 | * Handle the Minimum Request Turnaround Time(MRTT) | |
254 | * "The minimum amount of time that OSPM must wait after the completion | |
255 | * of a command before issuing the next command, in microseconds" | |
256 | */ | |
85b1407b GC |
257 | if (pcc_ss_data->pcc_mrtt) { |
258 | time_delta = ktime_us_delta(ktime_get(), | |
259 | pcc_ss_data->last_cmd_cmpl_time); | |
260 | if (pcc_ss_data->pcc_mrtt > time_delta) | |
261 | udelay(pcc_ss_data->pcc_mrtt - time_delta); | |
f387e5b9 PP |
262 | } |
263 | ||
264 | /* | |
265 | * Handle the non-zero Maximum Periodic Access Rate(MPAR) | |
266 | * "The maximum number of periodic requests that the subspace channel can | |
267 | * support, reported in commands per minute. 0 indicates no limitation." | |
268 | * | |
269 | * This parameter should be ideally zero or large enough so that it can | |
270 | * handle maximum number of requests that all the cores in the system can | |
271 | * collectively generate. If it is not, we will follow the spec and just | |
272 | * not send the request to the platform after hitting the MPAR limit in | |
273 | * any 60s window | |
274 | */ | |
85b1407b GC |
275 | if (pcc_ss_data->pcc_mpar) { |
276 | if (pcc_ss_data->mpar_count == 0) { | |
277 | time_delta = ktime_ms_delta(ktime_get(), | |
278 | pcc_ss_data->last_mpar_reset); | |
279 | if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { | |
d29abc83 GC |
280 | pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", |
281 | pcc_ss_id); | |
80b8286a PP |
282 | ret = -EIO; |
283 | goto end; | |
f387e5b9 | 284 | } |
85b1407b GC |
285 | pcc_ss_data->last_mpar_reset = ktime_get(); |
286 | pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; | |
f387e5b9 | 287 | } |
85b1407b | 288 | pcc_ss_data->mpar_count--; |
f387e5b9 PP |
289 | } |
290 | ||
337aadff | 291 | /* Write to the shared comm region. */ |
beee23ae | 292 | writew_relaxed(cmd, &generic_comm_base->command); |
337aadff AC |
293 | |
294 | /* Flip CMD COMPLETE bit */ | |
beee23ae | 295 | writew_relaxed(0, &generic_comm_base->status); |
337aadff | 296 | |
85b1407b | 297 | pcc_ss_data->platform_owns_pcc = true; |
139aee73 | 298 | |
337aadff | 299 | /* Ring doorbell */ |
7b6da7fe | 300 | ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd); |
ad62e1e6 | 301 | if (ret < 0) { |
d29abc83 GC |
302 | pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", |
303 | pcc_ss_id, cmd, ret); | |
80b8286a | 304 | goto end; |
337aadff AC |
305 | } |
306 | ||
139aee73 | 307 | /* wait for completion and check for PCC errro bit */ |
85b1407b | 308 | ret = check_pcc_chan(pcc_ss_id, true); |
139aee73 | 309 | |
85b1407b GC |
310 | if (pcc_ss_data->pcc_mrtt) |
311 | pcc_ss_data->last_cmd_cmpl_time = ktime_get(); | |
337aadff | 312 | |
7b6da7fe SH |
313 | if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq) |
314 | mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret); | |
b59c4b3d | 315 | else |
7b6da7fe | 316 | mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret); |
80b8286a PP |
317 | |
318 | end: | |
319 | if (cmd == CMD_WRITE) { | |
320 | if (unlikely(ret)) { | |
321 | for_each_possible_cpu(i) { | |
322 | struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); | |
e69ae675 | 323 | |
80b8286a PP |
324 | if (!desc) |
325 | continue; | |
326 | ||
85b1407b | 327 | if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) |
80b8286a PP |
328 | desc->write_cmd_status = ret; |
329 | } | |
330 | } | |
85b1407b GC |
331 | pcc_ss_data->pcc_write_cnt++; |
332 | wake_up_all(&pcc_ss_data->pcc_write_wait_q); | |
80b8286a PP |
333 | } |
334 | ||
ad62e1e6 | 335 | return ret; |
337aadff AC |
336 | } |
337 | ||
338 | static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) | |
339 | { | |
ad62e1e6 | 340 | if (ret < 0) |
337aadff AC |
341 | pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", |
342 | *(u16 *)msg, ret); | |
343 | else | |
344 | pr_debug("TX completed. CMD sent:%x, ret:%d\n", | |
345 | *(u16 *)msg, ret); | |
346 | } | |
347 | ||
5c447c18 | 348 | static struct mbox_client cppc_mbox_cl = { |
337aadff AC |
349 | .tx_done = cppc_chan_tx_done, |
350 | .knows_txdone = true, | |
351 | }; | |
352 | ||
353 | static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) | |
354 | { | |
355 | int result = -EFAULT; | |
356 | acpi_status status = AE_OK; | |
357 | struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; | |
358 | struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; | |
359 | struct acpi_buffer state = {0, NULL}; | |
360 | union acpi_object *psd = NULL; | |
361 | struct acpi_psd_package *pdomain; | |
362 | ||
4c4cdc4c AS |
363 | status = acpi_evaluate_object_typed(handle, "_PSD", NULL, |
364 | &buffer, ACPI_TYPE_PACKAGE); | |
365 | if (status == AE_NOT_FOUND) /* _PSD is optional */ | |
366 | return 0; | |
337aadff AC |
367 | if (ACPI_FAILURE(status)) |
368 | return -ENODEV; | |
369 | ||
370 | psd = buffer.pointer; | |
371 | if (!psd || psd->package.count != 1) { | |
372 | pr_debug("Invalid _PSD data\n"); | |
373 | goto end; | |
374 | } | |
375 | ||
376 | pdomain = &(cpc_ptr->domain_info); | |
377 | ||
378 | state.length = sizeof(struct acpi_psd_package); | |
379 | state.pointer = pdomain; | |
380 | ||
381 | status = acpi_extract_package(&(psd->package.elements[0]), | |
382 | &format, &state); | |
383 | if (ACPI_FAILURE(status)) { | |
384 | pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); | |
385 | goto end; | |
386 | } | |
387 | ||
388 | if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { | |
389 | pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); | |
390 | goto end; | |
391 | } | |
392 | ||
393 | if (pdomain->revision != ACPI_PSD_REV0_REVISION) { | |
394 | pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); | |
395 | goto end; | |
396 | } | |
397 | ||
398 | if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && | |
399 | pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && | |
400 | pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { | |
401 | pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); | |
402 | goto end; | |
403 | } | |
404 | ||
405 | result = 0; | |
406 | end: | |
407 | kfree(buffer.pointer); | |
408 | return result; | |
409 | } | |
410 | ||
a28b2bfc IV |
411 | bool acpi_cpc_valid(void) |
412 | { | |
413 | struct cpc_desc *cpc_ptr; | |
414 | int cpu; | |
415 | ||
2aeca6bd | 416 | for_each_present_cpu(cpu) { |
a28b2bfc IV |
417 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); |
418 | if (!cpc_ptr) | |
419 | return false; | |
420 | } | |
421 | ||
422 | return true; | |
423 | } | |
424 | EXPORT_SYMBOL_GPL(acpi_cpc_valid); | |
425 | ||
337aadff | 426 | /** |
a28b2bfc IV |
427 | * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu |
428 | * @cpu: Find all CPUs that share a domain with cpu. | |
429 | * @cpu_data: Pointer to CPU specific CPPC data including PSD info. | |
337aadff AC |
430 | * |
431 | * Return: 0 for success or negative value for err. | |
432 | */ | |
a28b2bfc | 433 | int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) |
337aadff | 434 | { |
337aadff | 435 | struct cpc_desc *cpc_ptr, *match_cpc_ptr; |
a28b2bfc IV |
436 | struct acpi_psd_package *match_pdomain; |
437 | struct acpi_psd_package *pdomain; | |
438 | int count_target, i; | |
337aadff AC |
439 | |
440 | /* | |
603fadf3 | 441 | * Now that we have _PSD data from all CPUs, let's setup P-state |
337aadff AC |
442 | * domain info. |
443 | */ | |
a28b2bfc IV |
444 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); |
445 | if (!cpc_ptr) | |
446 | return -EFAULT; | |
337aadff | 447 | |
a28b2bfc IV |
448 | pdomain = &(cpc_ptr->domain_info); |
449 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
450 | if (pdomain->num_processors <= 1) | |
451 | return 0; | |
337aadff | 452 | |
a28b2bfc IV |
453 | /* Validate the Domain info */ |
454 | count_target = pdomain->num_processors; | |
455 | if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) | |
456 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
457 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) | |
458 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW; | |
459 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) | |
460 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
337aadff | 461 | |
a28b2bfc IV |
462 | for_each_possible_cpu(i) { |
463 | if (i == cpu) | |
464 | continue; | |
337aadff | 465 | |
a28b2bfc IV |
466 | match_cpc_ptr = per_cpu(cpc_desc_ptr, i); |
467 | if (!match_cpc_ptr) | |
468 | goto err_fault; | |
337aadff | 469 | |
a28b2bfc IV |
470 | match_pdomain = &(match_cpc_ptr->domain_info); |
471 | if (match_pdomain->domain != pdomain->domain) | |
472 | continue; | |
337aadff | 473 | |
a28b2bfc IV |
474 | /* Here i and cpu are in the same domain */ |
475 | if (match_pdomain->num_processors != count_target) | |
476 | goto err_fault; | |
337aadff | 477 | |
a28b2bfc IV |
478 | if (pdomain->coord_type != match_pdomain->coord_type) |
479 | goto err_fault; | |
337aadff | 480 | |
a28b2bfc | 481 | cpumask_set_cpu(i, cpu_data->shared_cpu_map); |
337aadff AC |
482 | } |
483 | ||
a28b2bfc | 484 | return 0; |
337aadff | 485 | |
a28b2bfc IV |
486 | err_fault: |
487 | /* Assume no coordination on any error parsing domain info */ | |
488 | cpumask_clear(cpu_data->shared_cpu_map); | |
489 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
490 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE; | |
491 | ||
492 | return -EFAULT; | |
337aadff AC |
493 | } |
494 | EXPORT_SYMBOL_GPL(acpi_get_psd_map); | |
495 | ||
85b1407b | 496 | static int register_pcc_channel(int pcc_ss_idx) |
337aadff | 497 | { |
7b6da7fe | 498 | struct pcc_mbox_chan *pcc_chan; |
ad62e1e6 | 499 | u64 usecs_lat; |
337aadff | 500 | |
85b1407b | 501 | if (pcc_ss_idx >= 0) { |
7b6da7fe | 502 | pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); |
337aadff | 503 | |
7b6da7fe | 504 | if (IS_ERR(pcc_chan)) { |
d29abc83 GC |
505 | pr_err("Failed to find PCC channel for subspace %d\n", |
506 | pcc_ss_idx); | |
337aadff AC |
507 | return -ENODEV; |
508 | } | |
509 | ||
7b6da7fe | 510 | pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan; |
ad62e1e6 AC |
511 | /* |
512 | * cppc_ss->latency is just a Nominal value. In reality | |
513 | * the remote processor could be much slower to reply. | |
514 | * So add an arbitrary amount of wait on top of Nominal. | |
515 | */ | |
7b6da7fe | 516 | usecs_lat = NUM_RETRIES * pcc_chan->latency; |
58e1c035 | 517 | pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; |
7b6da7fe SH |
518 | pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time; |
519 | pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate; | |
520 | pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency; | |
85b1407b GC |
521 | |
522 | pcc_data[pcc_ss_idx]->pcc_comm_addr = | |
7b6da7fe SH |
523 | acpi_os_ioremap(pcc_chan->shmem_base_addr, |
524 | pcc_chan->shmem_size); | |
85b1407b | 525 | if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { |
d29abc83 GC |
526 | pr_err("Failed to ioremap PCC comm region mem for %d\n", |
527 | pcc_ss_idx); | |
337aadff AC |
528 | return -ENOMEM; |
529 | } | |
530 | ||
603fadf3 | 531 | /* Set flag so that we don't come here for each CPU. */ |
85b1407b | 532 | pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; |
337aadff AC |
533 | } |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
a6cbcdd5 SP |
538 | /** |
539 | * cpc_ffh_supported() - check if FFH reading supported | |
540 | * | |
541 | * Check if the architecture has support for functional fixed hardware | |
542 | * read/write capability. | |
543 | * | |
544 | * Return: true for supported, false for not supported | |
545 | */ | |
546 | bool __weak cpc_ffh_supported(void) | |
547 | { | |
548 | return false; | |
549 | } | |
550 | ||
85b1407b GC |
551 | /** |
552 | * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace | |
553 | * | |
554 | * Check and allocate the cppc_pcc_data memory. | |
555 | * In some processor configurations it is possible that same subspace | |
603fadf3 | 556 | * is shared between multiple CPUs. This is seen especially in CPUs |
85b1407b GC |
557 | * with hardware multi-threading support. |
558 | * | |
559 | * Return: 0 for success, errno for failure | |
560 | */ | |
5c447c18 | 561 | static int pcc_data_alloc(int pcc_ss_id) |
85b1407b GC |
562 | { |
563 | if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) | |
564 | return -EINVAL; | |
565 | ||
566 | if (pcc_data[pcc_ss_id]) { | |
567 | pcc_data[pcc_ss_id]->refcount++; | |
568 | } else { | |
569 | pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), | |
570 | GFP_KERNEL); | |
571 | if (!pcc_data[pcc_ss_id]) | |
572 | return -ENOMEM; | |
573 | pcc_data[pcc_ss_id]->refcount++; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
4773e77c PP |
578 | |
579 | /* Check if CPPC revision + num_ent combination is supported */ | |
580 | static bool is_cppc_supported(int revision, int num_ent) | |
581 | { | |
582 | int expected_num_ent; | |
583 | ||
584 | switch (revision) { | |
585 | case CPPC_V2_REV: | |
586 | expected_num_ent = CPPC_V2_NUM_ENT; | |
587 | break; | |
588 | case CPPC_V3_REV: | |
589 | expected_num_ent = CPPC_V3_NUM_ENT; | |
590 | break; | |
591 | default: | |
592 | pr_debug("Firmware exports unsupported CPPC revision: %d\n", | |
593 | revision); | |
594 | return false; | |
595 | } | |
596 | ||
597 | if (expected_num_ent != num_ent) { | |
598 | pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n", | |
599 | num_ent, expected_num_ent, revision); | |
600 | return false; | |
601 | } | |
602 | ||
603 | return true; | |
604 | } | |
605 | ||
337aadff AC |
606 | /* |
607 | * An example CPC table looks like the following. | |
608 | * | |
609 | * Name(_CPC, Package() | |
610 | * { | |
611 | * 17, | |
612 | * NumEntries | |
613 | * 1, | |
614 | * // Revision | |
615 | * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, | |
616 | * // Highest Performance | |
617 | * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, | |
618 | * // Nominal Performance | |
619 | * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, | |
620 | * // Lowest Nonlinear Performance | |
621 | * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, | |
622 | * // Lowest Performance | |
623 | * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, | |
624 | * // Guaranteed Performance Register | |
625 | * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, | |
626 | * // Desired Performance Register | |
627 | * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, | |
628 | * .. | |
629 | * .. | |
630 | * .. | |
631 | * | |
632 | * } | |
633 | * Each Register() encodes how to access that specific register. | |
634 | * e.g. a sample PCC entry has the following encoding: | |
635 | * | |
636 | * Register ( | |
637 | * PCC, | |
638 | * AddressSpaceKeyword | |
639 | * 8, | |
640 | * //RegisterBitWidth | |
641 | * 8, | |
642 | * //RegisterBitOffset | |
643 | * 0x30, | |
644 | * //RegisterAddress | |
645 | * 9 | |
646 | * //AccessSize (subspace ID) | |
647 | * 0 | |
648 | * ) | |
649 | * } | |
650 | */ | |
651 | ||
41ea6672 NF |
652 | #ifndef init_freq_invariance_cppc |
653 | static inline void init_freq_invariance_cppc(void) { } | |
654 | #endif | |
655 | ||
337aadff AC |
656 | /** |
657 | * acpi_cppc_processor_probe - Search for per CPU _CPC objects. | |
603fadf3 | 658 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
659 | * |
660 | * Return: 0 for success or negative value for err. | |
661 | */ | |
662 | int acpi_cppc_processor_probe(struct acpi_processor *pr) | |
663 | { | |
664 | struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; | |
665 | union acpi_object *out_obj, *cpc_obj; | |
666 | struct cpc_desc *cpc_ptr; | |
667 | struct cpc_reg *gas_t; | |
158c998e | 668 | struct device *cpu_dev; |
337aadff AC |
669 | acpi_handle handle = pr->handle; |
670 | unsigned int num_ent, i, cpc_rev; | |
85b1407b | 671 | int pcc_subspace_id = -1; |
337aadff AC |
672 | acpi_status status; |
673 | int ret = -EFAULT; | |
674 | ||
603fadf3 | 675 | /* Parse the ACPI _CPC table for this CPU. */ |
337aadff AC |
676 | status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, |
677 | ACPI_TYPE_PACKAGE); | |
678 | if (ACPI_FAILURE(status)) { | |
679 | ret = -ENODEV; | |
680 | goto out_buf_free; | |
681 | } | |
682 | ||
683 | out_obj = (union acpi_object *) output.pointer; | |
684 | ||
685 | cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); | |
686 | if (!cpc_ptr) { | |
687 | ret = -ENOMEM; | |
688 | goto out_buf_free; | |
689 | } | |
690 | ||
691 | /* First entry is NumEntries. */ | |
692 | cpc_obj = &out_obj->package.elements[0]; | |
693 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
694 | num_ent = cpc_obj->integer.value; | |
695 | } else { | |
696 | pr_debug("Unexpected entry type(%d) for NumEntries\n", | |
697 | cpc_obj->type); | |
698 | goto out_free; | |
699 | } | |
5bbb86aa AC |
700 | cpc_ptr->num_entries = num_ent; |
701 | ||
337aadff AC |
702 | /* Second entry should be revision. */ |
703 | cpc_obj = &out_obj->package.elements[1]; | |
704 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
705 | cpc_rev = cpc_obj->integer.value; | |
706 | } else { | |
707 | pr_debug("Unexpected entry type(%d) for Revision\n", | |
708 | cpc_obj->type); | |
709 | goto out_free; | |
710 | } | |
4773e77c | 711 | cpc_ptr->version = cpc_rev; |
337aadff | 712 | |
4773e77c | 713 | if (!is_cppc_supported(cpc_rev, num_ent)) |
337aadff | 714 | goto out_free; |
337aadff AC |
715 | |
716 | /* Iterate through remaining entries in _CPC */ | |
717 | for (i = 2; i < num_ent; i++) { | |
718 | cpc_obj = &out_obj->package.elements[i]; | |
719 | ||
720 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
721 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; | |
722 | cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; | |
723 | } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { | |
724 | gas_t = (struct cpc_reg *) | |
725 | cpc_obj->buffer.pointer; | |
726 | ||
727 | /* | |
728 | * The PCC Subspace index is encoded inside | |
729 | * the CPC table entries. The same PCC index | |
730 | * will be used for all the PCC entries, | |
731 | * so extract it only once. | |
732 | */ | |
733 | if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { | |
85b1407b GC |
734 | if (pcc_subspace_id < 0) { |
735 | pcc_subspace_id = gas_t->access_width; | |
736 | if (pcc_data_alloc(pcc_subspace_id)) | |
737 | goto out_free; | |
738 | } else if (pcc_subspace_id != gas_t->access_width) { | |
337aadff AC |
739 | pr_debug("Mismatched PCC ids.\n"); |
740 | goto out_free; | |
741 | } | |
5bbb86aa AC |
742 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
743 | if (gas_t->address) { | |
744 | void __iomem *addr; | |
745 | ||
746 | addr = ioremap(gas_t->address, gas_t->bit_width/8); | |
747 | if (!addr) | |
748 | goto out_free; | |
749 | cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; | |
750 | } | |
a2c8f92b SN |
751 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { |
752 | if (gas_t->access_width < 1 || gas_t->access_width > 3) { | |
753 | /* | |
754 | * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. | |
755 | * SystemIO doesn't implement 64-bit | |
756 | * registers. | |
757 | */ | |
758 | pr_debug("Invalid access width %d for SystemIO register\n", | |
759 | gas_t->access_width); | |
760 | goto out_free; | |
761 | } | |
762 | if (gas_t->address & OVER_16BTS_MASK) { | |
763 | /* SystemIO registers use 16-bit integer addresses */ | |
764 | pr_debug("Invalid IO port %llu for SystemIO register\n", | |
765 | gas_t->address); | |
766 | goto out_free; | |
767 | } | |
5bbb86aa | 768 | } else { |
a6cbcdd5 | 769 | if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { |
a2c8f92b | 770 | /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ |
a6cbcdd5 SP |
771 | pr_debug("Unsupported register type: %d\n", gas_t->space_id); |
772 | goto out_free; | |
773 | } | |
337aadff AC |
774 | } |
775 | ||
776 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; | |
777 | memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); | |
778 | } else { | |
e69ae675 | 779 | pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id); |
337aadff AC |
780 | goto out_free; |
781 | } | |
782 | } | |
85b1407b | 783 | per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; |
4773e77c PP |
784 | |
785 | /* | |
786 | * Initialize the remaining cpc_regs as unsupported. | |
787 | * Example: In case FW exposes CPPC v2, the below loop will initialize | |
788 | * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported | |
789 | */ | |
790 | for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { | |
791 | cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; | |
792 | cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; | |
793 | } | |
794 | ||
795 | ||
337aadff AC |
796 | /* Store CPU Logical ID */ |
797 | cpc_ptr->cpu_id = pr->id; | |
798 | ||
337aadff AC |
799 | /* Parse PSD data for this CPU */ |
800 | ret = acpi_get_psd(cpc_ptr, handle); | |
801 | if (ret) | |
802 | goto out_free; | |
803 | ||
603fadf3 | 804 | /* Register PCC channel once for all PCC subspace ID. */ |
85b1407b GC |
805 | if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { |
806 | ret = register_pcc_channel(pcc_subspace_id); | |
337aadff AC |
807 | if (ret) |
808 | goto out_free; | |
8482ef8c | 809 | |
85b1407b GC |
810 | init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); |
811 | init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); | |
337aadff AC |
812 | } |
813 | ||
814 | /* Everything looks okay */ | |
815 | pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); | |
816 | ||
158c998e AC |
817 | /* Add per logical CPU nodes for reading its feedback counters. */ |
818 | cpu_dev = get_cpu_device(pr->id); | |
50163475 DC |
819 | if (!cpu_dev) { |
820 | ret = -EINVAL; | |
158c998e | 821 | goto out_free; |
50163475 | 822 | } |
158c998e | 823 | |
603fadf3 | 824 | /* Plug PSD data into this CPU's CPC descriptor. */ |
28076483 RW |
825 | per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; |
826 | ||
158c998e AC |
827 | ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, |
828 | "acpi_cppc"); | |
28076483 RW |
829 | if (ret) { |
830 | per_cpu(cpc_desc_ptr, pr->id) = NULL; | |
4d8be4bc | 831 | kobject_put(&cpc_ptr->kobj); |
158c998e | 832 | goto out_free; |
28076483 | 833 | } |
158c998e | 834 | |
41ea6672 NF |
835 | init_freq_invariance_cppc(); |
836 | ||
337aadff AC |
837 | kfree(output.pointer); |
838 | return 0; | |
839 | ||
840 | out_free: | |
5bbb86aa AC |
841 | /* Free all the mapped sys mem areas for this CPU */ |
842 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
843 | void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
844 | ||
845 | if (addr) | |
846 | iounmap(addr); | |
847 | } | |
337aadff AC |
848 | kfree(cpc_ptr); |
849 | ||
850 | out_buf_free: | |
851 | kfree(output.pointer); | |
852 | return ret; | |
853 | } | |
854 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); | |
855 | ||
856 | /** | |
857 | * acpi_cppc_processor_exit - Cleanup CPC structs. | |
603fadf3 | 858 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
859 | * |
860 | * Return: Void | |
861 | */ | |
862 | void acpi_cppc_processor_exit(struct acpi_processor *pr) | |
863 | { | |
864 | struct cpc_desc *cpc_ptr; | |
5bbb86aa AC |
865 | unsigned int i; |
866 | void __iomem *addr; | |
85b1407b GC |
867 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); |
868 | ||
e69ae675 | 869 | if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) { |
85b1407b GC |
870 | if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { |
871 | pcc_data[pcc_ss_id]->refcount--; | |
872 | if (!pcc_data[pcc_ss_id]->refcount) { | |
873 | pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); | |
85b1407b | 874 | kfree(pcc_data[pcc_ss_id]); |
56a0b978 | 875 | pcc_data[pcc_ss_id] = NULL; |
85b1407b GC |
876 | } |
877 | } | |
878 | } | |
158c998e | 879 | |
337aadff | 880 | cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); |
9e9d68da SAS |
881 | if (!cpc_ptr) |
882 | return; | |
5bbb86aa AC |
883 | |
884 | /* Free all the mapped sys mem areas for this CPU */ | |
885 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
886 | addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
887 | if (addr) | |
888 | iounmap(addr); | |
889 | } | |
890 | ||
158c998e | 891 | kobject_put(&cpc_ptr->kobj); |
337aadff AC |
892 | kfree(cpc_ptr); |
893 | } | |
894 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); | |
895 | ||
a6cbcdd5 SP |
896 | /** |
897 | * cpc_read_ffh() - Read FFH register | |
603fadf3 | 898 | * @cpunum: CPU number to read |
a6cbcdd5 SP |
899 | * @reg: cppc register information |
900 | * @val: place holder for return value | |
901 | * | |
902 | * Read bit_width bits from a specified address and bit_offset | |
903 | * | |
904 | * Return: 0 for success and error code | |
905 | */ | |
906 | int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | |
907 | { | |
908 | return -ENOTSUPP; | |
909 | } | |
910 | ||
911 | /** | |
912 | * cpc_write_ffh() - Write FFH register | |
603fadf3 | 913 | * @cpunum: CPU number to write |
a6cbcdd5 SP |
914 | * @reg: cppc register information |
915 | * @val: value to write | |
916 | * | |
917 | * Write value of bit_width bits to a specified address and bit_offset | |
918 | * | |
919 | * Return: 0 for success and error code | |
920 | */ | |
921 | int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | |
922 | { | |
923 | return -ENOTSUPP; | |
924 | } | |
925 | ||
77e3d86f PP |
926 | /* |
927 | * Since cpc_read and cpc_write are called while holding pcc_lock, it should be | |
928 | * as fast as possible. We have already mapped the PCC subspace during init, so | |
929 | * we can directly write to it. | |
930 | */ | |
337aadff | 931 | |
a6cbcdd5 | 932 | static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) |
337aadff | 933 | { |
77e3d86f | 934 | int ret_val = 0; |
26692cd9 | 935 | void __iomem *vaddr = NULL; |
85b1407b | 936 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa AC |
937 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
938 | ||
939 | if (reg_res->type == ACPI_TYPE_INTEGER) { | |
940 | *val = reg_res->cpc_entry.int_value; | |
941 | return ret_val; | |
942 | } | |
77e3d86f PP |
943 | |
944 | *val = 0; | |
a2c8f92b SN |
945 | |
946 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { | |
947 | u32 width = 8 << (reg->access_width - 1); | |
948 | acpi_status status; | |
949 | ||
950 | status = acpi_os_read_port((acpi_io_address)reg->address, | |
951 | (u32 *)val, width); | |
952 | if (ACPI_FAILURE(status)) { | |
953 | pr_debug("Error: Failed to read SystemIO port %llx\n", | |
954 | reg->address); | |
955 | return -EFAULT; | |
956 | } | |
957 | ||
958 | return 0; | |
959 | } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) | |
85b1407b | 960 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
961 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
962 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
963 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
964 | return cpc_read_ffh(cpu, reg, val); | |
5bbb86aa AC |
965 | else |
966 | return acpi_os_read_memory((acpi_physical_address)reg->address, | |
967 | val, reg->bit_width); | |
337aadff | 968 | |
5bbb86aa | 969 | switch (reg->bit_width) { |
e69ae675 XT |
970 | case 8: |
971 | *val = readb_relaxed(vaddr); | |
972 | break; | |
973 | case 16: | |
974 | *val = readw_relaxed(vaddr); | |
975 | break; | |
976 | case 32: | |
977 | *val = readl_relaxed(vaddr); | |
978 | break; | |
979 | case 64: | |
980 | *val = readq_relaxed(vaddr); | |
981 | break; | |
982 | default: | |
983 | pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", | |
984 | reg->bit_width, pcc_ss_id); | |
985 | ret_val = -EFAULT; | |
5bbb86aa AC |
986 | } |
987 | ||
77e3d86f | 988 | return ret_val; |
337aadff AC |
989 | } |
990 | ||
a6cbcdd5 | 991 | static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) |
337aadff | 992 | { |
77e3d86f | 993 | int ret_val = 0; |
26692cd9 | 994 | void __iomem *vaddr = NULL; |
85b1407b | 995 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa | 996 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
77e3d86f | 997 | |
a2c8f92b SN |
998 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { |
999 | u32 width = 8 << (reg->access_width - 1); | |
1000 | acpi_status status; | |
1001 | ||
1002 | status = acpi_os_write_port((acpi_io_address)reg->address, | |
1003 | (u32)val, width); | |
1004 | if (ACPI_FAILURE(status)) { | |
1005 | pr_debug("Error: Failed to write SystemIO port %llx\n", | |
1006 | reg->address); | |
1007 | return -EFAULT; | |
1008 | } | |
1009 | ||
1010 | return 0; | |
1011 | } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) | |
85b1407b | 1012 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
1013 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
1014 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
1015 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
1016 | return cpc_write_ffh(cpu, reg, val); | |
5bbb86aa AC |
1017 | else |
1018 | return acpi_os_write_memory((acpi_physical_address)reg->address, | |
1019 | val, reg->bit_width); | |
337aadff | 1020 | |
5bbb86aa | 1021 | switch (reg->bit_width) { |
e69ae675 XT |
1022 | case 8: |
1023 | writeb_relaxed(val, vaddr); | |
1024 | break; | |
1025 | case 16: | |
1026 | writew_relaxed(val, vaddr); | |
1027 | break; | |
1028 | case 32: | |
1029 | writel_relaxed(val, vaddr); | |
1030 | break; | |
1031 | case 64: | |
1032 | writeq_relaxed(val, vaddr); | |
1033 | break; | |
1034 | default: | |
1035 | pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", | |
1036 | reg->bit_width, pcc_ss_id); | |
1037 | ret_val = -EFAULT; | |
1038 | break; | |
5bbb86aa AC |
1039 | } |
1040 | ||
77e3d86f | 1041 | return ret_val; |
337aadff AC |
1042 | } |
1043 | ||
0654cf05 | 1044 | static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) |
1757d05f XW |
1045 | { |
1046 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
935dff30 RW |
1047 | struct cpc_register_resource *reg; |
1048 | ||
1049 | if (!cpc_desc) { | |
1050 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); | |
1051 | return -ENODEV; | |
1052 | } | |
1053 | ||
1054 | reg = &cpc_desc->cpc_regs[reg_idx]; | |
1757d05f | 1055 | |
0654cf05 RW |
1056 | if (CPC_IN_PCC(reg)) { |
1057 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); | |
1058 | struct cppc_pcc_data *pcc_ss_data = NULL; | |
1757d05f XW |
1059 | int ret = 0; |
1060 | ||
1061 | if (pcc_ss_id < 0) | |
1062 | return -EIO; | |
1063 | ||
1064 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
1065 | ||
1066 | down_write(&pcc_ss_data->pcc_lock); | |
1067 | ||
1068 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) | |
0654cf05 | 1069 | cpc_read(cpunum, reg, perf); |
1757d05f XW |
1070 | else |
1071 | ret = -EIO; | |
1072 | ||
1073 | up_write(&pcc_ss_data->pcc_lock); | |
1074 | ||
1075 | return ret; | |
1076 | } | |
1077 | ||
0654cf05 | 1078 | cpc_read(cpunum, reg, perf); |
1757d05f XW |
1079 | |
1080 | return 0; | |
1081 | } | |
0654cf05 RW |
1082 | |
1083 | /** | |
1084 | * cppc_get_desired_perf - Get the desired performance register value. | |
1085 | * @cpunum: CPU from which to get desired performance. | |
1086 | * @desired_perf: Return address. | |
1087 | * | |
1088 | * Return: 0 for success, -EIO otherwise. | |
1089 | */ | |
1090 | int cppc_get_desired_perf(int cpunum, u64 *desired_perf) | |
1091 | { | |
1092 | return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); | |
1093 | } | |
1757d05f XW |
1094 | EXPORT_SYMBOL_GPL(cppc_get_desired_perf); |
1095 | ||
0654cf05 RW |
1096 | /** |
1097 | * cppc_get_nominal_perf - Get the nominal performance register value. | |
1098 | * @cpunum: CPU from which to get nominal performance. | |
1099 | * @nominal_perf: Return address. | |
1100 | * | |
1101 | * Return: 0 for success, -EIO otherwise. | |
1102 | */ | |
1103 | int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) | |
1104 | { | |
1105 | return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); | |
1106 | } | |
1107 | ||
337aadff | 1108 | /** |
603fadf3 | 1109 | * cppc_get_perf_caps - Get a CPU's performance capabilities. |
337aadff AC |
1110 | * @cpunum: CPU from which to get capabilities info. |
1111 | * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h | |
1112 | * | |
1113 | * Return: 0 for success with perf_caps populated else -ERRNO. | |
1114 | */ | |
1115 | int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) | |
1116 | { | |
1117 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
368520a6 | 1118 | struct cpc_register_resource *highest_reg, *lowest_reg, |
29523f09 | 1119 | *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, |
4773e77c | 1120 | *low_freq_reg = NULL, *nom_freq_reg = NULL; |
29523f09 | 1121 | u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; |
85b1407b | 1122 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1123 | struct cppc_pcc_data *pcc_ss_data = NULL; |
850d64a4 | 1124 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1125 | |
6fa12d58 | 1126 | if (!cpc_desc) { |
337aadff AC |
1127 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1128 | return -ENODEV; | |
1129 | } | |
1130 | ||
1131 | highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; | |
1132 | lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; | |
368520a6 PP |
1133 | lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; |
1134 | nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
4773e77c PP |
1135 | low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; |
1136 | nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; | |
29523f09 | 1137 | guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; |
337aadff | 1138 | |
337aadff | 1139 | /* Are any of the regs PCC ?*/ |
80b8286a | 1140 | if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || |
4773e77c PP |
1141 | CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || |
1142 | CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { | |
6fa12d58 PP |
1143 | if (pcc_ss_id < 0) { |
1144 | pr_debug("Invalid pcc_ss_id\n"); | |
1145 | return -ENODEV; | |
1146 | } | |
1147 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
850d64a4 | 1148 | regs_in_pcc = 1; |
85b1407b | 1149 | down_write(&pcc_ss_data->pcc_lock); |
337aadff | 1150 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1151 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1152 | ret = -EIO; |
1153 | goto out_err; | |
1154 | } | |
1155 | } | |
1156 | ||
a6cbcdd5 | 1157 | cpc_read(cpunum, highest_reg, &high); |
337aadff AC |
1158 | perf_caps->highest_perf = high; |
1159 | ||
a6cbcdd5 | 1160 | cpc_read(cpunum, lowest_reg, &low); |
337aadff AC |
1161 | perf_caps->lowest_perf = low; |
1162 | ||
368520a6 | 1163 | cpc_read(cpunum, nominal_reg, &nom); |
337aadff AC |
1164 | perf_caps->nominal_perf = nom; |
1165 | ||
edef1ef1 SP |
1166 | if (guaranteed_reg->type != ACPI_TYPE_BUFFER || |
1167 | IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { | |
1168 | perf_caps->guaranteed_perf = 0; | |
1169 | } else { | |
1170 | cpc_read(cpunum, guaranteed_reg, &guaranteed); | |
1171 | perf_caps->guaranteed_perf = guaranteed; | |
1172 | } | |
29523f09 | 1173 | |
368520a6 PP |
1174 | cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); |
1175 | perf_caps->lowest_nonlinear_perf = min_nonlinear; | |
1176 | ||
1177 | if (!high || !low || !nom || !min_nonlinear) | |
337aadff AC |
1178 | ret = -EFAULT; |
1179 | ||
4773e77c PP |
1180 | /* Read optional lowest and nominal frequencies if present */ |
1181 | if (CPC_SUPPORTED(low_freq_reg)) | |
1182 | cpc_read(cpunum, low_freq_reg, &low_f); | |
1183 | ||
1184 | if (CPC_SUPPORTED(nom_freq_reg)) | |
1185 | cpc_read(cpunum, nom_freq_reg, &nom_f); | |
1186 | ||
1187 | perf_caps->lowest_freq = low_f; | |
1188 | perf_caps->nominal_freq = nom_f; | |
1189 | ||
1190 | ||
337aadff | 1191 | out_err: |
850d64a4 | 1192 | if (regs_in_pcc) |
85b1407b | 1193 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1194 | return ret; |
1195 | } | |
1196 | EXPORT_SYMBOL_GPL(cppc_get_perf_caps); | |
1197 | ||
1198 | /** | |
603fadf3 | 1199 | * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. |
337aadff AC |
1200 | * @cpunum: CPU from which to read counters. |
1201 | * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h | |
1202 | * | |
1203 | * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. | |
1204 | */ | |
1205 | int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) | |
1206 | { | |
1207 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
158c998e AC |
1208 | struct cpc_register_resource *delivered_reg, *reference_reg, |
1209 | *ref_perf_reg, *ctr_wrap_reg; | |
85b1407b | 1210 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1211 | struct cppc_pcc_data *pcc_ss_data = NULL; |
158c998e | 1212 | u64 delivered, reference, ref_perf, ctr_wrap_time; |
850d64a4 | 1213 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1214 | |
6fa12d58 | 1215 | if (!cpc_desc) { |
337aadff AC |
1216 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1217 | return -ENODEV; | |
1218 | } | |
1219 | ||
1220 | delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; | |
1221 | reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; | |
158c998e AC |
1222 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; |
1223 | ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; | |
1224 | ||
1225 | /* | |
603fadf3 | 1226 | * If reference perf register is not supported then we should |
158c998e AC |
1227 | * use the nominal perf value |
1228 | */ | |
1229 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1230 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
337aadff | 1231 | |
337aadff | 1232 | /* Are any of the regs PCC ?*/ |
158c998e AC |
1233 | if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || |
1234 | CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { | |
6fa12d58 PP |
1235 | if (pcc_ss_id < 0) { |
1236 | pr_debug("Invalid pcc_ss_id\n"); | |
1237 | return -ENODEV; | |
1238 | } | |
1239 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b | 1240 | down_write(&pcc_ss_data->pcc_lock); |
850d64a4 | 1241 | regs_in_pcc = 1; |
337aadff | 1242 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1243 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1244 | ret = -EIO; |
1245 | goto out_err; | |
1246 | } | |
1247 | } | |
1248 | ||
a6cbcdd5 SP |
1249 | cpc_read(cpunum, delivered_reg, &delivered); |
1250 | cpc_read(cpunum, reference_reg, &reference); | |
1251 | cpc_read(cpunum, ref_perf_reg, &ref_perf); | |
158c998e AC |
1252 | |
1253 | /* | |
1254 | * Per spec, if ctr_wrap_time optional register is unsupported, then the | |
1255 | * performance counters are assumed to never wrap during the lifetime of | |
1256 | * platform | |
1257 | */ | |
1258 | ctr_wrap_time = (u64)(~((u64)0)); | |
1259 | if (CPC_SUPPORTED(ctr_wrap_reg)) | |
a6cbcdd5 | 1260 | cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); |
337aadff | 1261 | |
158c998e | 1262 | if (!delivered || !reference || !ref_perf) { |
337aadff AC |
1263 | ret = -EFAULT; |
1264 | goto out_err; | |
1265 | } | |
1266 | ||
1267 | perf_fb_ctrs->delivered = delivered; | |
1268 | perf_fb_ctrs->reference = reference; | |
158c998e | 1269 | perf_fb_ctrs->reference_perf = ref_perf; |
2c74d847 | 1270 | perf_fb_ctrs->wraparound_time = ctr_wrap_time; |
337aadff | 1271 | out_err: |
850d64a4 | 1272 | if (regs_in_pcc) |
85b1407b | 1273 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1274 | return ret; |
1275 | } | |
1276 | EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); | |
1277 | ||
1278 | /** | |
603fadf3 | 1279 | * cppc_set_perf - Set a CPU's performance controls. |
337aadff AC |
1280 | * @cpu: CPU for which to set performance controls. |
1281 | * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h | |
1282 | * | |
1283 | * Return: 0 for success, -ERRNO otherwise. | |
1284 | */ | |
1285 | int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) | |
1286 | { | |
1287 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1288 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1289 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
6fa12d58 | 1290 | struct cppc_pcc_data *pcc_ss_data = NULL; |
337aadff AC |
1291 | int ret = 0; |
1292 | ||
6fa12d58 | 1293 | if (!cpc_desc) { |
337aadff AC |
1294 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); |
1295 | return -ENODEV; | |
1296 | } | |
1297 | ||
1298 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1299 | ||
80b8286a PP |
1300 | /* |
1301 | * This is Phase-I where we want to write to CPC registers | |
1302 | * -> We want all CPUs to be able to execute this phase in parallel | |
1303 | * | |
1304 | * Since read_lock can be acquired by multiple CPUs simultaneously we | |
1305 | * achieve that goal here | |
1306 | */ | |
1307 | if (CPC_IN_PCC(desired_reg)) { | |
6fa12d58 PP |
1308 | if (pcc_ss_id < 0) { |
1309 | pr_debug("Invalid pcc_ss_id\n"); | |
1310 | return -ENODEV; | |
1311 | } | |
1312 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1313 | down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ |
1314 | if (pcc_ss_data->platform_owns_pcc) { | |
1315 | ret = check_pcc_chan(pcc_ss_id, false); | |
80b8286a | 1316 | if (ret) { |
85b1407b | 1317 | up_read(&pcc_ss_data->pcc_lock); |
80b8286a PP |
1318 | return ret; |
1319 | } | |
80b8286a | 1320 | } |
139aee73 PP |
1321 | /* |
1322 | * Update the pending_write to make sure a PCC CMD_READ will not | |
1323 | * arrive and steal the channel during the switch to write lock | |
1324 | */ | |
85b1407b GC |
1325 | pcc_ss_data->pending_pcc_write_cmd = true; |
1326 | cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; | |
80b8286a | 1327 | cpc_desc->write_cmd_status = 0; |
ad62e1e6 AC |
1328 | } |
1329 | ||
337aadff AC |
1330 | /* |
1331 | * Skip writing MIN/MAX until Linux knows how to come up with | |
1332 | * useful values. | |
1333 | */ | |
a6cbcdd5 | 1334 | cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); |
337aadff | 1335 | |
80b8286a | 1336 | if (CPC_IN_PCC(desired_reg)) |
85b1407b | 1337 | up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ |
80b8286a PP |
1338 | /* |
1339 | * This is Phase-II where we transfer the ownership of PCC to Platform | |
1340 | * | |
1341 | * Short Summary: Basically if we think of a group of cppc_set_perf | |
1342 | * requests that happened in short overlapping interval. The last CPU to | |
1343 | * come out of Phase-I will enter Phase-II and ring the doorbell. | |
1344 | * | |
1345 | * We have the following requirements for Phase-II: | |
1346 | * 1. We want to execute Phase-II only when there are no CPUs | |
1347 | * currently executing in Phase-I | |
1348 | * 2. Once we start Phase-II we want to avoid all other CPUs from | |
1349 | * entering Phase-I. | |
1350 | * 3. We want only one CPU among all those who went through Phase-I | |
1351 | * to run phase-II | |
1352 | * | |
1353 | * If write_trylock fails to get the lock and doesn't transfer the | |
1354 | * PCC ownership to the platform, then one of the following will be TRUE | |
1355 | * 1. There is at-least one CPU in Phase-I which will later execute | |
1356 | * write_trylock, so the CPUs in Phase-I will be responsible for | |
1357 | * executing the Phase-II. | |
1358 | * 2. Some other CPU has beaten this CPU to successfully execute the | |
1359 | * write_trylock and has already acquired the write_lock. We know for a | |
603fadf3 | 1360 | * fact it (other CPU acquiring the write_lock) couldn't have happened |
80b8286a PP |
1361 | * before this CPU's Phase-I as we held the read_lock. |
1362 | * 3. Some other CPU executing pcc CMD_READ has stolen the | |
1363 | * down_write, in which case, send_pcc_cmd will check for pending | |
1364 | * CMD_WRITE commands by checking the pending_pcc_write_cmd. | |
1365 | * So this CPU can be certain that its request will be delivered | |
1366 | * So in all cases, this CPU knows that its request will be delivered | |
1367 | * by another CPU and can return | |
1368 | * | |
1369 | * After getting the down_write we still need to check for | |
1370 | * pending_pcc_write_cmd to take care of the following scenario | |
1371 | * The thread running this code could be scheduled out between | |
1372 | * Phase-I and Phase-II. Before it is scheduled back on, another CPU | |
1373 | * could have delivered the request to Platform by triggering the | |
1374 | * doorbell and transferred the ownership of PCC to platform. So this | |
1375 | * avoids triggering an unnecessary doorbell and more importantly before | |
1376 | * triggering the doorbell it makes sure that the PCC channel ownership | |
1377 | * is still with OSPM. | |
1378 | * pending_pcc_write_cmd can also be cleared by a different CPU, if | |
1379 | * there was a pcc CMD_READ waiting on down_write and it steals the lock | |
935ab850 | 1380 | * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this |
80b8286a PP |
1381 | * case during a CMD_READ and if there are pending writes it delivers |
1382 | * the write command before servicing the read command | |
1383 | */ | |
1384 | if (CPC_IN_PCC(desired_reg)) { | |
85b1407b | 1385 | if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ |
80b8286a | 1386 | /* Update only if there are pending write commands */ |
85b1407b GC |
1387 | if (pcc_ss_data->pending_pcc_write_cmd) |
1388 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
1389 | up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ | |
80b8286a PP |
1390 | } else |
1391 | /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ | |
85b1407b GC |
1392 | wait_event(pcc_ss_data->pcc_write_wait_q, |
1393 | cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); | |
80b8286a PP |
1394 | |
1395 | /* send_pcc_cmd updates the status in case of failure */ | |
1396 | ret = cpc_desc->write_cmd_status; | |
337aadff | 1397 | } |
337aadff AC |
1398 | return ret; |
1399 | } | |
1400 | EXPORT_SYMBOL_GPL(cppc_set_perf); | |
be8b88d7 PP |
1401 | |
1402 | /** | |
1403 | * cppc_get_transition_latency - returns frequency transition latency in ns | |
1404 | * | |
935ab850 TS |
1405 | * ACPI CPPC does not explicitly specify how a platform can specify the |
1406 | * transition latency for performance change requests. The closest we have | |
be8b88d7 PP |
1407 | * is the timing information from the PCCT tables which provides the info |
1408 | * on the number and frequency of PCC commands the platform can handle. | |
1409 | */ | |
1410 | unsigned int cppc_get_transition_latency(int cpu_num) | |
1411 | { | |
1412 | /* | |
1413 | * Expected transition latency is based on the PCCT timing values | |
1414 | * Below are definition from ACPI spec: | |
1415 | * pcc_nominal- Expected latency to process a command, in microseconds | |
1416 | * pcc_mpar - The maximum number of periodic requests that the subspace | |
1417 | * channel can support, reported in commands per minute. 0 | |
1418 | * indicates no limitation. | |
1419 | * pcc_mrtt - The minimum amount of time that OSPM must wait after the | |
1420 | * completion of a command before issuing the next command, | |
1421 | * in microseconds. | |
1422 | */ | |
1423 | unsigned int latency_ns = 0; | |
1424 | struct cpc_desc *cpc_desc; | |
1425 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1426 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); |
1ecbd717 | 1427 | struct cppc_pcc_data *pcc_ss_data; |
be8b88d7 PP |
1428 | |
1429 | cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); | |
1430 | if (!cpc_desc) | |
1431 | return CPUFREQ_ETERNAL; | |
1432 | ||
1433 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1434 | if (!CPC_IN_PCC(desired_reg)) | |
1435 | return CPUFREQ_ETERNAL; | |
1436 | ||
1ecbd717 GC |
1437 | if (pcc_ss_id < 0) |
1438 | return CPUFREQ_ETERNAL; | |
1439 | ||
1440 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1441 | if (pcc_ss_data->pcc_mpar) |
1442 | latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); | |
be8b88d7 | 1443 | |
85b1407b GC |
1444 | latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); |
1445 | latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); | |
be8b88d7 PP |
1446 | |
1447 | return latency_ns; | |
1448 | } | |
1449 | EXPORT_SYMBOL_GPL(cppc_get_transition_latency); |