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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
337aadff AC |
2 | /* |
3 | * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. | |
4 | * | |
5 | * (C) Copyright 2014, 2015 Linaro Ltd. | |
6 | * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> | |
7 | * | |
337aadff AC |
8 | * CPPC describes a few methods for controlling CPU performance using |
9 | * information from a per CPU table called CPC. This table is described in | |
10 | * the ACPI v5.0+ specification. The table consists of a list of | |
11 | * registers which may be memory mapped or hardware registers and also may | |
12 | * include some static integer values. | |
13 | * | |
14 | * CPU performance is on an abstract continuous scale as against a discretized | |
15 | * P-state scale which is tied to CPU frequency only. In brief, the basic | |
16 | * operation involves: | |
17 | * | |
18 | * - OS makes a CPU performance request. (Can provide min and max bounds) | |
19 | * | |
20 | * - Platform (such as BMC) is free to optimize request within requested bounds | |
21 | * depending on power/thermal budgets etc. | |
22 | * | |
23 | * - Platform conveys its decision back to OS | |
24 | * | |
25 | * The communication between OS and platform occurs through another medium | |
26 | * called (PCC) Platform Communication Channel. This is a generic mailbox like | |
27 | * mechanism which includes doorbell semantics to indicate register updates. | |
28 | * See drivers/mailbox/pcc.c for details on PCC. | |
29 | * | |
30 | * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and | |
31 | * above specifications. | |
32 | */ | |
33 | ||
34 | #define pr_fmt(fmt) "ACPI CPPC: " fmt | |
35 | ||
337aadff | 36 | #include <linux/delay.h> |
58e1c035 | 37 | #include <linux/iopoll.h> |
ad62e1e6 | 38 | #include <linux/ktime.h> |
80b8286a PP |
39 | #include <linux/rwsem.h> |
40 | #include <linux/wait.h> | |
41ea6672 | 41 | #include <linux/topology.h> |
337aadff AC |
42 | |
43 | #include <acpi/cppc_acpi.h> | |
80b8286a | 44 | |
8482ef8c | 45 | struct cppc_pcc_data { |
7b6da7fe | 46 | struct pcc_mbox_chan *pcc_channel; |
8482ef8c | 47 | void __iomem *pcc_comm_addr; |
8482ef8c | 48 | bool pcc_channel_acquired; |
58e1c035 | 49 | unsigned int deadline_us; |
8482ef8c | 50 | unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; |
80b8286a | 51 | |
8482ef8c | 52 | bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ |
139aee73 | 53 | bool platform_owns_pcc; /* Ownership of PCC subspace */ |
8482ef8c | 54 | unsigned int pcc_write_cnt; /* Running count of PCC write commands */ |
80b8286a | 55 | |
8482ef8c PP |
56 | /* |
57 | * Lock to provide controlled access to the PCC channel. | |
58 | * | |
59 | * For performance critical usecases(currently cppc_set_perf) | |
60 | * We need to take read_lock and check if channel belongs to OSPM | |
61 | * before reading or writing to PCC subspace | |
62 | * We need to take write_lock before transferring the channel | |
63 | * ownership to the platform via a Doorbell | |
64 | * This allows us to batch a number of CPPC requests if they happen | |
65 | * to originate in about the same time | |
66 | * | |
67 | * For non-performance critical usecases(init) | |
68 | * Take write_lock for all purposes which gives exclusive access | |
69 | */ | |
70 | struct rw_semaphore pcc_lock; | |
71 | ||
72 | /* Wait queue for CPUs whose requests were batched */ | |
73 | wait_queue_head_t pcc_write_wait_q; | |
85b1407b GC |
74 | ktime_t last_cmd_cmpl_time; |
75 | ktime_t last_mpar_reset; | |
76 | int mpar_count; | |
77 | int refcount; | |
8482ef8c | 78 | }; |
80b8286a | 79 | |
603fadf3 | 80 | /* Array to represent the PCC channel per subspace ID */ |
85b1407b | 81 | static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; |
603fadf3 | 82 | /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ |
85b1407b | 83 | static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); |
337aadff AC |
84 | |
85 | /* | |
86 | * The cpc_desc structure contains the ACPI register details | |
87 | * as described in the per CPU _CPC tables. The details | |
88 | * include the type of register (e.g. PCC, System IO, FFH etc.) | |
89 | * and destination addresses which lets us READ/WRITE CPU performance | |
90 | * information using the appropriate I/O methods. | |
91 | */ | |
92 | static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); | |
93 | ||
77e3d86f | 94 | /* pcc mapped address + header size + offset within PCC subspace */ |
85b1407b GC |
95 | #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ |
96 | 0x8 + (offs)) | |
77e3d86f | 97 | |
ad61dd30 | 98 | /* Check if a CPC register is in PCC */ |
80b8286a PP |
99 | #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ |
100 | (cpc)->cpc_entry.reg.space_id == \ | |
101 | ACPI_ADR_SPACE_PLATFORM_COMM) | |
102 | ||
6380b7b2 PG |
103 | /* Check if a CPC register is in SystemMemory */ |
104 | #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ | |
105 | (cpc)->cpc_entry.reg.space_id == \ | |
106 | ACPI_ADR_SPACE_SYSTEM_MEMORY) | |
107 | ||
108 | /* Check if a CPC register is in SystemIo */ | |
109 | #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ | |
110 | (cpc)->cpc_entry.reg.space_id == \ | |
111 | ACPI_ADR_SPACE_SYSTEM_IO) | |
112 | ||
935ab850 | 113 | /* Evaluates to True if reg is a NULL register descriptor */ |
158c998e AC |
114 | #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ |
115 | (reg)->address == 0 && \ | |
116 | (reg)->bit_width == 0 && \ | |
117 | (reg)->bit_offset == 0 && \ | |
118 | (reg)->access_width == 0) | |
119 | ||
935ab850 | 120 | /* Evaluates to True if an optional cpc field is supported */ |
158c998e AC |
121 | #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ |
122 | !!(cpc)->cpc_entry.int_value : \ | |
123 | !IS_NULL_REG(&(cpc)->cpc_entry.reg)) | |
337aadff AC |
124 | /* |
125 | * Arbitrary Retries in case the remote processor is slow to respond | |
ad62e1e6 AC |
126 | * to PCC commands. Keeping it high enough to cover emulators where |
127 | * the processors run painfully slow. | |
337aadff | 128 | */ |
b52f4511 | 129 | #define NUM_RETRIES 500ULL |
337aadff | 130 | |
a2c8f92b SN |
131 | #define OVER_16BTS_MASK ~0xFFFFULL |
132 | ||
158c998e | 133 | #define define_one_cppc_ro(_name) \ |
2bc6262c | 134 | static struct kobj_attribute _name = \ |
158c998e AC |
135 | __ATTR(_name, 0444, show_##_name, NULL) |
136 | ||
137 | #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) | |
138 | ||
2c74d847 PP |
139 | #define show_cppc_data(access_fn, struct_name, member_name) \ |
140 | static ssize_t show_##member_name(struct kobject *kobj, \ | |
2bc6262c | 141 | struct kobj_attribute *attr, char *buf) \ |
2c74d847 PP |
142 | { \ |
143 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ | |
144 | struct struct_name st_name = {0}; \ | |
145 | int ret; \ | |
146 | \ | |
147 | ret = access_fn(cpc_ptr->cpu_id, &st_name); \ | |
148 | if (ret) \ | |
149 | return ret; \ | |
150 | \ | |
151 | return scnprintf(buf, PAGE_SIZE, "%llu\n", \ | |
152 | (u64)st_name.member_name); \ | |
153 | } \ | |
154 | define_one_cppc_ro(member_name) | |
155 | ||
156 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); | |
157 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); | |
158 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); | |
159 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); | |
4773e77c PP |
160 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); |
161 | show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); | |
162 | ||
2c74d847 PP |
163 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); |
164 | show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); | |
165 | ||
158c998e | 166 | static ssize_t show_feedback_ctrs(struct kobject *kobj, |
2bc6262c | 167 | struct kobj_attribute *attr, char *buf) |
158c998e AC |
168 | { |
169 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
170 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
2c74d847 | 171 | int ret; |
158c998e | 172 | |
2c74d847 PP |
173 | ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); |
174 | if (ret) | |
175 | return ret; | |
158c998e AC |
176 | |
177 | return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", | |
178 | fb_ctrs.reference, fb_ctrs.delivered); | |
179 | } | |
180 | define_one_cppc_ro(feedback_ctrs); | |
181 | ||
158c998e AC |
182 | static struct attribute *cppc_attrs[] = { |
183 | &feedback_ctrs.attr, | |
184 | &reference_perf.attr, | |
185 | &wraparound_time.attr, | |
2c74d847 PP |
186 | &highest_perf.attr, |
187 | &lowest_perf.attr, | |
188 | &lowest_nonlinear_perf.attr, | |
189 | &nominal_perf.attr, | |
4773e77c PP |
190 | &nominal_freq.attr, |
191 | &lowest_freq.attr, | |
158c998e AC |
192 | NULL |
193 | }; | |
17f18417 | 194 | ATTRIBUTE_GROUPS(cppc); |
158c998e AC |
195 | |
196 | static struct kobj_type cppc_ktype = { | |
197 | .sysfs_ops = &kobj_sysfs_ops, | |
17f18417 | 198 | .default_groups = cppc_groups, |
158c998e AC |
199 | }; |
200 | ||
85b1407b | 201 | static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) |
ad62e1e6 | 202 | { |
58e1c035 | 203 | int ret, status; |
85b1407b GC |
204 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
205 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = | |
206 | pcc_ss_data->pcc_comm_addr; | |
ad62e1e6 | 207 | |
85b1407b | 208 | if (!pcc_ss_data->platform_owns_pcc) |
139aee73 PP |
209 | return 0; |
210 | ||
58e1c035 PP |
211 | /* |
212 | * Poll PCC status register every 3us(delay_us) for maximum of | |
213 | * deadline_us(timeout_us) until PCC command complete bit is set(cond) | |
214 | */ | |
215 | ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, | |
216 | status & PCC_CMD_COMPLETE_MASK, 3, | |
217 | pcc_ss_data->deadline_us); | |
ad62e1e6 | 218 | |
58e1c035 | 219 | if (likely(!ret)) { |
85b1407b | 220 | pcc_ss_data->platform_owns_pcc = false; |
58e1c035 PP |
221 | if (chk_err_bit && (status & PCC_ERROR_MASK)) |
222 | ret = -EIO; | |
223 | } | |
224 | ||
225 | if (unlikely(ret)) | |
226 | pr_err("PCC check channel failed for ss: %d. ret=%d\n", | |
227 | pcc_ss_id, ret); | |
139aee73 | 228 | |
ad62e1e6 AC |
229 | return ret; |
230 | } | |
231 | ||
80b8286a PP |
232 | /* |
233 | * This function transfers the ownership of the PCC to the platform | |
234 | * So it must be called while holding write_lock(pcc_lock) | |
235 | */ | |
85b1407b | 236 | static int send_pcc_cmd(int pcc_ss_id, u16 cmd) |
337aadff | 237 | { |
80b8286a | 238 | int ret = -EIO, i; |
85b1407b | 239 | struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; |
1d9b4abe IV |
240 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = |
241 | pcc_ss_data->pcc_comm_addr; | |
f387e5b9 | 242 | unsigned int time_delta; |
337aadff | 243 | |
ad62e1e6 AC |
244 | /* |
245 | * For CMD_WRITE we know for a fact the caller should have checked | |
246 | * the channel before writing to PCC space | |
247 | */ | |
248 | if (cmd == CMD_READ) { | |
80b8286a PP |
249 | /* |
250 | * If there are pending cpc_writes, then we stole the channel | |
251 | * before write completion, so first send a WRITE command to | |
252 | * platform | |
253 | */ | |
85b1407b GC |
254 | if (pcc_ss_data->pending_pcc_write_cmd) |
255 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
80b8286a | 256 | |
85b1407b | 257 | ret = check_pcc_chan(pcc_ss_id, false); |
ad62e1e6 | 258 | if (ret) |
80b8286a PP |
259 | goto end; |
260 | } else /* CMD_WRITE */ | |
85b1407b | 261 | pcc_ss_data->pending_pcc_write_cmd = FALSE; |
337aadff | 262 | |
f387e5b9 PP |
263 | /* |
264 | * Handle the Minimum Request Turnaround Time(MRTT) | |
265 | * "The minimum amount of time that OSPM must wait after the completion | |
266 | * of a command before issuing the next command, in microseconds" | |
267 | */ | |
85b1407b GC |
268 | if (pcc_ss_data->pcc_mrtt) { |
269 | time_delta = ktime_us_delta(ktime_get(), | |
270 | pcc_ss_data->last_cmd_cmpl_time); | |
271 | if (pcc_ss_data->pcc_mrtt > time_delta) | |
272 | udelay(pcc_ss_data->pcc_mrtt - time_delta); | |
f387e5b9 PP |
273 | } |
274 | ||
275 | /* | |
276 | * Handle the non-zero Maximum Periodic Access Rate(MPAR) | |
277 | * "The maximum number of periodic requests that the subspace channel can | |
278 | * support, reported in commands per minute. 0 indicates no limitation." | |
279 | * | |
280 | * This parameter should be ideally zero or large enough so that it can | |
281 | * handle maximum number of requests that all the cores in the system can | |
282 | * collectively generate. If it is not, we will follow the spec and just | |
283 | * not send the request to the platform after hitting the MPAR limit in | |
284 | * any 60s window | |
285 | */ | |
85b1407b GC |
286 | if (pcc_ss_data->pcc_mpar) { |
287 | if (pcc_ss_data->mpar_count == 0) { | |
288 | time_delta = ktime_ms_delta(ktime_get(), | |
289 | pcc_ss_data->last_mpar_reset); | |
290 | if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { | |
d29abc83 GC |
291 | pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", |
292 | pcc_ss_id); | |
80b8286a PP |
293 | ret = -EIO; |
294 | goto end; | |
f387e5b9 | 295 | } |
85b1407b GC |
296 | pcc_ss_data->last_mpar_reset = ktime_get(); |
297 | pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; | |
f387e5b9 | 298 | } |
85b1407b | 299 | pcc_ss_data->mpar_count--; |
f387e5b9 PP |
300 | } |
301 | ||
337aadff | 302 | /* Write to the shared comm region. */ |
beee23ae | 303 | writew_relaxed(cmd, &generic_comm_base->command); |
337aadff AC |
304 | |
305 | /* Flip CMD COMPLETE bit */ | |
beee23ae | 306 | writew_relaxed(0, &generic_comm_base->status); |
337aadff | 307 | |
85b1407b | 308 | pcc_ss_data->platform_owns_pcc = true; |
139aee73 | 309 | |
337aadff | 310 | /* Ring doorbell */ |
7b6da7fe | 311 | ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd); |
ad62e1e6 | 312 | if (ret < 0) { |
d29abc83 GC |
313 | pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", |
314 | pcc_ss_id, cmd, ret); | |
80b8286a | 315 | goto end; |
337aadff AC |
316 | } |
317 | ||
9e12eb82 | 318 | /* wait for completion and check for PCC error bit */ |
85b1407b | 319 | ret = check_pcc_chan(pcc_ss_id, true); |
139aee73 | 320 | |
85b1407b GC |
321 | if (pcc_ss_data->pcc_mrtt) |
322 | pcc_ss_data->last_cmd_cmpl_time = ktime_get(); | |
337aadff | 323 | |
7b6da7fe SH |
324 | if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq) |
325 | mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret); | |
b59c4b3d | 326 | else |
7b6da7fe | 327 | mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret); |
80b8286a PP |
328 | |
329 | end: | |
330 | if (cmd == CMD_WRITE) { | |
331 | if (unlikely(ret)) { | |
332 | for_each_possible_cpu(i) { | |
333 | struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); | |
e69ae675 | 334 | |
80b8286a PP |
335 | if (!desc) |
336 | continue; | |
337 | ||
85b1407b | 338 | if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) |
80b8286a PP |
339 | desc->write_cmd_status = ret; |
340 | } | |
341 | } | |
85b1407b GC |
342 | pcc_ss_data->pcc_write_cnt++; |
343 | wake_up_all(&pcc_ss_data->pcc_write_wait_q); | |
80b8286a PP |
344 | } |
345 | ||
ad62e1e6 | 346 | return ret; |
337aadff AC |
347 | } |
348 | ||
349 | static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) | |
350 | { | |
ad62e1e6 | 351 | if (ret < 0) |
337aadff AC |
352 | pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", |
353 | *(u16 *)msg, ret); | |
354 | else | |
355 | pr_debug("TX completed. CMD sent:%x, ret:%d\n", | |
356 | *(u16 *)msg, ret); | |
357 | } | |
358 | ||
5c447c18 | 359 | static struct mbox_client cppc_mbox_cl = { |
337aadff AC |
360 | .tx_done = cppc_chan_tx_done, |
361 | .knows_txdone = true, | |
362 | }; | |
363 | ||
364 | static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) | |
365 | { | |
366 | int result = -EFAULT; | |
367 | acpi_status status = AE_OK; | |
368 | struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; | |
369 | struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; | |
370 | struct acpi_buffer state = {0, NULL}; | |
371 | union acpi_object *psd = NULL; | |
372 | struct acpi_psd_package *pdomain; | |
373 | ||
4c4cdc4c AS |
374 | status = acpi_evaluate_object_typed(handle, "_PSD", NULL, |
375 | &buffer, ACPI_TYPE_PACKAGE); | |
376 | if (status == AE_NOT_FOUND) /* _PSD is optional */ | |
377 | return 0; | |
337aadff AC |
378 | if (ACPI_FAILURE(status)) |
379 | return -ENODEV; | |
380 | ||
381 | psd = buffer.pointer; | |
382 | if (!psd || psd->package.count != 1) { | |
383 | pr_debug("Invalid _PSD data\n"); | |
384 | goto end; | |
385 | } | |
386 | ||
387 | pdomain = &(cpc_ptr->domain_info); | |
388 | ||
389 | state.length = sizeof(struct acpi_psd_package); | |
390 | state.pointer = pdomain; | |
391 | ||
392 | status = acpi_extract_package(&(psd->package.elements[0]), | |
393 | &format, &state); | |
394 | if (ACPI_FAILURE(status)) { | |
395 | pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); | |
396 | goto end; | |
397 | } | |
398 | ||
399 | if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { | |
400 | pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); | |
401 | goto end; | |
402 | } | |
403 | ||
404 | if (pdomain->revision != ACPI_PSD_REV0_REVISION) { | |
405 | pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); | |
406 | goto end; | |
407 | } | |
408 | ||
409 | if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && | |
410 | pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && | |
411 | pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { | |
412 | pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); | |
413 | goto end; | |
414 | } | |
415 | ||
416 | result = 0; | |
417 | end: | |
418 | kfree(buffer.pointer); | |
419 | return result; | |
420 | } | |
421 | ||
a28b2bfc IV |
422 | bool acpi_cpc_valid(void) |
423 | { | |
424 | struct cpc_desc *cpc_ptr; | |
425 | int cpu; | |
426 | ||
a2a9d185 PY |
427 | if (acpi_disabled) |
428 | return false; | |
429 | ||
2aeca6bd | 430 | for_each_present_cpu(cpu) { |
a28b2bfc IV |
431 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); |
432 | if (!cpc_ptr) | |
433 | return false; | |
434 | } | |
435 | ||
436 | return true; | |
437 | } | |
438 | EXPORT_SYMBOL_GPL(acpi_cpc_valid); | |
439 | ||
3cc30dd0 PG |
440 | bool cppc_allow_fast_switch(void) |
441 | { | |
442 | struct cpc_register_resource *desired_reg; | |
443 | struct cpc_desc *cpc_ptr; | |
444 | int cpu; | |
445 | ||
446 | for_each_possible_cpu(cpu) { | |
447 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); | |
448 | desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF]; | |
449 | if (!CPC_IN_SYSTEM_MEMORY(desired_reg) && | |
450 | !CPC_IN_SYSTEM_IO(desired_reg)) | |
451 | return false; | |
452 | } | |
453 | ||
454 | return true; | |
455 | } | |
456 | EXPORT_SYMBOL_GPL(cppc_allow_fast_switch); | |
457 | ||
337aadff | 458 | /** |
a28b2bfc IV |
459 | * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu |
460 | * @cpu: Find all CPUs that share a domain with cpu. | |
461 | * @cpu_data: Pointer to CPU specific CPPC data including PSD info. | |
337aadff AC |
462 | * |
463 | * Return: 0 for success or negative value for err. | |
464 | */ | |
a28b2bfc | 465 | int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) |
337aadff | 466 | { |
337aadff | 467 | struct cpc_desc *cpc_ptr, *match_cpc_ptr; |
a28b2bfc IV |
468 | struct acpi_psd_package *match_pdomain; |
469 | struct acpi_psd_package *pdomain; | |
470 | int count_target, i; | |
337aadff AC |
471 | |
472 | /* | |
603fadf3 | 473 | * Now that we have _PSD data from all CPUs, let's setup P-state |
337aadff AC |
474 | * domain info. |
475 | */ | |
a28b2bfc IV |
476 | cpc_ptr = per_cpu(cpc_desc_ptr, cpu); |
477 | if (!cpc_ptr) | |
478 | return -EFAULT; | |
337aadff | 479 | |
a28b2bfc IV |
480 | pdomain = &(cpc_ptr->domain_info); |
481 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
482 | if (pdomain->num_processors <= 1) | |
483 | return 0; | |
337aadff | 484 | |
a28b2bfc IV |
485 | /* Validate the Domain info */ |
486 | count_target = pdomain->num_processors; | |
487 | if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) | |
488 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
489 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) | |
490 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW; | |
491 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) | |
492 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
337aadff | 493 | |
a28b2bfc IV |
494 | for_each_possible_cpu(i) { |
495 | if (i == cpu) | |
496 | continue; | |
337aadff | 497 | |
a28b2bfc IV |
498 | match_cpc_ptr = per_cpu(cpc_desc_ptr, i); |
499 | if (!match_cpc_ptr) | |
500 | goto err_fault; | |
337aadff | 501 | |
a28b2bfc IV |
502 | match_pdomain = &(match_cpc_ptr->domain_info); |
503 | if (match_pdomain->domain != pdomain->domain) | |
504 | continue; | |
337aadff | 505 | |
a28b2bfc IV |
506 | /* Here i and cpu are in the same domain */ |
507 | if (match_pdomain->num_processors != count_target) | |
508 | goto err_fault; | |
337aadff | 509 | |
a28b2bfc IV |
510 | if (pdomain->coord_type != match_pdomain->coord_type) |
511 | goto err_fault; | |
337aadff | 512 | |
a28b2bfc | 513 | cpumask_set_cpu(i, cpu_data->shared_cpu_map); |
337aadff AC |
514 | } |
515 | ||
a28b2bfc | 516 | return 0; |
337aadff | 517 | |
a28b2bfc IV |
518 | err_fault: |
519 | /* Assume no coordination on any error parsing domain info */ | |
520 | cpumask_clear(cpu_data->shared_cpu_map); | |
521 | cpumask_set_cpu(cpu, cpu_data->shared_cpu_map); | |
522 | cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE; | |
523 | ||
524 | return -EFAULT; | |
337aadff AC |
525 | } |
526 | EXPORT_SYMBOL_GPL(acpi_get_psd_map); | |
527 | ||
85b1407b | 528 | static int register_pcc_channel(int pcc_ss_idx) |
337aadff | 529 | { |
7b6da7fe | 530 | struct pcc_mbox_chan *pcc_chan; |
ad62e1e6 | 531 | u64 usecs_lat; |
337aadff | 532 | |
85b1407b | 533 | if (pcc_ss_idx >= 0) { |
7b6da7fe | 534 | pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); |
337aadff | 535 | |
7b6da7fe | 536 | if (IS_ERR(pcc_chan)) { |
d29abc83 GC |
537 | pr_err("Failed to find PCC channel for subspace %d\n", |
538 | pcc_ss_idx); | |
337aadff AC |
539 | return -ENODEV; |
540 | } | |
541 | ||
7b6da7fe | 542 | pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan; |
ad62e1e6 AC |
543 | /* |
544 | * cppc_ss->latency is just a Nominal value. In reality | |
545 | * the remote processor could be much slower to reply. | |
546 | * So add an arbitrary amount of wait on top of Nominal. | |
547 | */ | |
7b6da7fe | 548 | usecs_lat = NUM_RETRIES * pcc_chan->latency; |
58e1c035 | 549 | pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; |
7b6da7fe SH |
550 | pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time; |
551 | pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate; | |
552 | pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency; | |
85b1407b GC |
553 | |
554 | pcc_data[pcc_ss_idx]->pcc_comm_addr = | |
7b6da7fe SH |
555 | acpi_os_ioremap(pcc_chan->shmem_base_addr, |
556 | pcc_chan->shmem_size); | |
85b1407b | 557 | if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { |
d29abc83 GC |
558 | pr_err("Failed to ioremap PCC comm region mem for %d\n", |
559 | pcc_ss_idx); | |
337aadff AC |
560 | return -ENOMEM; |
561 | } | |
562 | ||
603fadf3 | 563 | /* Set flag so that we don't come here for each CPU. */ |
85b1407b | 564 | pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; |
337aadff AC |
565 | } |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
a6cbcdd5 SP |
570 | /** |
571 | * cpc_ffh_supported() - check if FFH reading supported | |
572 | * | |
573 | * Check if the architecture has support for functional fixed hardware | |
574 | * read/write capability. | |
575 | * | |
576 | * Return: true for supported, false for not supported | |
577 | */ | |
578 | bool __weak cpc_ffh_supported(void) | |
579 | { | |
580 | return false; | |
581 | } | |
582 | ||
8b356e53 ML |
583 | /** |
584 | * cpc_supported_by_cpu() - check if CPPC is supported by CPU | |
585 | * | |
586 | * Check if the architectural support for CPPC is present even | |
587 | * if the _OSC hasn't prescribed it | |
588 | * | |
589 | * Return: true for supported, false for not supported | |
590 | */ | |
591 | bool __weak cpc_supported_by_cpu(void) | |
592 | { | |
593 | return false; | |
594 | } | |
595 | ||
85b1407b GC |
596 | /** |
597 | * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace | |
598 | * | |
599 | * Check and allocate the cppc_pcc_data memory. | |
600 | * In some processor configurations it is possible that same subspace | |
603fadf3 | 601 | * is shared between multiple CPUs. This is seen especially in CPUs |
85b1407b GC |
602 | * with hardware multi-threading support. |
603 | * | |
604 | * Return: 0 for success, errno for failure | |
605 | */ | |
5c447c18 | 606 | static int pcc_data_alloc(int pcc_ss_id) |
85b1407b GC |
607 | { |
608 | if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) | |
609 | return -EINVAL; | |
610 | ||
611 | if (pcc_data[pcc_ss_id]) { | |
612 | pcc_data[pcc_ss_id]->refcount++; | |
613 | } else { | |
614 | pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), | |
615 | GFP_KERNEL); | |
616 | if (!pcc_data[pcc_ss_id]) | |
617 | return -ENOMEM; | |
618 | pcc_data[pcc_ss_id]->refcount++; | |
619 | } | |
620 | ||
621 | return 0; | |
622 | } | |
4773e77c | 623 | |
337aadff AC |
624 | /* |
625 | * An example CPC table looks like the following. | |
626 | * | |
1a901c91 AS |
627 | * Name (_CPC, Package() { |
628 | * 17, // NumEntries | |
629 | * 1, // Revision | |
630 | * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance | |
631 | * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance | |
632 | * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance | |
633 | * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance | |
634 | * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register | |
635 | * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register | |
636 | * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, | |
637 | * ... | |
638 | * ... | |
639 | * ... | |
640 | * } | |
337aadff AC |
641 | * Each Register() encodes how to access that specific register. |
642 | * e.g. a sample PCC entry has the following encoding: | |
643 | * | |
1a901c91 AS |
644 | * Register ( |
645 | * PCC, // AddressSpaceKeyword | |
646 | * 8, // RegisterBitWidth | |
647 | * 8, // RegisterBitOffset | |
648 | * 0x30, // RegisterAddress | |
649 | * 9, // AccessSize (subspace ID) | |
650 | * ) | |
337aadff AC |
651 | */ |
652 | ||
1132e6de IV |
653 | #ifndef arch_init_invariance_cppc |
654 | static inline void arch_init_invariance_cppc(void) { } | |
41ea6672 NF |
655 | #endif |
656 | ||
337aadff AC |
657 | /** |
658 | * acpi_cppc_processor_probe - Search for per CPU _CPC objects. | |
603fadf3 | 659 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
660 | * |
661 | * Return: 0 for success or negative value for err. | |
662 | */ | |
663 | int acpi_cppc_processor_probe(struct acpi_processor *pr) | |
664 | { | |
665 | struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; | |
666 | union acpi_object *out_obj, *cpc_obj; | |
667 | struct cpc_desc *cpc_ptr; | |
668 | struct cpc_reg *gas_t; | |
158c998e | 669 | struct device *cpu_dev; |
337aadff AC |
670 | acpi_handle handle = pr->handle; |
671 | unsigned int num_ent, i, cpc_rev; | |
85b1407b | 672 | int pcc_subspace_id = -1; |
337aadff | 673 | acpi_status status; |
f21a3509 | 674 | int ret = -ENODATA; |
337aadff | 675 | |
7feec743 ML |
676 | if (!osc_sb_cppc2_support_acked) { |
677 | pr_debug("CPPC v2 _OSC not acked\n"); | |
8b356e53 ML |
678 | if (!cpc_supported_by_cpu()) |
679 | return -ENODEV; | |
7feec743 | 680 | } |
c42fa24b | 681 | |
603fadf3 | 682 | /* Parse the ACPI _CPC table for this CPU. */ |
337aadff AC |
683 | status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, |
684 | ACPI_TYPE_PACKAGE); | |
685 | if (ACPI_FAILURE(status)) { | |
686 | ret = -ENODEV; | |
687 | goto out_buf_free; | |
688 | } | |
689 | ||
690 | out_obj = (union acpi_object *) output.pointer; | |
691 | ||
692 | cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); | |
693 | if (!cpc_ptr) { | |
694 | ret = -ENOMEM; | |
695 | goto out_buf_free; | |
696 | } | |
697 | ||
698 | /* First entry is NumEntries. */ | |
699 | cpc_obj = &out_obj->package.elements[0]; | |
700 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
701 | num_ent = cpc_obj->integer.value; | |
40d8abf3 RW |
702 | if (num_ent <= 1) { |
703 | pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n", | |
704 | num_ent, pr->id); | |
705 | goto out_free; | |
706 | } | |
337aadff | 707 | } else { |
f21a3509 RW |
708 | pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n", |
709 | cpc_obj->type, pr->id); | |
337aadff AC |
710 | goto out_free; |
711 | } | |
5bbb86aa | 712 | |
337aadff AC |
713 | /* Second entry should be revision. */ |
714 | cpc_obj = &out_obj->package.elements[1]; | |
715 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
716 | cpc_rev = cpc_obj->integer.value; | |
717 | } else { | |
f21a3509 RW |
718 | pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n", |
719 | cpc_obj->type, pr->id); | |
337aadff AC |
720 | goto out_free; |
721 | } | |
722 | ||
4f4179fc RW |
723 | if (cpc_rev < CPPC_V2_REV) { |
724 | pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev, | |
725 | pr->id); | |
337aadff | 726 | goto out_free; |
4f4179fc RW |
727 | } |
728 | ||
729 | /* | |
730 | * Disregard _CPC if the number of entries in the return pachage is not | |
731 | * as expected, but support future revisions being proper supersets of | |
732 | * the v3 and only causing more entries to be returned by _CPC. | |
733 | */ | |
734 | if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) || | |
735 | (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) || | |
736 | (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) { | |
737 | pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n", | |
738 | num_ent, pr->id); | |
739 | goto out_free; | |
740 | } | |
741 | if (cpc_rev > CPPC_V3_REV) { | |
742 | num_ent = CPPC_V3_NUM_ENT; | |
743 | cpc_rev = CPPC_V3_REV; | |
744 | } | |
745 | ||
746 | cpc_ptr->num_entries = num_ent; | |
747 | cpc_ptr->version = cpc_rev; | |
337aadff AC |
748 | |
749 | /* Iterate through remaining entries in _CPC */ | |
750 | for (i = 2; i < num_ent; i++) { | |
751 | cpc_obj = &out_obj->package.elements[i]; | |
752 | ||
753 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
754 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; | |
755 | cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; | |
756 | } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { | |
757 | gas_t = (struct cpc_reg *) | |
758 | cpc_obj->buffer.pointer; | |
759 | ||
760 | /* | |
761 | * The PCC Subspace index is encoded inside | |
762 | * the CPC table entries. The same PCC index | |
763 | * will be used for all the PCC entries, | |
764 | * so extract it only once. | |
765 | */ | |
766 | if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { | |
85b1407b GC |
767 | if (pcc_subspace_id < 0) { |
768 | pcc_subspace_id = gas_t->access_width; | |
769 | if (pcc_data_alloc(pcc_subspace_id)) | |
770 | goto out_free; | |
771 | } else if (pcc_subspace_id != gas_t->access_width) { | |
f21a3509 RW |
772 | pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n", |
773 | pr->id); | |
337aadff AC |
774 | goto out_free; |
775 | } | |
5bbb86aa AC |
776 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
777 | if (gas_t->address) { | |
778 | void __iomem *addr; | |
779 | ||
0651ab90 PG |
780 | if (!osc_cpc_flexible_adr_space_confirmed) { |
781 | pr_debug("Flexible address space capability not supported\n"); | |
09073396 ML |
782 | if (!cpc_supported_by_cpu()) |
783 | goto out_free; | |
0651ab90 PG |
784 | } |
785 | ||
5bbb86aa AC |
786 | addr = ioremap(gas_t->address, gas_t->bit_width/8); |
787 | if (!addr) | |
788 | goto out_free; | |
789 | cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; | |
790 | } | |
a2c8f92b SN |
791 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { |
792 | if (gas_t->access_width < 1 || gas_t->access_width > 3) { | |
793 | /* | |
794 | * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. | |
795 | * SystemIO doesn't implement 64-bit | |
796 | * registers. | |
797 | */ | |
f21a3509 RW |
798 | pr_debug("Invalid access width %d for SystemIO register in _CPC\n", |
799 | gas_t->access_width); | |
a2c8f92b SN |
800 | goto out_free; |
801 | } | |
802 | if (gas_t->address & OVER_16BTS_MASK) { | |
803 | /* SystemIO registers use 16-bit integer addresses */ | |
f21a3509 RW |
804 | pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n", |
805 | gas_t->address); | |
a2c8f92b SN |
806 | goto out_free; |
807 | } | |
0651ab90 PG |
808 | if (!osc_cpc_flexible_adr_space_confirmed) { |
809 | pr_debug("Flexible address space capability not supported\n"); | |
09073396 ML |
810 | if (!cpc_supported_by_cpu()) |
811 | goto out_free; | |
0651ab90 | 812 | } |
5bbb86aa | 813 | } else { |
a6cbcdd5 | 814 | if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { |
a2c8f92b | 815 | /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */ |
f21a3509 RW |
816 | pr_debug("Unsupported register type (%d) in _CPC\n", |
817 | gas_t->space_id); | |
a6cbcdd5 SP |
818 | goto out_free; |
819 | } | |
337aadff AC |
820 | } |
821 | ||
822 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; | |
823 | memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); | |
824 | } else { | |
f21a3509 RW |
825 | pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n", |
826 | i, pr->id); | |
337aadff AC |
827 | goto out_free; |
828 | } | |
829 | } | |
85b1407b | 830 | per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; |
4773e77c PP |
831 | |
832 | /* | |
833 | * Initialize the remaining cpc_regs as unsupported. | |
834 | * Example: In case FW exposes CPPC v2, the below loop will initialize | |
835 | * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported | |
836 | */ | |
837 | for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { | |
838 | cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; | |
839 | cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; | |
840 | } | |
841 | ||
842 | ||
337aadff AC |
843 | /* Store CPU Logical ID */ |
844 | cpc_ptr->cpu_id = pr->id; | |
845 | ||
337aadff AC |
846 | /* Parse PSD data for this CPU */ |
847 | ret = acpi_get_psd(cpc_ptr, handle); | |
848 | if (ret) | |
849 | goto out_free; | |
850 | ||
603fadf3 | 851 | /* Register PCC channel once for all PCC subspace ID. */ |
85b1407b GC |
852 | if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { |
853 | ret = register_pcc_channel(pcc_subspace_id); | |
337aadff AC |
854 | if (ret) |
855 | goto out_free; | |
8482ef8c | 856 | |
85b1407b GC |
857 | init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); |
858 | init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); | |
337aadff AC |
859 | } |
860 | ||
861 | /* Everything looks okay */ | |
862 | pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); | |
863 | ||
158c998e AC |
864 | /* Add per logical CPU nodes for reading its feedback counters. */ |
865 | cpu_dev = get_cpu_device(pr->id); | |
50163475 DC |
866 | if (!cpu_dev) { |
867 | ret = -EINVAL; | |
158c998e | 868 | goto out_free; |
50163475 | 869 | } |
158c998e | 870 | |
603fadf3 | 871 | /* Plug PSD data into this CPU's CPC descriptor. */ |
28076483 RW |
872 | per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; |
873 | ||
158c998e AC |
874 | ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, |
875 | "acpi_cppc"); | |
28076483 RW |
876 | if (ret) { |
877 | per_cpu(cpc_desc_ptr, pr->id) = NULL; | |
4d8be4bc | 878 | kobject_put(&cpc_ptr->kobj); |
158c998e | 879 | goto out_free; |
28076483 | 880 | } |
158c998e | 881 | |
1132e6de | 882 | arch_init_invariance_cppc(); |
41ea6672 | 883 | |
337aadff AC |
884 | kfree(output.pointer); |
885 | return 0; | |
886 | ||
887 | out_free: | |
5bbb86aa AC |
888 | /* Free all the mapped sys mem areas for this CPU */ |
889 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
890 | void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
891 | ||
892 | if (addr) | |
893 | iounmap(addr); | |
894 | } | |
337aadff AC |
895 | kfree(cpc_ptr); |
896 | ||
897 | out_buf_free: | |
898 | kfree(output.pointer); | |
899 | return ret; | |
900 | } | |
901 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); | |
902 | ||
903 | /** | |
904 | * acpi_cppc_processor_exit - Cleanup CPC structs. | |
603fadf3 | 905 | * @pr: Ptr to acpi_processor containing this CPU's logical ID. |
337aadff AC |
906 | * |
907 | * Return: Void | |
908 | */ | |
909 | void acpi_cppc_processor_exit(struct acpi_processor *pr) | |
910 | { | |
911 | struct cpc_desc *cpc_ptr; | |
5bbb86aa AC |
912 | unsigned int i; |
913 | void __iomem *addr; | |
85b1407b GC |
914 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); |
915 | ||
e69ae675 | 916 | if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) { |
85b1407b GC |
917 | if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { |
918 | pcc_data[pcc_ss_id]->refcount--; | |
919 | if (!pcc_data[pcc_ss_id]->refcount) { | |
920 | pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); | |
85b1407b | 921 | kfree(pcc_data[pcc_ss_id]); |
56a0b978 | 922 | pcc_data[pcc_ss_id] = NULL; |
85b1407b GC |
923 | } |
924 | } | |
925 | } | |
158c998e | 926 | |
337aadff | 927 | cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); |
9e9d68da SAS |
928 | if (!cpc_ptr) |
929 | return; | |
5bbb86aa AC |
930 | |
931 | /* Free all the mapped sys mem areas for this CPU */ | |
932 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
933 | addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
934 | if (addr) | |
935 | iounmap(addr); | |
936 | } | |
937 | ||
158c998e | 938 | kobject_put(&cpc_ptr->kobj); |
337aadff AC |
939 | kfree(cpc_ptr); |
940 | } | |
941 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); | |
942 | ||
a6cbcdd5 SP |
943 | /** |
944 | * cpc_read_ffh() - Read FFH register | |
603fadf3 | 945 | * @cpunum: CPU number to read |
a6cbcdd5 SP |
946 | * @reg: cppc register information |
947 | * @val: place holder for return value | |
948 | * | |
949 | * Read bit_width bits from a specified address and bit_offset | |
950 | * | |
951 | * Return: 0 for success and error code | |
952 | */ | |
953 | int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | |
954 | { | |
955 | return -ENOTSUPP; | |
956 | } | |
957 | ||
958 | /** | |
959 | * cpc_write_ffh() - Write FFH register | |
603fadf3 | 960 | * @cpunum: CPU number to write |
a6cbcdd5 SP |
961 | * @reg: cppc register information |
962 | * @val: value to write | |
963 | * | |
964 | * Write value of bit_width bits to a specified address and bit_offset | |
965 | * | |
966 | * Return: 0 for success and error code | |
967 | */ | |
968 | int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | |
969 | { | |
970 | return -ENOTSUPP; | |
971 | } | |
972 | ||
77e3d86f PP |
973 | /* |
974 | * Since cpc_read and cpc_write are called while holding pcc_lock, it should be | |
975 | * as fast as possible. We have already mapped the PCC subspace during init, so | |
976 | * we can directly write to it. | |
977 | */ | |
337aadff | 978 | |
a6cbcdd5 | 979 | static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) |
337aadff | 980 | { |
26692cd9 | 981 | void __iomem *vaddr = NULL; |
85b1407b | 982 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa AC |
983 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
984 | ||
985 | if (reg_res->type == ACPI_TYPE_INTEGER) { | |
986 | *val = reg_res->cpc_entry.int_value; | |
f684b107 | 987 | return 0; |
5bbb86aa | 988 | } |
77e3d86f PP |
989 | |
990 | *val = 0; | |
a2c8f92b SN |
991 | |
992 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { | |
993 | u32 width = 8 << (reg->access_width - 1); | |
5f51c7ce | 994 | u32 val_u32; |
a2c8f92b SN |
995 | acpi_status status; |
996 | ||
997 | status = acpi_os_read_port((acpi_io_address)reg->address, | |
5f51c7ce | 998 | &val_u32, width); |
a2c8f92b SN |
999 | if (ACPI_FAILURE(status)) { |
1000 | pr_debug("Error: Failed to read SystemIO port %llx\n", | |
1001 | reg->address); | |
1002 | return -EFAULT; | |
1003 | } | |
1004 | ||
5f51c7ce | 1005 | *val = val_u32; |
a2c8f92b SN |
1006 | return 0; |
1007 | } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) | |
85b1407b | 1008 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
1009 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
1010 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
1011 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
1012 | return cpc_read_ffh(cpu, reg, val); | |
5bbb86aa AC |
1013 | else |
1014 | return acpi_os_read_memory((acpi_physical_address)reg->address, | |
1015 | val, reg->bit_width); | |
337aadff | 1016 | |
5bbb86aa | 1017 | switch (reg->bit_width) { |
e69ae675 XT |
1018 | case 8: |
1019 | *val = readb_relaxed(vaddr); | |
1020 | break; | |
1021 | case 16: | |
1022 | *val = readw_relaxed(vaddr); | |
1023 | break; | |
1024 | case 32: | |
1025 | *val = readl_relaxed(vaddr); | |
1026 | break; | |
1027 | case 64: | |
1028 | *val = readq_relaxed(vaddr); | |
1029 | break; | |
1030 | default: | |
1031 | pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", | |
1032 | reg->bit_width, pcc_ss_id); | |
f684b107 | 1033 | return -EFAULT; |
5bbb86aa AC |
1034 | } |
1035 | ||
f684b107 | 1036 | return 0; |
337aadff AC |
1037 | } |
1038 | ||
a6cbcdd5 | 1039 | static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) |
337aadff | 1040 | { |
77e3d86f | 1041 | int ret_val = 0; |
26692cd9 | 1042 | void __iomem *vaddr = NULL; |
85b1407b | 1043 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
5bbb86aa | 1044 | struct cpc_reg *reg = ®_res->cpc_entry.reg; |
77e3d86f | 1045 | |
a2c8f92b SN |
1046 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { |
1047 | u32 width = 8 << (reg->access_width - 1); | |
1048 | acpi_status status; | |
1049 | ||
1050 | status = acpi_os_write_port((acpi_io_address)reg->address, | |
1051 | (u32)val, width); | |
1052 | if (ACPI_FAILURE(status)) { | |
1053 | pr_debug("Error: Failed to write SystemIO port %llx\n", | |
1054 | reg->address); | |
1055 | return -EFAULT; | |
1056 | } | |
1057 | ||
1058 | return 0; | |
1059 | } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) | |
85b1407b | 1060 | vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); |
5bbb86aa AC |
1061 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) |
1062 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
1063 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
1064 | return cpc_write_ffh(cpu, reg, val); | |
5bbb86aa AC |
1065 | else |
1066 | return acpi_os_write_memory((acpi_physical_address)reg->address, | |
1067 | val, reg->bit_width); | |
337aadff | 1068 | |
5bbb86aa | 1069 | switch (reg->bit_width) { |
e69ae675 XT |
1070 | case 8: |
1071 | writeb_relaxed(val, vaddr); | |
1072 | break; | |
1073 | case 16: | |
1074 | writew_relaxed(val, vaddr); | |
1075 | break; | |
1076 | case 32: | |
1077 | writel_relaxed(val, vaddr); | |
1078 | break; | |
1079 | case 64: | |
1080 | writeq_relaxed(val, vaddr); | |
1081 | break; | |
1082 | default: | |
1083 | pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", | |
1084 | reg->bit_width, pcc_ss_id); | |
1085 | ret_val = -EFAULT; | |
1086 | break; | |
5bbb86aa AC |
1087 | } |
1088 | ||
77e3d86f | 1089 | return ret_val; |
337aadff AC |
1090 | } |
1091 | ||
0654cf05 | 1092 | static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) |
1757d05f XW |
1093 | { |
1094 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
935dff30 RW |
1095 | struct cpc_register_resource *reg; |
1096 | ||
1097 | if (!cpc_desc) { | |
1098 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); | |
1099 | return -ENODEV; | |
1100 | } | |
1101 | ||
1102 | reg = &cpc_desc->cpc_regs[reg_idx]; | |
1757d05f | 1103 | |
0654cf05 RW |
1104 | if (CPC_IN_PCC(reg)) { |
1105 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); | |
1106 | struct cppc_pcc_data *pcc_ss_data = NULL; | |
1757d05f XW |
1107 | int ret = 0; |
1108 | ||
1109 | if (pcc_ss_id < 0) | |
1110 | return -EIO; | |
1111 | ||
1112 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
1113 | ||
1114 | down_write(&pcc_ss_data->pcc_lock); | |
1115 | ||
1116 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) | |
0654cf05 | 1117 | cpc_read(cpunum, reg, perf); |
1757d05f XW |
1118 | else |
1119 | ret = -EIO; | |
1120 | ||
1121 | up_write(&pcc_ss_data->pcc_lock); | |
1122 | ||
1123 | return ret; | |
1124 | } | |
1125 | ||
0654cf05 | 1126 | cpc_read(cpunum, reg, perf); |
1757d05f XW |
1127 | |
1128 | return 0; | |
1129 | } | |
0654cf05 RW |
1130 | |
1131 | /** | |
1132 | * cppc_get_desired_perf - Get the desired performance register value. | |
1133 | * @cpunum: CPU from which to get desired performance. | |
1134 | * @desired_perf: Return address. | |
1135 | * | |
1136 | * Return: 0 for success, -EIO otherwise. | |
1137 | */ | |
1138 | int cppc_get_desired_perf(int cpunum, u64 *desired_perf) | |
1139 | { | |
1140 | return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); | |
1141 | } | |
1757d05f XW |
1142 | EXPORT_SYMBOL_GPL(cppc_get_desired_perf); |
1143 | ||
0654cf05 RW |
1144 | /** |
1145 | * cppc_get_nominal_perf - Get the nominal performance register value. | |
1146 | * @cpunum: CPU from which to get nominal performance. | |
1147 | * @nominal_perf: Return address. | |
1148 | * | |
1149 | * Return: 0 for success, -EIO otherwise. | |
1150 | */ | |
1151 | int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) | |
1152 | { | |
1153 | return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); | |
1154 | } | |
1155 | ||
337aadff | 1156 | /** |
603fadf3 | 1157 | * cppc_get_perf_caps - Get a CPU's performance capabilities. |
337aadff AC |
1158 | * @cpunum: CPU from which to get capabilities info. |
1159 | * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h | |
1160 | * | |
1161 | * Return: 0 for success with perf_caps populated else -ERRNO. | |
1162 | */ | |
1163 | int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) | |
1164 | { | |
1165 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
368520a6 | 1166 | struct cpc_register_resource *highest_reg, *lowest_reg, |
29523f09 | 1167 | *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, |
4773e77c | 1168 | *low_freq_reg = NULL, *nom_freq_reg = NULL; |
29523f09 | 1169 | u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; |
85b1407b | 1170 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1171 | struct cppc_pcc_data *pcc_ss_data = NULL; |
850d64a4 | 1172 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1173 | |
6fa12d58 | 1174 | if (!cpc_desc) { |
337aadff AC |
1175 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1176 | return -ENODEV; | |
1177 | } | |
1178 | ||
1179 | highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; | |
1180 | lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; | |
368520a6 PP |
1181 | lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; |
1182 | nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
4773e77c PP |
1183 | low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; |
1184 | nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; | |
29523f09 | 1185 | guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; |
337aadff | 1186 | |
337aadff | 1187 | /* Are any of the regs PCC ?*/ |
80b8286a | 1188 | if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || |
4773e77c PP |
1189 | CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || |
1190 | CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { | |
6fa12d58 PP |
1191 | if (pcc_ss_id < 0) { |
1192 | pr_debug("Invalid pcc_ss_id\n"); | |
1193 | return -ENODEV; | |
1194 | } | |
1195 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
850d64a4 | 1196 | regs_in_pcc = 1; |
85b1407b | 1197 | down_write(&pcc_ss_data->pcc_lock); |
337aadff | 1198 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1199 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1200 | ret = -EIO; |
1201 | goto out_err; | |
1202 | } | |
1203 | } | |
1204 | ||
a6cbcdd5 | 1205 | cpc_read(cpunum, highest_reg, &high); |
337aadff AC |
1206 | perf_caps->highest_perf = high; |
1207 | ||
a6cbcdd5 | 1208 | cpc_read(cpunum, lowest_reg, &low); |
337aadff AC |
1209 | perf_caps->lowest_perf = low; |
1210 | ||
368520a6 | 1211 | cpc_read(cpunum, nominal_reg, &nom); |
337aadff AC |
1212 | perf_caps->nominal_perf = nom; |
1213 | ||
edef1ef1 SP |
1214 | if (guaranteed_reg->type != ACPI_TYPE_BUFFER || |
1215 | IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { | |
1216 | perf_caps->guaranteed_perf = 0; | |
1217 | } else { | |
1218 | cpc_read(cpunum, guaranteed_reg, &guaranteed); | |
1219 | perf_caps->guaranteed_perf = guaranteed; | |
1220 | } | |
29523f09 | 1221 | |
368520a6 PP |
1222 | cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); |
1223 | perf_caps->lowest_nonlinear_perf = min_nonlinear; | |
1224 | ||
1225 | if (!high || !low || !nom || !min_nonlinear) | |
337aadff AC |
1226 | ret = -EFAULT; |
1227 | ||
4773e77c PP |
1228 | /* Read optional lowest and nominal frequencies if present */ |
1229 | if (CPC_SUPPORTED(low_freq_reg)) | |
1230 | cpc_read(cpunum, low_freq_reg, &low_f); | |
1231 | ||
1232 | if (CPC_SUPPORTED(nom_freq_reg)) | |
1233 | cpc_read(cpunum, nom_freq_reg, &nom_f); | |
1234 | ||
1235 | perf_caps->lowest_freq = low_f; | |
1236 | perf_caps->nominal_freq = nom_f; | |
1237 | ||
1238 | ||
337aadff | 1239 | out_err: |
850d64a4 | 1240 | if (regs_in_pcc) |
85b1407b | 1241 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1242 | return ret; |
1243 | } | |
1244 | EXPORT_SYMBOL_GPL(cppc_get_perf_caps); | |
1245 | ||
ae2df912 JL |
1246 | /** |
1247 | * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region. | |
1248 | * | |
1249 | * CPPC has flexibility about how CPU performance counters are accessed. | |
1250 | * One of the choices is PCC regions, which can have a high access latency. This | |
1251 | * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time. | |
1252 | * | |
1253 | * Return: true if any of the counters are in PCC regions, false otherwise | |
1254 | */ | |
1255 | bool cppc_perf_ctrs_in_pcc(void) | |
1256 | { | |
1257 | int cpu; | |
1258 | ||
1259 | for_each_present_cpu(cpu) { | |
1260 | struct cpc_register_resource *ref_perf_reg; | |
1261 | struct cpc_desc *cpc_desc; | |
1262 | ||
1263 | cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1264 | ||
1265 | if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) || | |
1266 | CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) || | |
1267 | CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME])) | |
1268 | return true; | |
1269 | ||
1270 | ||
1271 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; | |
1272 | ||
1273 | /* | |
1274 | * If reference perf register is not supported then we should | |
1275 | * use the nominal perf value | |
1276 | */ | |
1277 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1278 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
1279 | ||
1280 | if (CPC_IN_PCC(ref_perf_reg)) | |
1281 | return true; | |
1282 | } | |
1283 | ||
1284 | return false; | |
1285 | } | |
1286 | EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc); | |
1287 | ||
337aadff | 1288 | /** |
603fadf3 | 1289 | * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. |
337aadff AC |
1290 | * @cpunum: CPU from which to read counters. |
1291 | * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h | |
1292 | * | |
1293 | * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. | |
1294 | */ | |
1295 | int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) | |
1296 | { | |
1297 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
158c998e AC |
1298 | struct cpc_register_resource *delivered_reg, *reference_reg, |
1299 | *ref_perf_reg, *ctr_wrap_reg; | |
85b1407b | 1300 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); |
6fa12d58 | 1301 | struct cppc_pcc_data *pcc_ss_data = NULL; |
158c998e | 1302 | u64 delivered, reference, ref_perf, ctr_wrap_time; |
850d64a4 | 1303 | int ret = 0, regs_in_pcc = 0; |
337aadff | 1304 | |
6fa12d58 | 1305 | if (!cpc_desc) { |
337aadff AC |
1306 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); |
1307 | return -ENODEV; | |
1308 | } | |
1309 | ||
1310 | delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; | |
1311 | reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; | |
158c998e AC |
1312 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; |
1313 | ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; | |
1314 | ||
1315 | /* | |
603fadf3 | 1316 | * If reference perf register is not supported then we should |
158c998e AC |
1317 | * use the nominal perf value |
1318 | */ | |
1319 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1320 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
337aadff | 1321 | |
337aadff | 1322 | /* Are any of the regs PCC ?*/ |
158c998e AC |
1323 | if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || |
1324 | CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { | |
6fa12d58 PP |
1325 | if (pcc_ss_id < 0) { |
1326 | pr_debug("Invalid pcc_ss_id\n"); | |
1327 | return -ENODEV; | |
1328 | } | |
1329 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b | 1330 | down_write(&pcc_ss_data->pcc_lock); |
850d64a4 | 1331 | regs_in_pcc = 1; |
337aadff | 1332 | /* Ring doorbell once to update PCC subspace */ |
85b1407b | 1333 | if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { |
337aadff AC |
1334 | ret = -EIO; |
1335 | goto out_err; | |
1336 | } | |
1337 | } | |
1338 | ||
a6cbcdd5 SP |
1339 | cpc_read(cpunum, delivered_reg, &delivered); |
1340 | cpc_read(cpunum, reference_reg, &reference); | |
1341 | cpc_read(cpunum, ref_perf_reg, &ref_perf); | |
158c998e AC |
1342 | |
1343 | /* | |
1344 | * Per spec, if ctr_wrap_time optional register is unsupported, then the | |
1345 | * performance counters are assumed to never wrap during the lifetime of | |
1346 | * platform | |
1347 | */ | |
1348 | ctr_wrap_time = (u64)(~((u64)0)); | |
1349 | if (CPC_SUPPORTED(ctr_wrap_reg)) | |
a6cbcdd5 | 1350 | cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); |
337aadff | 1351 | |
158c998e | 1352 | if (!delivered || !reference || !ref_perf) { |
337aadff AC |
1353 | ret = -EFAULT; |
1354 | goto out_err; | |
1355 | } | |
1356 | ||
1357 | perf_fb_ctrs->delivered = delivered; | |
1358 | perf_fb_ctrs->reference = reference; | |
158c998e | 1359 | perf_fb_ctrs->reference_perf = ref_perf; |
2c74d847 | 1360 | perf_fb_ctrs->wraparound_time = ctr_wrap_time; |
337aadff | 1361 | out_err: |
850d64a4 | 1362 | if (regs_in_pcc) |
85b1407b | 1363 | up_write(&pcc_ss_data->pcc_lock); |
337aadff AC |
1364 | return ret; |
1365 | } | |
1366 | EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); | |
1367 | ||
fb0b00af JS |
1368 | /** |
1369 | * cppc_set_enable - Set to enable CPPC on the processor by writing the | |
1370 | * Continuous Performance Control package EnableRegister field. | |
1371 | * @cpu: CPU for which to enable CPPC register. | |
1372 | * @enable: 0 - disable, 1 - enable CPPC feature on the processor. | |
1373 | * | |
1374 | * Return: 0 for success, -ERRNO or -EIO otherwise. | |
1375 | */ | |
1376 | int cppc_set_enable(int cpu, bool enable) | |
1377 | { | |
1378 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); | |
1379 | struct cpc_register_resource *enable_reg; | |
1380 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1381 | struct cppc_pcc_data *pcc_ss_data = NULL; | |
1382 | int ret = -EINVAL; | |
1383 | ||
1384 | if (!cpc_desc) { | |
1385 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); | |
1386 | return -EINVAL; | |
1387 | } | |
1388 | ||
1389 | enable_reg = &cpc_desc->cpc_regs[ENABLE]; | |
1390 | ||
1391 | if (CPC_IN_PCC(enable_reg)) { | |
1392 | ||
1393 | if (pcc_ss_id < 0) | |
1394 | return -EIO; | |
1395 | ||
1396 | ret = cpc_write(cpu, enable_reg, enable); | |
1397 | if (ret) | |
1398 | return ret; | |
1399 | ||
1400 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
1401 | ||
1402 | down_write(&pcc_ss_data->pcc_lock); | |
1403 | /* after writing CPC, transfer the ownership of PCC to platfrom */ | |
1404 | ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
1405 | up_write(&pcc_ss_data->pcc_lock); | |
1406 | return ret; | |
1407 | } | |
1408 | ||
1409 | return cpc_write(cpu, enable_reg, enable); | |
1410 | } | |
1411 | EXPORT_SYMBOL_GPL(cppc_set_enable); | |
1412 | ||
337aadff | 1413 | /** |
603fadf3 | 1414 | * cppc_set_perf - Set a CPU's performance controls. |
337aadff AC |
1415 | * @cpu: CPU for which to set performance controls. |
1416 | * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h | |
1417 | * | |
1418 | * Return: 0 for success, -ERRNO otherwise. | |
1419 | */ | |
1420 | int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) | |
1421 | { | |
1422 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1423 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1424 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); |
6fa12d58 | 1425 | struct cppc_pcc_data *pcc_ss_data = NULL; |
337aadff AC |
1426 | int ret = 0; |
1427 | ||
6fa12d58 | 1428 | if (!cpc_desc) { |
337aadff AC |
1429 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); |
1430 | return -ENODEV; | |
1431 | } | |
1432 | ||
1433 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1434 | ||
80b8286a PP |
1435 | /* |
1436 | * This is Phase-I where we want to write to CPC registers | |
1437 | * -> We want all CPUs to be able to execute this phase in parallel | |
1438 | * | |
1439 | * Since read_lock can be acquired by multiple CPUs simultaneously we | |
1440 | * achieve that goal here | |
1441 | */ | |
1442 | if (CPC_IN_PCC(desired_reg)) { | |
6fa12d58 PP |
1443 | if (pcc_ss_id < 0) { |
1444 | pr_debug("Invalid pcc_ss_id\n"); | |
1445 | return -ENODEV; | |
1446 | } | |
1447 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1448 | down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ |
1449 | if (pcc_ss_data->platform_owns_pcc) { | |
1450 | ret = check_pcc_chan(pcc_ss_id, false); | |
80b8286a | 1451 | if (ret) { |
85b1407b | 1452 | up_read(&pcc_ss_data->pcc_lock); |
80b8286a PP |
1453 | return ret; |
1454 | } | |
80b8286a | 1455 | } |
139aee73 PP |
1456 | /* |
1457 | * Update the pending_write to make sure a PCC CMD_READ will not | |
1458 | * arrive and steal the channel during the switch to write lock | |
1459 | */ | |
85b1407b GC |
1460 | pcc_ss_data->pending_pcc_write_cmd = true; |
1461 | cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; | |
80b8286a | 1462 | cpc_desc->write_cmd_status = 0; |
ad62e1e6 AC |
1463 | } |
1464 | ||
337aadff AC |
1465 | /* |
1466 | * Skip writing MIN/MAX until Linux knows how to come up with | |
1467 | * useful values. | |
1468 | */ | |
a6cbcdd5 | 1469 | cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); |
337aadff | 1470 | |
80b8286a | 1471 | if (CPC_IN_PCC(desired_reg)) |
85b1407b | 1472 | up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ |
80b8286a PP |
1473 | /* |
1474 | * This is Phase-II where we transfer the ownership of PCC to Platform | |
1475 | * | |
1476 | * Short Summary: Basically if we think of a group of cppc_set_perf | |
1477 | * requests that happened in short overlapping interval. The last CPU to | |
1478 | * come out of Phase-I will enter Phase-II and ring the doorbell. | |
1479 | * | |
1480 | * We have the following requirements for Phase-II: | |
1481 | * 1. We want to execute Phase-II only when there are no CPUs | |
1482 | * currently executing in Phase-I | |
1483 | * 2. Once we start Phase-II we want to avoid all other CPUs from | |
1484 | * entering Phase-I. | |
1485 | * 3. We want only one CPU among all those who went through Phase-I | |
1486 | * to run phase-II | |
1487 | * | |
1488 | * If write_trylock fails to get the lock and doesn't transfer the | |
1489 | * PCC ownership to the platform, then one of the following will be TRUE | |
1490 | * 1. There is at-least one CPU in Phase-I which will later execute | |
1491 | * write_trylock, so the CPUs in Phase-I will be responsible for | |
1492 | * executing the Phase-II. | |
1493 | * 2. Some other CPU has beaten this CPU to successfully execute the | |
1494 | * write_trylock and has already acquired the write_lock. We know for a | |
603fadf3 | 1495 | * fact it (other CPU acquiring the write_lock) couldn't have happened |
80b8286a PP |
1496 | * before this CPU's Phase-I as we held the read_lock. |
1497 | * 3. Some other CPU executing pcc CMD_READ has stolen the | |
1498 | * down_write, in which case, send_pcc_cmd will check for pending | |
1499 | * CMD_WRITE commands by checking the pending_pcc_write_cmd. | |
1500 | * So this CPU can be certain that its request will be delivered | |
1501 | * So in all cases, this CPU knows that its request will be delivered | |
1502 | * by another CPU and can return | |
1503 | * | |
1504 | * After getting the down_write we still need to check for | |
1505 | * pending_pcc_write_cmd to take care of the following scenario | |
1506 | * The thread running this code could be scheduled out between | |
1507 | * Phase-I and Phase-II. Before it is scheduled back on, another CPU | |
1508 | * could have delivered the request to Platform by triggering the | |
1509 | * doorbell and transferred the ownership of PCC to platform. So this | |
1510 | * avoids triggering an unnecessary doorbell and more importantly before | |
1511 | * triggering the doorbell it makes sure that the PCC channel ownership | |
1512 | * is still with OSPM. | |
1513 | * pending_pcc_write_cmd can also be cleared by a different CPU, if | |
1514 | * there was a pcc CMD_READ waiting on down_write and it steals the lock | |
935ab850 | 1515 | * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this |
80b8286a PP |
1516 | * case during a CMD_READ and if there are pending writes it delivers |
1517 | * the write command before servicing the read command | |
1518 | */ | |
1519 | if (CPC_IN_PCC(desired_reg)) { | |
85b1407b | 1520 | if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ |
80b8286a | 1521 | /* Update only if there are pending write commands */ |
85b1407b GC |
1522 | if (pcc_ss_data->pending_pcc_write_cmd) |
1523 | send_pcc_cmd(pcc_ss_id, CMD_WRITE); | |
1524 | up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ | |
80b8286a PP |
1525 | } else |
1526 | /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ | |
85b1407b GC |
1527 | wait_event(pcc_ss_data->pcc_write_wait_q, |
1528 | cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); | |
80b8286a PP |
1529 | |
1530 | /* send_pcc_cmd updates the status in case of failure */ | |
1531 | ret = cpc_desc->write_cmd_status; | |
337aadff | 1532 | } |
337aadff AC |
1533 | return ret; |
1534 | } | |
1535 | EXPORT_SYMBOL_GPL(cppc_set_perf); | |
be8b88d7 PP |
1536 | |
1537 | /** | |
1538 | * cppc_get_transition_latency - returns frequency transition latency in ns | |
1539 | * | |
935ab850 TS |
1540 | * ACPI CPPC does not explicitly specify how a platform can specify the |
1541 | * transition latency for performance change requests. The closest we have | |
be8b88d7 PP |
1542 | * is the timing information from the PCCT tables which provides the info |
1543 | * on the number and frequency of PCC commands the platform can handle. | |
6380b7b2 PG |
1544 | * |
1545 | * If desired_reg is in the SystemMemory or SystemIo ACPI address space, | |
1546 | * then assume there is no latency. | |
be8b88d7 PP |
1547 | */ |
1548 | unsigned int cppc_get_transition_latency(int cpu_num) | |
1549 | { | |
1550 | /* | |
1551 | * Expected transition latency is based on the PCCT timing values | |
1552 | * Below are definition from ACPI spec: | |
1553 | * pcc_nominal- Expected latency to process a command, in microseconds | |
1554 | * pcc_mpar - The maximum number of periodic requests that the subspace | |
1555 | * channel can support, reported in commands per minute. 0 | |
1556 | * indicates no limitation. | |
1557 | * pcc_mrtt - The minimum amount of time that OSPM must wait after the | |
1558 | * completion of a command before issuing the next command, | |
1559 | * in microseconds. | |
1560 | */ | |
1561 | unsigned int latency_ns = 0; | |
1562 | struct cpc_desc *cpc_desc; | |
1563 | struct cpc_register_resource *desired_reg; | |
85b1407b | 1564 | int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); |
1ecbd717 | 1565 | struct cppc_pcc_data *pcc_ss_data; |
be8b88d7 PP |
1566 | |
1567 | cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); | |
1568 | if (!cpc_desc) | |
1569 | return CPUFREQ_ETERNAL; | |
1570 | ||
1571 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
6380b7b2 PG |
1572 | if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg)) |
1573 | return 0; | |
1574 | else if (!CPC_IN_PCC(desired_reg)) | |
be8b88d7 PP |
1575 | return CPUFREQ_ETERNAL; |
1576 | ||
1ecbd717 GC |
1577 | if (pcc_ss_id < 0) |
1578 | return CPUFREQ_ETERNAL; | |
1579 | ||
1580 | pcc_ss_data = pcc_data[pcc_ss_id]; | |
85b1407b GC |
1581 | if (pcc_ss_data->pcc_mpar) |
1582 | latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); | |
be8b88d7 | 1583 | |
85b1407b GC |
1584 | latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); |
1585 | latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); | |
be8b88d7 PP |
1586 | |
1587 | return latency_ns; | |
1588 | } | |
1589 | EXPORT_SYMBOL_GPL(cppc_get_transition_latency); |