projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ACPI / LPSS: introduce flags
[linux-2.6-block.git] / drivers / acpi / acpi_lpss.c
CommitLineData
f58b082a
RW		 1/*
2 * ACPI support for Intel Lynxpoint LPSS.
3 *
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/acpi.h>
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/clk-provider.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/clk-lpss.h>
2e0f8822 21#include <linux/pm_runtime.h>
c78b0830 22#include <linux/delay.h>
f58b082a
RW		 23
24#include "internal.h"
25
26ACPI_MODULE_NAME("acpi_lpss");
27
d6ddaaac
RW		 28#ifdef CONFIG_X86_INTEL_LPSS
29
30#define LPSS_ADDR(desc) ((unsigned long)&desc)
31
f58b082a 32#define LPSS_CLK_SIZE 0x04
2e0f8822
RW		 33#define LPSS_LTR_SIZE 0x18
34
35/* Offsets relative to LPSS_PRIVATE_OFFSET */
ed3a872e 36#define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
765bdd4e
MW		 37#define LPSS_RESETS 0x04
38#define LPSS_RESETS_RESET_FUNC BIT(0)
39#define LPSS_RESETS_RESET_APB BIT(1)
2e0f8822
RW		 40#define LPSS_GENERAL 0x08
41#define LPSS_GENERAL_LTR_MODE_SW BIT(2)
088f1fd2 42#define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
2e0f8822
RW		 43#define LPSS_SW_LTR 0x10
44#define LPSS_AUTO_LTR 0x14
1a8f8351
RW		 45#define LPSS_LTR_SNOOP_REQ BIT(15)
46#define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47#define LPSS_LTR_SNOOP_LAT_1US 0x800
48#define LPSS_LTR_SNOOP_LAT_32US 0xC00
49#define LPSS_LTR_SNOOP_LAT_SHIFT 5
50#define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51#define LPSS_LTR_MAX_VAL 0x3FF
06d86415
HK		 52#define LPSS_TX_INT 0x20
53#define LPSS_TX_INT_MASK BIT(1)
f58b082a 54
c78b0830
HK		 55#define LPSS_PRV_REG_COUNT 9
56
ff8c1af5
HK		 57/* LPSS Flags */
58#define LPSS_CLK BIT(0)
59#define LPSS_CLK_GATE BIT(1)
60#define LPSS_CLK_DIVIDER BIT(2)
61#define LPSS_LTR BIT(3)
62#define LPSS_SAVE_CTX BIT(4)
63
f6272170
MW		 64struct lpss_shared_clock {
65 const char *name;
66 unsigned long rate;
67 struct clk *clk;
68};
69
06d86415 70struct lpss_private_data;
f58b082a
RW		 71
72struct lpss_device_desc {
b59cc200 73 const char *clkdev_name;
ff8c1af5 74 unsigned int flags;
2e0f8822 75 unsigned int prv_offset;
958c4eb2 76 size_t prv_size_override;
f6272170 77 struct lpss_shared_clock *shared_clock;
06d86415 78 void (*setup)(struct lpss_private_data *pdata);
f58b082a
RW		 79};
80
b59cc200 81static struct lpss_device_desc lpss_dma_desc = {
b59cc200 82 .clkdev_name = "hclk",
ff8c1af5 83 .flags = LPSS_CLK,
b59cc200
RW		 84};
85
f58b082a
RW		 86struct lpss_private_data {
87 void __iomem *mmio_base;
88 resource_size_t mmio_size;
89 struct clk *clk;
90 const struct lpss_device_desc *dev_desc;
c78b0830 91 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
f58b082a
RW		 92};
93
06d86415
HK		 94static void lpss_uart_setup(struct lpss_private_data *pdata)
95{
088f1fd2 96 unsigned int offset;
06d86415
HK		 97 u32 reg;
98
088f1fd2
HK		 99 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
100 reg = readl(pdata->mmio_base + offset);
101 writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
102
103 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
104 reg = readl(pdata->mmio_base + offset);
105 writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset);
06d86415
HK		 106}
107
765bdd4e
MW		 108static void lpss_i2c_setup(struct lpss_private_data *pdata)
109{
110 unsigned int offset;
111 u32 val;
112
113 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
114 val = readl(pdata->mmio_base + offset);
115 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
116 writel(val, pdata->mmio_base + offset);
117}
118
f58b082a 119static struct lpss_device_desc lpt_dev_desc = {
ff8c1af5 120 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
ed3a872e 121 .prv_offset = 0x800,
ed3a872e
HK		 122};
123
124static struct lpss_device_desc lpt_i2c_dev_desc = {
ff8c1af5 125 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
2e0f8822 126 .prv_offset = 0x800,
2e0f8822
RW		 127};
128
06d86415 129static struct lpss_device_desc lpt_uart_dev_desc = {
ff8c1af5 130 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
06d86415 131 .prv_offset = 0x800,
06d86415 132 .setup = lpss_uart_setup,
2e0f8822
RW		 133};
134
135static struct lpss_device_desc lpt_sdio_dev_desc = {
ff8c1af5 136 .flags = LPSS_LTR,
2e0f8822 137 .prv_offset = 0x1000,
958c4eb2 138 .prv_size_override = 0x1018,
f58b082a
RW		 139};
140
e1c74817
CCE		 141static struct lpss_shared_clock pwm_clock = {
142 .name = "pwm_clk",
143 .rate = 25000000,
144};
145
146static struct lpss_device_desc byt_pwm_dev_desc = {
ff8c1af5 147 .flags = LPSS_CLK | LPSS_SAVE_CTX,
e1c74817
CCE		 148 .shared_clock = &pwm_clock,
149};
150
f6272170 151static struct lpss_device_desc byt_uart_dev_desc = {
ff8c1af5 152 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
f6272170 153 .prv_offset = 0x800,
06d86415 154 .setup = lpss_uart_setup,
f6272170
MW		 155};
156
f6272170 157static struct lpss_device_desc byt_spi_dev_desc = {
ff8c1af5 158 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
f6272170 159 .prv_offset = 0x400,
f6272170
MW		 160};
161
162static struct lpss_device_desc byt_sdio_dev_desc = {
ff8c1af5 163 .flags = LPSS_CLK,
f6272170
MW		 164};
165
166static struct lpss_shared_clock i2c_clock = {
167 .name = "i2c_clk",
168 .rate = 100000000,
169};
170
171static struct lpss_device_desc byt_i2c_dev_desc = {
ff8c1af5 172 .flags = LPSS_CLK | LPSS_SAVE_CTX,
f6272170
MW		 173 .prv_offset = 0x800,
174 .shared_clock = &i2c_clock,
765bdd4e 175 .setup = lpss_i2c_setup,
f6272170
MW		 176};
177
1bfbd8eb
AC		 178static struct lpss_shared_clock bsw_pwm_clock = {
179 .name = "pwm_clk",
180 .rate = 19200000,
181};
182
183static struct lpss_device_desc bsw_pwm_dev_desc = {
ff8c1af5 184 .flags = LPSS_CLK | LPSS_SAVE_CTX,
1bfbd8eb
AC		 185 .shared_clock = &bsw_pwm_clock,
186};
187
d6ddaaac
RW		 188#else
189
190#define LPSS_ADDR(desc) (0UL)
191
192#endif /* CONFIG_X86_INTEL_LPSS */
193
f58b082a 194static const struct acpi_device_id acpi_lpss_device_ids[] = {
b59cc200 195 /* Generic LPSS devices */
d6ddaaac 196 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
b59cc200 197
f58b082a 198 /* Lynxpoint LPSS devices */
d6ddaaac
RW		 199 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
200 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
201 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
202 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
203 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
204 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
205 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
f58b082a
RW		 206 { "INT33C7", },
207
f6272170 208 /* BayTrail LPSS devices */
d6ddaaac
RW		 209 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
210 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
211 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
212 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
213 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
f6272170 214 { "INT33B2", },
20482d32 215 { "INT33FC", },
f6272170 216
1bfbd8eb
AC		 217 /* Braswell LPSS devices */
218 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
219 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
220 { "8086228E", LPSS_ADDR(byt_spi_dev_desc) },
221 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
222
d6ddaaac
RW		 223 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
224 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
225 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
226 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
227 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
228 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
229 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
a4d97536
MW		 230 { "INT3437", },
231
ff8c1af5
HK		 232 /* Wildcat Point LPSS devices */
233 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
43218a1b 234
f58b082a
RW		 235 { }
236};
237
d6ddaaac
RW		 238#ifdef CONFIG_X86_INTEL_LPSS
239
f58b082a
RW		 240static int is_memory(struct acpi_resource *res, void *not_used)
241{
242 struct resource r;
243 return !acpi_dev_resource_memory(res, &r);
244}
245
246/* LPSS main clock device. */
247static struct platform_device *lpss_clk_dev;
248
249static inline void lpt_register_clock_device(void)
250{
251 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
252}
253
254static int register_device_clock(struct acpi_device *adev,
255 struct lpss_private_data *pdata)
256{
257 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
f6272170 258 struct lpss_shared_clock *shared_clock = dev_desc->shared_clock;
ed3a872e 259 const char *devname = dev_name(&adev->dev);
f6272170 260 struct clk *clk = ERR_PTR(-ENODEV);
b59cc200 261 struct lpss_clk_data *clk_data;
ed3a872e
HK		 262 const char *parent, *clk_name;
263 void __iomem *prv_base;
f58b082a
RW		 264
265 if (!lpss_clk_dev)
266 lpt_register_clock_device();
267
b59cc200
RW		 268 clk_data = platform_get_drvdata(lpss_clk_dev);
269 if (!clk_data)
270 return -ENODEV;
271
272 if (dev_desc->clkdev_name) {
273 clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name,
ed3a872e 274 devname);
b59cc200
RW		 275 return 0;
276 }
277
278 if (!pdata->mmio_base
2e0f8822 279 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
f58b082a
RW		 280 return -ENODATA;
281
f6272170 282 parent = clk_data->name;
ed3a872e 283 prv_base = pdata->mmio_base + dev_desc->prv_offset;
f6272170
MW		 284
285 if (shared_clock) {
286 clk = shared_clock->clk;
287 if (!clk) {
288 clk = clk_register_fixed_rate(NULL, shared_clock->name,
289 "lpss_clk", 0,
290 shared_clock->rate);
291 shared_clock->clk = clk;
292 }
293 parent = shared_clock->name;
294 }
295
ff8c1af5 296 if (dev_desc->flags & LPSS_CLK_GATE) {
ed3a872e
HK		 297 clk = clk_register_gate(NULL, devname, parent, 0,
298 prv_base, 0, 0, NULL);
299 parent = devname;
300 }
301
ff8c1af5 302 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
ed3a872e
HK		 303 /* Prevent division by zero */
304 if (!readl(prv_base))
305 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
306
307 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
308 if (!clk_name)
309 return -ENOMEM;
310 clk = clk_register_fractional_divider(NULL, clk_name, parent,
311 0, prv_base,
312 1, 15, 16, 15, 0, NULL);
313 parent = clk_name;
314
315 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
316 if (!clk_name) {
317 kfree(parent);
318 return -ENOMEM;
319 }
320 clk = clk_register_gate(NULL, clk_name, parent,
321 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
322 prv_base, 31, 0, NULL);
323 kfree(parent);
324 kfree(clk_name);
f6272170 325 }
f58b082a 326
f6272170
MW		 327 if (IS_ERR(clk))
328 return PTR_ERR(clk);
f58b082a 329
ed3a872e
HK		 330 pdata->clk = clk;
331 clk_register_clkdev(clk, NULL, devname);
f58b082a
RW		 332 return 0;
333}
334
335static int acpi_lpss_create_device(struct acpi_device *adev,
336 const struct acpi_device_id *id)
337{
338 struct lpss_device_desc *dev_desc;
339 struct lpss_private_data *pdata;
340 struct resource_list_entry *rentry;
341 struct list_head resource_list;
8ce62f85 342 struct platform_device *pdev;
f58b082a
RW		 343 int ret;
344
345 dev_desc = (struct lpss_device_desc *)id->driver_data;
8ce62f85
RW		 346 if (!dev_desc) {
347 pdev = acpi_create_platform_device(adev);
348 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
349 }
f58b082a
RW		 350 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
351 if (!pdata)
352 return -ENOMEM;
353
354 INIT_LIST_HEAD(&resource_list);
355 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
356 if (ret < 0)
357 goto err_out;
358
359 list_for_each_entry(rentry, &resource_list, node)
360 if (resource_type(&rentry->res) == IORESOURCE_MEM) {
958c4eb2
MW		 361 if (dev_desc->prv_size_override)
362 pdata->mmio_size = dev_desc->prv_size_override;
363 else
364 pdata->mmio_size = resource_size(&rentry->res);
f58b082a
RW		 365 pdata->mmio_base = ioremap(rentry->res.start,
366 pdata->mmio_size);
f58b082a
RW		 367 break;
368 }
369
370 acpi_dev_free_resource_list(&resource_list);
371
af65cfe9
MW		 372 pdata->dev_desc = dev_desc;
373
ff8c1af5 374 if (dev_desc->flags & LPSS_CLK) {
f58b082a
RW		 375 ret = register_device_clock(adev, pdata);
376 if (ret) {
b9e95fc6
RW		 377 /* Skip the device, but continue the namespace scan. */
378 ret = 0;
379 goto err_out;
f58b082a
RW		 380 }
381 }
382
b9e95fc6
RW		 383 /*
384 * This works around a known issue in ACPI tables where LPSS devices
385 * have _PS0 and _PS3 without _PSC (and no power resources), so
386 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
387 */
388 ret = acpi_device_fix_up_power(adev);
389 if (ret) {
390 /* Skip the device, but continue the namespace scan. */
391 ret = 0;
392 goto err_out;
393 }
394
06d86415
HK		 395 if (dev_desc->setup)
396 dev_desc->setup(pdata);
397
f58b082a 398 adev->driver_data = pdata;
8ce62f85
RW		 399 pdev = acpi_create_platform_device(adev);
400 if (!IS_ERR_OR_NULL(pdev)) {
401 device_enable_async_suspend(&pdev->dev);
402 return 1;
403 }
f58b082a 404
8ce62f85 405 ret = PTR_ERR(pdev);
f58b082a
RW		 406 adev->driver_data = NULL;
407
408 err_out:
409 kfree(pdata);
410 return ret;
411}
412
1a8f8351
RW		 413static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
414{
415 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
416}
417
418static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
419 unsigned int reg)
420{
421 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
422}
423
2e0f8822
RW		 424static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
425{
426 struct acpi_device *adev;
427 struct lpss_private_data *pdata;
428 unsigned long flags;
429 int ret;
430
431 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
432 if (WARN_ON(ret))
433 return ret;
434
435 spin_lock_irqsave(&dev->power.lock, flags);
436 if (pm_runtime_suspended(dev)) {
437 ret = -EAGAIN;
438 goto out;
439 }
440 pdata = acpi_driver_data(adev);
441 if (WARN_ON(!pdata || !pdata->mmio_base)) {
442 ret = -ENODEV;
443 goto out;
444 }
1a8f8351 445 *val = __lpss_reg_read(pdata, reg);
2e0f8822
RW		 446
447 out:
448 spin_unlock_irqrestore(&dev->power.lock, flags);
449 return ret;
450}
451
452static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
453 char *buf)
454{
455 u32 ltr_value = 0;
456 unsigned int reg;
457 int ret;
458
459 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
460 ret = lpss_reg_read(dev, reg, &ltr_value);
461 if (ret)
462 return ret;
463
464 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
465}
466
467static ssize_t lpss_ltr_mode_show(struct device *dev,
468 struct device_attribute *attr, char *buf)
469{
470 u32 ltr_mode = 0;
471 char *outstr;
472 int ret;
473
474 ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
475 if (ret)
476 return ret;
477
478 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
479 return sprintf(buf, "%s\n", outstr);
480}
481
482static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
483static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
484static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
485
486static struct attribute *lpss_attrs[] = {
487 &dev_attr_auto_ltr.attr,
488 &dev_attr_sw_ltr.attr,
489 &dev_attr_ltr_mode.attr,
490 NULL,
491};
492
493static struct attribute_group lpss_attr_group = {
494 .attrs = lpss_attrs,
495 .name = "lpss_ltr",
496};
497
1a8f8351
RW		 498static void acpi_lpss_set_ltr(struct device *dev, s32 val)
499{
500 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
501 u32 ltr_mode, ltr_val;
502
503 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
504 if (val < 0) {
505 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
506 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
507 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
508 }
509 return;
510 }
511 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
512 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
513 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
514 val = LPSS_LTR_MAX_VAL;
515 } else if (val > LPSS_LTR_MAX_VAL) {
516 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
517 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
518 } else {
519 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
520 }
521 ltr_val |= val;
522 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
523 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
524 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
525 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
526 }
527}
528
c78b0830
HK		 529#ifdef CONFIG_PM
530/**
531 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
532 * @dev: LPSS device
533 *
534 * Most LPSS devices have private registers which may loose their context when
535 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
536 * prv_reg_ctx array.
537 */
538static void acpi_lpss_save_ctx(struct device *dev)
539{
540 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
541 unsigned int i;
542
543 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
544 unsigned long offset = i * sizeof(u32);
545
546 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
547 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
548 pdata->prv_reg_ctx[i], offset);
549 }
550}
551
552/**
553 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
554 * @dev: LPSS device
555 *
556 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
557 */
558static void acpi_lpss_restore_ctx(struct device *dev)
559{
560 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
561 unsigned int i;
562
563 /*
564 * The following delay is needed or the subsequent write operations may
565 * fail. The LPSS devices are actually PCI devices and the PCI spec
566 * expects 10ms delay before the device can be accessed after D3 to D0
567 * transition.
568 */
569 msleep(10);
570
571 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
572 unsigned long offset = i * sizeof(u32);
573
574 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
575 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
576 pdata->prv_reg_ctx[i], offset);
577 }
578}
579
580#ifdef CONFIG_PM_SLEEP
581static int acpi_lpss_suspend_late(struct device *dev)
582{
583 int ret = pm_generic_suspend_late(dev);
584
585 if (ret)
586 return ret;
587
588 acpi_lpss_save_ctx(dev);
589 return acpi_dev_suspend_late(dev);
590}
591
592static int acpi_lpss_restore_early(struct device *dev)
593{
594 int ret = acpi_dev_resume_early(dev);
595
596 if (ret)
597 return ret;
598
599 acpi_lpss_restore_ctx(dev);
600 return pm_generic_resume_early(dev);
601}
602#endif /* CONFIG_PM_SLEEP */
603
604#ifdef CONFIG_PM_RUNTIME
605static int acpi_lpss_runtime_suspend(struct device *dev)
606{
607 int ret = pm_generic_runtime_suspend(dev);
608
609 if (ret)
610 return ret;
611
612 acpi_lpss_save_ctx(dev);
613 return acpi_dev_runtime_suspend(dev);
614}
615
616static int acpi_lpss_runtime_resume(struct device *dev)
617{
618 int ret = acpi_dev_runtime_resume(dev);
619
620 if (ret)
621 return ret;
622
623 acpi_lpss_restore_ctx(dev);
624 return pm_generic_runtime_resume(dev);
625}
626#endif /* CONFIG_PM_RUNTIME */
627#endif /* CONFIG_PM */
628
629static struct dev_pm_domain acpi_lpss_pm_domain = {
630 .ops = {
631#ifdef CONFIG_PM_SLEEP
632 .suspend_late = acpi_lpss_suspend_late,
633 .restore_early = acpi_lpss_restore_early,
634 .prepare = acpi_subsys_prepare,
635 .complete = acpi_subsys_complete,
636 .suspend = acpi_subsys_suspend,
637 .resume_early = acpi_subsys_resume_early,
638 .freeze = acpi_subsys_freeze,
639 .poweroff = acpi_subsys_suspend,
640 .poweroff_late = acpi_subsys_suspend_late,
641#endif
642#ifdef CONFIG_PM_RUNTIME
643 .runtime_suspend = acpi_lpss_runtime_suspend,
644 .runtime_resume = acpi_lpss_runtime_resume,
645#endif
646 },
647};
648
2e0f8822
RW		 649static int acpi_lpss_platform_notify(struct notifier_block *nb,
650 unsigned long action, void *data)
651{
652 struct platform_device *pdev = to_platform_device(data);
653 struct lpss_private_data *pdata;
654 struct acpi_device *adev;
655 const struct acpi_device_id *id;
2e0f8822
RW		 656
657 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
658 if (!id || !id->driver_data)
659 return 0;
660
661 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
662 return 0;
663
664 pdata = acpi_driver_data(adev);
c78b0830 665 if (!pdata || !pdata->mmio_base)
2e0f8822
RW		 666 return 0;
667
668 if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
669 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
670 return 0;
671 }
672
c78b0830
HK		 673 switch (action) {
674 case BUS_NOTIFY_BOUND_DRIVER:
ff8c1af5 675 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
c78b0830
HK		 676 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
677 break;
678 case BUS_NOTIFY_UNBOUND_DRIVER:
ff8c1af5 679 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
c78b0830
HK		 680 pdev->dev.pm_domain = NULL;
681 break;
682 case BUS_NOTIFY_ADD_DEVICE:
ff8c1af5 683 if (pdata->dev_desc->flags & LPSS_LTR)
c78b0830
HK		 684 return sysfs_create_group(&pdev->dev.kobj,
685 &lpss_attr_group);
686 case BUS_NOTIFY_DEL_DEVICE:
ff8c1af5 687 if (pdata->dev_desc->flags & LPSS_LTR)
c78b0830
HK		 688 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
689 default:
690 break;
691 }
2e0f8822 692
c78b0830 693 return 0;
2e0f8822
RW		 694}
695
696static struct notifier_block acpi_lpss_nb = {
697 .notifier_call = acpi_lpss_platform_notify,
698};
699
1a8f8351
RW		 700static void acpi_lpss_bind(struct device *dev)
701{
702 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
703
ff8c1af5 704 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1a8f8351
RW		 705 return;
706
707 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
708 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
709 else
710 dev_err(dev, "MMIO size insufficient to access LTR\n");
711}
712
713static void acpi_lpss_unbind(struct device *dev)
714{
715 dev->power.set_latency_tolerance = NULL;
716}
717
f58b082a
RW		 718static struct acpi_scan_handler lpss_handler = {
719 .ids = acpi_lpss_device_ids,
720 .attach = acpi_lpss_create_device,
1a8f8351
RW		 721 .bind = acpi_lpss_bind,
722 .unbind = acpi_lpss_unbind,
f58b082a
RW		 723};
724
725void __init acpi_lpss_init(void)
726{
2e0f8822
RW		 727 if (!lpt_clk_init()) {
728 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
f58b082a 729 acpi_scan_add_handler(&lpss_handler);
2e0f8822 730 }
f58b082a 731}
d6ddaaac
RW		 732
733#else
734
735static struct acpi_scan_handler lpss_handler = {
736 .ids = acpi_lpss_device_ids,
737};
738
739void __init acpi_lpss_init(void)
740{
741 acpi_scan_add_handler(&lpss_handler);
742}
743
744#endif /* CONFIG_X86_INTEL_LPSS */
Linux 6.x block layer and io_uring tree(s)