Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/clkdev.h> | |
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/platform_data/clk-lpss.h> | |
2e0f8822 | 21 | #include <linux/pm_runtime.h> |
c78b0830 | 22 | #include <linux/delay.h> |
f58b082a RW |
23 | |
24 | #include "internal.h" | |
25 | ||
26 | ACPI_MODULE_NAME("acpi_lpss"); | |
27 | ||
d6ddaaac RW |
28 | #ifdef CONFIG_X86_INTEL_LPSS |
29 | ||
30 | #define LPSS_ADDR(desc) ((unsigned long)&desc) | |
31 | ||
f58b082a | 32 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
33 | #define LPSS_LTR_SIZE 0x18 |
34 | ||
35 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 36 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
37 | #define LPSS_RESETS 0x04 |
38 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
39 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
40 | #define LPSS_GENERAL 0x08 |
41 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 42 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
43 | #define LPSS_SW_LTR 0x10 |
44 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
45 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
46 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
47 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
48 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
49 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
50 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
51 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
52 | #define LPSS_TX_INT 0x20 |
53 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 54 | |
c78b0830 HK |
55 | #define LPSS_PRV_REG_COUNT 9 |
56 | ||
ff8c1af5 HK |
57 | /* LPSS Flags */ |
58 | #define LPSS_CLK BIT(0) | |
59 | #define LPSS_CLK_GATE BIT(1) | |
60 | #define LPSS_CLK_DIVIDER BIT(2) | |
61 | #define LPSS_LTR BIT(3) | |
62 | #define LPSS_SAVE_CTX BIT(4) | |
f6272170 | 63 | |
06d86415 | 64 | struct lpss_private_data; |
f58b082a RW |
65 | |
66 | struct lpss_device_desc { | |
ff8c1af5 | 67 | unsigned int flags; |
2e0f8822 | 68 | unsigned int prv_offset; |
958c4eb2 | 69 | size_t prv_size_override; |
06d86415 | 70 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
71 | }; |
72 | ||
b59cc200 | 73 | static struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 74 | .flags = LPSS_CLK, |
b59cc200 RW |
75 | }; |
76 | ||
f58b082a RW |
77 | struct lpss_private_data { |
78 | void __iomem *mmio_base; | |
79 | resource_size_t mmio_size; | |
03f09f73 | 80 | unsigned int fixed_clk_rate; |
f58b082a RW |
81 | struct clk *clk; |
82 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 83 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
84 | }; |
85 | ||
1f47a77c HK |
86 | /* UART Component Parameter Register */ |
87 | #define LPSS_UART_CPR 0xF4 | |
88 | #define LPSS_UART_CPR_AFCE BIT(4) | |
89 | ||
06d86415 HK |
90 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
91 | { | |
088f1fd2 | 92 | unsigned int offset; |
1f47a77c | 93 | u32 val; |
06d86415 | 94 | |
088f1fd2 | 95 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
96 | val = readl(pdata->mmio_base + offset); |
97 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
98 | ||
99 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
100 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
101 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
102 | val = readl(pdata->mmio_base + offset); | |
103 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
104 | writel(val, pdata->mmio_base + offset); | |
105 | } | |
06d86415 HK |
106 | } |
107 | ||
03f09f73 | 108 | static void byt_i2c_setup(struct lpss_private_data *pdata) |
765bdd4e MW |
109 | { |
110 | unsigned int offset; | |
111 | u32 val; | |
112 | ||
113 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
114 | val = readl(pdata->mmio_base + offset); | |
115 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
116 | writel(val, pdata->mmio_base + offset); | |
765bdd4e | 117 | |
03f09f73 HK |
118 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
119 | pdata->fixed_clk_rate = 133000000; | |
765bdd4e | 120 | } |
43218a1b | 121 | |
f58b082a | 122 | static struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 123 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 124 | .prv_offset = 0x800, |
ed3a872e HK |
125 | }; |
126 | ||
127 | static struct lpss_device_desc lpt_i2c_dev_desc = { | |
f8f87c03 | 128 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 129 | .prv_offset = 0x800, |
2e0f8822 RW |
130 | }; |
131 | ||
06d86415 | 132 | static struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 133 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
06d86415 | 134 | .prv_offset = 0x800, |
06d86415 | 135 | .setup = lpss_uart_setup, |
2e0f8822 RW |
136 | }; |
137 | ||
138 | static struct lpss_device_desc lpt_sdio_dev_desc = { | |
ff8c1af5 | 139 | .flags = LPSS_LTR, |
2e0f8822 | 140 | .prv_offset = 0x1000, |
958c4eb2 | 141 | .prv_size_override = 0x1018, |
e1c74817 CCE |
142 | }; |
143 | ||
144 | static struct lpss_device_desc byt_pwm_dev_desc = { | |
3f56bf3e | 145 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
146 | }; |
147 | ||
f6272170 | 148 | static struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 149 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 150 | .prv_offset = 0x800, |
06d86415 | 151 | .setup = lpss_uart_setup, |
f6272170 MW |
152 | }; |
153 | ||
f6272170 | 154 | static struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 155 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 156 | .prv_offset = 0x400, |
f6272170 MW |
157 | }; |
158 | ||
159 | static struct lpss_device_desc byt_sdio_dev_desc = { | |
3df2da96 | 160 | .flags = LPSS_CLK, |
f6272170 MW |
161 | }; |
162 | ||
163 | static struct lpss_device_desc byt_i2c_dev_desc = { | |
3df2da96 | 164 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 165 | .prv_offset = 0x800, |
03f09f73 | 166 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
167 | }; |
168 | ||
d6ddaaac RW |
169 | #else |
170 | ||
171 | #define LPSS_ADDR(desc) (0UL) | |
172 | ||
173 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
174 | ||
f58b082a | 175 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 176 | /* Generic LPSS devices */ |
d6ddaaac | 177 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 178 | |
f58b082a | 179 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
180 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
181 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
182 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
183 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
184 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
185 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
186 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
187 | { "INT33C7", }, |
188 | ||
f6272170 | 189 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
190 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
191 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
192 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
193 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
194 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 195 | { "INT33B2", }, |
20482d32 | 196 | { "INT33FC", }, |
f6272170 | 197 | |
1bfbd8eb | 198 | /* Braswell LPSS devices */ |
3f56bf3e | 199 | { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, |
1bfbd8eb AC |
200 | { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, |
201 | { "8086228E", LPSS_ADDR(byt_spi_dev_desc) }, | |
202 | { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, | |
203 | ||
d6ddaaac RW |
204 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
205 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
206 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
207 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
208 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
209 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
210 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
211 | { "INT3437", }, |
212 | ||
ff8c1af5 HK |
213 | /* Wildcat Point LPSS devices */ |
214 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 215 | |
f58b082a RW |
216 | { } |
217 | }; | |
218 | ||
d6ddaaac RW |
219 | #ifdef CONFIG_X86_INTEL_LPSS |
220 | ||
f58b082a RW |
221 | static int is_memory(struct acpi_resource *res, void *not_used) |
222 | { | |
223 | struct resource r; | |
224 | return !acpi_dev_resource_memory(res, &r); | |
225 | } | |
226 | ||
227 | /* LPSS main clock device. */ | |
228 | static struct platform_device *lpss_clk_dev; | |
229 | ||
230 | static inline void lpt_register_clock_device(void) | |
231 | { | |
232 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
233 | } | |
234 | ||
235 | static int register_device_clock(struct acpi_device *adev, | |
236 | struct lpss_private_data *pdata) | |
237 | { | |
238 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 239 | const char *devname = dev_name(&adev->dev); |
f6272170 | 240 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 241 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
242 | const char *parent, *clk_name; |
243 | void __iomem *prv_base; | |
f58b082a RW |
244 | |
245 | if (!lpss_clk_dev) | |
246 | lpt_register_clock_device(); | |
247 | ||
b59cc200 RW |
248 | clk_data = platform_get_drvdata(lpss_clk_dev); |
249 | if (!clk_data) | |
250 | return -ENODEV; | |
b0d00f8b | 251 | clk = clk_data->clk; |
b59cc200 RW |
252 | |
253 | if (!pdata->mmio_base | |
2e0f8822 | 254 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
255 | return -ENODATA; |
256 | ||
f6272170 | 257 | parent = clk_data->name; |
ed3a872e | 258 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 259 | |
03f09f73 HK |
260 | if (pdata->fixed_clk_rate) { |
261 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
262 | pdata->fixed_clk_rate); | |
263 | goto out; | |
f6272170 MW |
264 | } |
265 | ||
ff8c1af5 | 266 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
267 | clk = clk_register_gate(NULL, devname, parent, 0, |
268 | prv_base, 0, 0, NULL); | |
269 | parent = devname; | |
270 | } | |
271 | ||
ff8c1af5 | 272 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
273 | /* Prevent division by zero */ |
274 | if (!readl(prv_base)) | |
275 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
276 | ||
277 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
278 | if (!clk_name) | |
279 | return -ENOMEM; | |
280 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
281 | 0, prv_base, | |
282 | 1, 15, 16, 15, 0, NULL); | |
283 | parent = clk_name; | |
284 | ||
285 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
286 | if (!clk_name) { | |
287 | kfree(parent); | |
288 | return -ENOMEM; | |
289 | } | |
290 | clk = clk_register_gate(NULL, clk_name, parent, | |
291 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
292 | prv_base, 31, 0, NULL); | |
293 | kfree(parent); | |
294 | kfree(clk_name); | |
f6272170 | 295 | } |
03f09f73 | 296 | out: |
f6272170 MW |
297 | if (IS_ERR(clk)) |
298 | return PTR_ERR(clk); | |
f58b082a | 299 | |
ed3a872e HK |
300 | pdata->clk = clk; |
301 | clk_register_clkdev(clk, NULL, devname); | |
f58b082a RW |
302 | return 0; |
303 | } | |
304 | ||
305 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
306 | const struct acpi_device_id *id) | |
307 | { | |
308 | struct lpss_device_desc *dev_desc; | |
309 | struct lpss_private_data *pdata; | |
310 | struct resource_list_entry *rentry; | |
311 | struct list_head resource_list; | |
8ce62f85 | 312 | struct platform_device *pdev; |
f58b082a RW |
313 | int ret; |
314 | ||
315 | dev_desc = (struct lpss_device_desc *)id->driver_data; | |
8ce62f85 RW |
316 | if (!dev_desc) { |
317 | pdev = acpi_create_platform_device(adev); | |
318 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
319 | } | |
f58b082a RW |
320 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
321 | if (!pdata) | |
322 | return -ENOMEM; | |
323 | ||
324 | INIT_LIST_HEAD(&resource_list); | |
325 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
326 | if (ret < 0) | |
327 | goto err_out; | |
328 | ||
329 | list_for_each_entry(rentry, &resource_list, node) | |
330 | if (resource_type(&rentry->res) == IORESOURCE_MEM) { | |
958c4eb2 MW |
331 | if (dev_desc->prv_size_override) |
332 | pdata->mmio_size = dev_desc->prv_size_override; | |
333 | else | |
334 | pdata->mmio_size = resource_size(&rentry->res); | |
f58b082a RW |
335 | pdata->mmio_base = ioremap(rentry->res.start, |
336 | pdata->mmio_size); | |
4483d59e HK |
337 | if (!pdata->mmio_base) |
338 | goto err_out; | |
f58b082a RW |
339 | break; |
340 | } | |
341 | ||
342 | acpi_dev_free_resource_list(&resource_list); | |
343 | ||
af65cfe9 MW |
344 | pdata->dev_desc = dev_desc; |
345 | ||
03f09f73 HK |
346 | if (dev_desc->setup) |
347 | dev_desc->setup(pdata); | |
348 | ||
ff8c1af5 | 349 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
350 | ret = register_device_clock(adev, pdata); |
351 | if (ret) { | |
b9e95fc6 RW |
352 | /* Skip the device, but continue the namespace scan. */ |
353 | ret = 0; | |
354 | goto err_out; | |
f58b082a RW |
355 | } |
356 | } | |
357 | ||
b9e95fc6 RW |
358 | /* |
359 | * This works around a known issue in ACPI tables where LPSS devices | |
360 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
361 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
362 | */ | |
363 | ret = acpi_device_fix_up_power(adev); | |
364 | if (ret) { | |
365 | /* Skip the device, but continue the namespace scan. */ | |
366 | ret = 0; | |
367 | goto err_out; | |
368 | } | |
369 | ||
f58b082a | 370 | adev->driver_data = pdata; |
8ce62f85 RW |
371 | pdev = acpi_create_platform_device(adev); |
372 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
373 | return 1; |
374 | } | |
f58b082a | 375 | |
8ce62f85 | 376 | ret = PTR_ERR(pdev); |
f58b082a RW |
377 | adev->driver_data = NULL; |
378 | ||
379 | err_out: | |
380 | kfree(pdata); | |
381 | return ret; | |
382 | } | |
383 | ||
1a8f8351 RW |
384 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
385 | { | |
386 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
387 | } | |
388 | ||
389 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
390 | unsigned int reg) | |
391 | { | |
392 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
393 | } | |
394 | ||
2e0f8822 RW |
395 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
396 | { | |
397 | struct acpi_device *adev; | |
398 | struct lpss_private_data *pdata; | |
399 | unsigned long flags; | |
400 | int ret; | |
401 | ||
402 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
403 | if (WARN_ON(ret)) | |
404 | return ret; | |
405 | ||
406 | spin_lock_irqsave(&dev->power.lock, flags); | |
407 | if (pm_runtime_suspended(dev)) { | |
408 | ret = -EAGAIN; | |
409 | goto out; | |
410 | } | |
411 | pdata = acpi_driver_data(adev); | |
412 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
413 | ret = -ENODEV; | |
414 | goto out; | |
415 | } | |
1a8f8351 | 416 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
417 | |
418 | out: | |
419 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
420 | return ret; | |
421 | } | |
422 | ||
423 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
424 | char *buf) | |
425 | { | |
426 | u32 ltr_value = 0; | |
427 | unsigned int reg; | |
428 | int ret; | |
429 | ||
430 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
431 | ret = lpss_reg_read(dev, reg, <r_value); | |
432 | if (ret) | |
433 | return ret; | |
434 | ||
435 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
436 | } | |
437 | ||
438 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
439 | struct device_attribute *attr, char *buf) | |
440 | { | |
441 | u32 ltr_mode = 0; | |
442 | char *outstr; | |
443 | int ret; | |
444 | ||
445 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
449 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
450 | return sprintf(buf, "%s\n", outstr); | |
451 | } | |
452 | ||
453 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
454 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
455 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
456 | ||
457 | static struct attribute *lpss_attrs[] = { | |
458 | &dev_attr_auto_ltr.attr, | |
459 | &dev_attr_sw_ltr.attr, | |
460 | &dev_attr_ltr_mode.attr, | |
461 | NULL, | |
462 | }; | |
463 | ||
464 | static struct attribute_group lpss_attr_group = { | |
465 | .attrs = lpss_attrs, | |
466 | .name = "lpss_ltr", | |
467 | }; | |
468 | ||
1a8f8351 RW |
469 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
470 | { | |
471 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
472 | u32 ltr_mode, ltr_val; | |
473 | ||
474 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
475 | if (val < 0) { | |
476 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
477 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
478 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
479 | } | |
480 | return; | |
481 | } | |
482 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
483 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
484 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
485 | val = LPSS_LTR_MAX_VAL; | |
486 | } else if (val > LPSS_LTR_MAX_VAL) { | |
487 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
488 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
489 | } else { | |
490 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
491 | } | |
492 | ltr_val |= val; | |
493 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
494 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
495 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
496 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
497 | } | |
498 | } | |
499 | ||
c78b0830 HK |
500 | #ifdef CONFIG_PM |
501 | /** | |
502 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
503 | * @dev: LPSS device | |
cb39dcdd | 504 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
505 | * |
506 | * Most LPSS devices have private registers which may loose their context when | |
507 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
508 | * prv_reg_ctx array. | |
509 | */ | |
cb39dcdd AS |
510 | static void acpi_lpss_save_ctx(struct device *dev, |
511 | struct lpss_private_data *pdata) | |
c78b0830 | 512 | { |
c78b0830 HK |
513 | unsigned int i; |
514 | ||
515 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
516 | unsigned long offset = i * sizeof(u32); | |
517 | ||
518 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
519 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
520 | pdata->prv_reg_ctx[i], offset); | |
521 | } | |
522 | } | |
523 | ||
524 | /** | |
525 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
526 | * @dev: LPSS device | |
cb39dcdd | 527 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
528 | * |
529 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
530 | */ | |
cb39dcdd AS |
531 | static void acpi_lpss_restore_ctx(struct device *dev, |
532 | struct lpss_private_data *pdata) | |
c78b0830 | 533 | { |
c78b0830 HK |
534 | unsigned int i; |
535 | ||
536 | /* | |
537 | * The following delay is needed or the subsequent write operations may | |
538 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
539 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
540 | * transition. | |
541 | */ | |
542 | msleep(10); | |
543 | ||
544 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
545 | unsigned long offset = i * sizeof(u32); | |
546 | ||
547 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
548 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
549 | pdata->prv_reg_ctx[i], offset); | |
550 | } | |
551 | } | |
552 | ||
553 | #ifdef CONFIG_PM_SLEEP | |
554 | static int acpi_lpss_suspend_late(struct device *dev) | |
555 | { | |
cb39dcdd AS |
556 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
557 | int ret; | |
c78b0830 | 558 | |
cb39dcdd | 559 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
560 | if (ret) |
561 | return ret; | |
562 | ||
cb39dcdd AS |
563 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
564 | acpi_lpss_save_ctx(dev, pdata); | |
565 | ||
c78b0830 HK |
566 | return acpi_dev_suspend_late(dev); |
567 | } | |
568 | ||
f4168b61 | 569 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 570 | { |
cb39dcdd AS |
571 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
572 | int ret; | |
c78b0830 | 573 | |
cb39dcdd | 574 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
575 | if (ret) |
576 | return ret; | |
577 | ||
cb39dcdd AS |
578 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
579 | acpi_lpss_restore_ctx(dev, pdata); | |
580 | ||
c78b0830 HK |
581 | return pm_generic_resume_early(dev); |
582 | } | |
583 | #endif /* CONFIG_PM_SLEEP */ | |
584 | ||
c78b0830 HK |
585 | static int acpi_lpss_runtime_suspend(struct device *dev) |
586 | { | |
cb39dcdd AS |
587 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
588 | int ret; | |
c78b0830 | 589 | |
cb39dcdd | 590 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
591 | if (ret) |
592 | return ret; | |
593 | ||
cb39dcdd AS |
594 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
595 | acpi_lpss_save_ctx(dev, pdata); | |
596 | ||
3df2da96 | 597 | return acpi_dev_runtime_suspend(dev); |
c78b0830 HK |
598 | } |
599 | ||
600 | static int acpi_lpss_runtime_resume(struct device *dev) | |
601 | { | |
cb39dcdd AS |
602 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
603 | int ret; | |
c78b0830 | 604 | |
cb39dcdd | 605 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
606 | if (ret) |
607 | return ret; | |
608 | ||
cb39dcdd AS |
609 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
610 | acpi_lpss_restore_ctx(dev, pdata); | |
611 | ||
c78b0830 HK |
612 | return pm_generic_runtime_resume(dev); |
613 | } | |
c78b0830 HK |
614 | #endif /* CONFIG_PM */ |
615 | ||
616 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
617 | .ops = { | |
5de21bb9 | 618 | #ifdef CONFIG_PM |
c78b0830 | 619 | #ifdef CONFIG_PM_SLEEP |
c78b0830 HK |
620 | .prepare = acpi_subsys_prepare, |
621 | .complete = acpi_subsys_complete, | |
622 | .suspend = acpi_subsys_suspend, | |
f4168b61 FZ |
623 | .suspend_late = acpi_lpss_suspend_late, |
624 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
625 | .freeze = acpi_subsys_freeze, |
626 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
627 | .poweroff_late = acpi_lpss_suspend_late, |
628 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 629 | #endif |
c78b0830 HK |
630 | .runtime_suspend = acpi_lpss_runtime_suspend, |
631 | .runtime_resume = acpi_lpss_runtime_resume, | |
632 | #endif | |
633 | }, | |
634 | }; | |
635 | ||
2e0f8822 RW |
636 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
637 | unsigned long action, void *data) | |
638 | { | |
639 | struct platform_device *pdev = to_platform_device(data); | |
640 | struct lpss_private_data *pdata; | |
641 | struct acpi_device *adev; | |
642 | const struct acpi_device_id *id; | |
2e0f8822 RW |
643 | |
644 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
645 | if (!id || !id->driver_data) | |
646 | return 0; | |
647 | ||
648 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
649 | return 0; | |
650 | ||
651 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 652 | if (!pdata) |
2e0f8822 RW |
653 | return 0; |
654 | ||
cb39dcdd AS |
655 | if (pdata->mmio_base && |
656 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
657 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
658 | return 0; | |
659 | } | |
660 | ||
c78b0830 | 661 | switch (action) { |
c78b0830 | 662 | case BUS_NOTIFY_ADD_DEVICE: |
01ac170b | 663 | pdev->dev.pm_domain = &acpi_lpss_pm_domain; |
ff8c1af5 | 664 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
665 | return sysfs_create_group(&pdev->dev.kobj, |
666 | &lpss_attr_group); | |
01ac170b | 667 | break; |
c78b0830 | 668 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 669 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 670 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
01ac170b AS |
671 | pdev->dev.pm_domain = NULL; |
672 | break; | |
c78b0830 HK |
673 | default: |
674 | break; | |
675 | } | |
2e0f8822 | 676 | |
c78b0830 | 677 | return 0; |
2e0f8822 RW |
678 | } |
679 | ||
680 | static struct notifier_block acpi_lpss_nb = { | |
681 | .notifier_call = acpi_lpss_platform_notify, | |
682 | }; | |
683 | ||
1a8f8351 RW |
684 | static void acpi_lpss_bind(struct device *dev) |
685 | { | |
686 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
687 | ||
ff8c1af5 | 688 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
689 | return; |
690 | ||
691 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
692 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
693 | else | |
694 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
695 | } | |
696 | ||
697 | static void acpi_lpss_unbind(struct device *dev) | |
698 | { | |
699 | dev->power.set_latency_tolerance = NULL; | |
700 | } | |
701 | ||
f58b082a RW |
702 | static struct acpi_scan_handler lpss_handler = { |
703 | .ids = acpi_lpss_device_ids, | |
704 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
705 | .bind = acpi_lpss_bind, |
706 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
707 | }; |
708 | ||
709 | void __init acpi_lpss_init(void) | |
710 | { | |
2e0f8822 RW |
711 | if (!lpt_clk_init()) { |
712 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
f58b082a | 713 | acpi_scan_add_handler(&lpss_handler); |
2e0f8822 | 714 | } |
f58b082a | 715 | } |
d6ddaaac RW |
716 | |
717 | #else | |
718 | ||
719 | static struct acpi_scan_handler lpss_handler = { | |
720 | .ids = acpi_lpss_device_ids, | |
721 | }; | |
722 | ||
723 | void __init acpi_lpss_init(void) | |
724 | { | |
725 | acpi_scan_add_handler(&lpss_handler); | |
726 | } | |
727 | ||
728 | #endif /* CONFIG_X86_INTEL_LPSS */ |