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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
6025e2fa | 13 | #include <linux/dmi.h> |
f58b082a RW |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
eebb3e8d | 16 | #include <linux/mutex.h> |
1e30124a | 17 | #include <linux/pci.h> |
f58b082a | 18 | #include <linux/platform_device.h> |
a9443a63 | 19 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 20 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
bf7696a1 | 23 | #include <linux/pwm.h> |
a09c5913 | 24 | #include <linux/suspend.h> |
c78b0830 | 25 | #include <linux/delay.h> |
f58b082a RW |
26 | |
27 | #include "internal.h" | |
28 | ||
d6ddaaac RW |
29 | #ifdef CONFIG_X86_INTEL_LPSS |
30 | ||
eebb3e8d | 31 | #include <asm/cpu_device_id.h> |
4626d840 | 32 | #include <asm/intel-family.h> |
eebb3e8d | 33 | #include <asm/iosf_mbi.h> |
eebb3e8d | 34 | |
d6ddaaac RW |
35 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
36 | ||
f58b082a | 37 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
38 | #define LPSS_LTR_SIZE 0x18 |
39 | ||
40 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 41 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
42 | #define LPSS_RESETS 0x04 |
43 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
44 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
45 | #define LPSS_GENERAL 0x08 |
46 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 47 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
48 | #define LPSS_SW_LTR 0x10 |
49 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
50 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
51 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
52 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
53 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
54 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
55 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
56 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
57 | #define LPSS_TX_INT 0x20 |
58 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 59 | |
c78b0830 HK |
60 | #define LPSS_PRV_REG_COUNT 9 |
61 | ||
ff8c1af5 HK |
62 | /* LPSS Flags */ |
63 | #define LPSS_CLK BIT(0) | |
64 | #define LPSS_CLK_GATE BIT(1) | |
65 | #define LPSS_CLK_DIVIDER BIT(2) | |
66 | #define LPSS_LTR BIT(3) | |
67 | #define LPSS_SAVE_CTX BIT(4) | |
15aa5e4c HG |
68 | /* |
69 | * For some devices the DSDT AML code for another device turns off the device | |
70 | * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) | |
71 | * as ctx register values. | |
72 | * Luckily these devices always use the same ctx register values, so we can | |
73 | * work around this by saving the ctx registers once on activation. | |
74 | */ | |
75 | #define LPSS_SAVE_CTX_ONCE BIT(5) | |
76 | #define LPSS_NO_D3_DELAY BIT(6) | |
f6272170 | 77 | |
06d86415 | 78 | struct lpss_private_data; |
f58b082a RW |
79 | |
80 | struct lpss_device_desc { | |
ff8c1af5 | 81 | unsigned int flags; |
fcf0789a | 82 | const char *clk_con_id; |
2e0f8822 | 83 | unsigned int prv_offset; |
958c4eb2 | 84 | size_t prv_size_override; |
a5565cf2 | 85 | struct property_entry *properties; |
06d86415 | 86 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 87 | bool resume_from_noirq; |
f58b082a RW |
88 | }; |
89 | ||
eebb3e8d | 90 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 91 | .flags = LPSS_CLK, |
b59cc200 RW |
92 | }; |
93 | ||
f58b082a | 94 | struct lpss_private_data { |
dd242a08 | 95 | struct acpi_device *adev; |
f58b082a RW |
96 | void __iomem *mmio_base; |
97 | resource_size_t mmio_size; | |
03f09f73 | 98 | unsigned int fixed_clk_rate; |
f58b082a RW |
99 | struct clk *clk; |
100 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 101 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
102 | }; |
103 | ||
86b62e5c HG |
104 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
105 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
106 | ||
eebb3e8d AS |
107 | /* LPSS run time quirks */ |
108 | static unsigned int lpss_quirks; | |
109 | ||
110 | /* | |
111 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
112 | * | |
fa9e93b1 | 113 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
114 | * it can be powered off automatically whenever the last LPSS device goes down. |
115 | * In case of no power any access to the DMA controller will hang the system. | |
116 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
117 | * well as on ASuS T100TA transformer. | |
118 | * | |
119 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
120 | * on whenever we have at least one other device in use. | |
121 | */ | |
122 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
123 | ||
1f47a77c HK |
124 | /* UART Component Parameter Register */ |
125 | #define LPSS_UART_CPR 0xF4 | |
126 | #define LPSS_UART_CPR_AFCE BIT(4) | |
127 | ||
06d86415 HK |
128 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
129 | { | |
088f1fd2 | 130 | unsigned int offset; |
1f47a77c | 131 | u32 val; |
06d86415 | 132 | |
088f1fd2 | 133 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
134 | val = readl(pdata->mmio_base + offset); |
135 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
136 | ||
137 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
138 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
139 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
140 | val = readl(pdata->mmio_base + offset); | |
141 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
142 | writel(val, pdata->mmio_base + offset); | |
143 | } | |
06d86415 HK |
144 | } |
145 | ||
3095794a | 146 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
147 | { |
148 | unsigned int offset; | |
149 | u32 val; | |
150 | ||
151 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
152 | val = readl(pdata->mmio_base + offset); | |
153 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
154 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
155 | } |
156 | ||
04434ab5 HG |
157 | /* |
158 | * BYT PWM used for backlight control by the i915 driver on systems without | |
159 | * the Crystal Cove PMIC. | |
160 | */ | |
161 | static struct pwm_lookup byt_pwm_lookup[] = { | |
162 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
b2147a3a | 163 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
04434ab5 HG |
164 | "pwm-lpss-platform"), |
165 | }; | |
166 | ||
167 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
168 | { | |
dd242a08 HG |
169 | struct acpi_device *adev = pdata->adev; |
170 | ||
171 | /* Only call pwm_add_table for the first PWM controller */ | |
172 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
173 | return; | |
174 | ||
b2147a3a | 175 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
04434ab5 HG |
176 | } |
177 | ||
3095794a MW |
178 | #define LPSS_I2C_ENABLE 0x6c |
179 | ||
180 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
181 | { | |
86b62e5c HG |
182 | const char *uid_str = acpi_device_uid(pdata->adev); |
183 | acpi_handle handle = pdata->adev->handle; | |
184 | unsigned long long shared_host = 0; | |
185 | acpi_status status; | |
186 | long uid = 0; | |
187 | ||
188 | /* Expected to always be true, but better safe then sorry */ | |
8e3ecc68 LS |
189 | if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) { |
190 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ | |
191 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
192 | if (ACPI_SUCCESS(status) && shared_host) | |
193 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
194 | } | |
86b62e5c | 195 | |
3095794a | 196 | lpss_deassert_reset(pdata); |
765bdd4e | 197 | |
03f09f73 HK |
198 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
199 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
200 | |
201 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 202 | } |
43218a1b | 203 | |
bf7696a1 HG |
204 | /* BSW PWM used for backlight control by the i915 driver */ |
205 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
206 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
b2147a3a | 207 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
bf7696a1 HG |
208 | "pwm-lpss-platform"), |
209 | }; | |
210 | ||
211 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
212 | { | |
dd242a08 HG |
213 | struct acpi_device *adev = pdata->adev; |
214 | ||
215 | /* Only call pwm_add_table for the first PWM controller */ | |
216 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
217 | return; | |
218 | ||
bf7696a1 HG |
219 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
220 | } | |
221 | ||
b2687cd7 | 222 | static const struct lpss_device_desc lpt_dev_desc = { |
57b30064 JN |
223 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
224 | | LPSS_SAVE_CTX, | |
ed3a872e | 225 | .prv_offset = 0x800, |
ed3a872e HK |
226 | }; |
227 | ||
b2687cd7 | 228 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
57b30064 | 229 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, |
2e0f8822 | 230 | .prv_offset = 0x800, |
2e0f8822 RW |
231 | }; |
232 | ||
a5565cf2 HK |
233 | static struct property_entry uart_properties[] = { |
234 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
235 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
236 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
237 | { }, | |
238 | }; | |
239 | ||
b2687cd7 | 240 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
57b30064 JN |
241 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
242 | | LPSS_SAVE_CTX, | |
fcf0789a | 243 | .clk_con_id = "baudclk", |
06d86415 | 244 | .prv_offset = 0x800, |
06d86415 | 245 | .setup = lpss_uart_setup, |
a5565cf2 | 246 | .properties = uart_properties, |
2e0f8822 RW |
247 | }; |
248 | ||
b2687cd7 | 249 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 250 | .flags = LPSS_LTR, |
2e0f8822 | 251 | .prv_offset = 0x1000, |
958c4eb2 | 252 | .prv_size_override = 0x1018, |
e1c74817 CCE |
253 | }; |
254 | ||
b2687cd7 | 255 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 256 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 257 | .prv_offset = 0x800, |
04434ab5 | 258 | .setup = byt_pwm_setup, |
e1c74817 CCE |
259 | }; |
260 | ||
b00855ae | 261 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
15aa5e4c | 262 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, |
fdcb613d | 263 | .prv_offset = 0x800, |
bf7696a1 | 264 | .setup = bsw_pwm_setup, |
5e31ee84 | 265 | .resume_from_noirq = true, |
b00855ae SK |
266 | }; |
267 | ||
b2687cd7 | 268 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 269 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 270 | .clk_con_id = "baudclk", |
f6272170 | 271 | .prv_offset = 0x800, |
06d86415 | 272 | .setup = lpss_uart_setup, |
a5565cf2 | 273 | .properties = uart_properties, |
f6272170 MW |
274 | }; |
275 | ||
b00855ae SK |
276 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
277 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
278 | | LPSS_NO_D3_DELAY, | |
279 | .clk_con_id = "baudclk", | |
280 | .prv_offset = 0x800, | |
281 | .setup = lpss_uart_setup, | |
a5565cf2 | 282 | .properties = uart_properties, |
b00855ae SK |
283 | }; |
284 | ||
b2687cd7 | 285 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 286 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 287 | .prv_offset = 0x400, |
f6272170 MW |
288 | }; |
289 | ||
b2687cd7 | 290 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 291 | .flags = LPSS_CLK, |
f6272170 MW |
292 | }; |
293 | ||
b2687cd7 | 294 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 295 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 296 | .prv_offset = 0x800, |
03f09f73 | 297 | .setup = byt_i2c_setup, |
48402cee | 298 | .resume_from_noirq = true, |
1bfbd8eb AC |
299 | }; |
300 | ||
b00855ae SK |
301 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
302 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
303 | .prv_offset = 0x800, | |
304 | .setup = byt_i2c_setup, | |
48402cee | 305 | .resume_from_noirq = true, |
b00855ae SK |
306 | }; |
307 | ||
eebb3e8d | 308 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
309 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
310 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
311 | .prv_offset = 0x400, |
312 | .setup = lpss_deassert_reset, | |
313 | }; | |
314 | ||
eebb3e8d | 315 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
e36cf2f7 TG |
316 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), |
317 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), | |
eebb3e8d AS |
318 | {} |
319 | }; | |
320 | ||
d6ddaaac RW |
321 | #else |
322 | ||
323 | #define LPSS_ADDR(desc) (0UL) | |
324 | ||
325 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
326 | ||
f58b082a | 327 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 328 | /* Generic LPSS devices */ |
d6ddaaac | 329 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 330 | |
f58b082a | 331 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
332 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
333 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
334 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
335 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
336 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
337 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
338 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
339 | { "INT33C7", }, |
340 | ||
f6272170 | 341 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
342 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
343 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
344 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
345 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
346 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 347 | { "INT33B2", }, |
20482d32 | 348 | { "INT33FC", }, |
f6272170 | 349 | |
1bfbd8eb | 350 | /* Braswell LPSS devices */ |
24071406 | 351 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae SK |
352 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
353 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 354 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 355 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 356 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 357 | |
b00855ae | 358 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
359 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
360 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
361 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
362 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
363 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
364 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
365 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
366 | { "INT3437", }, |
367 | ||
ff8c1af5 HK |
368 | /* Wildcat Point LPSS devices */ |
369 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 370 | |
f58b082a RW |
371 | { } |
372 | }; | |
373 | ||
d6ddaaac RW |
374 | #ifdef CONFIG_X86_INTEL_LPSS |
375 | ||
f58b082a RW |
376 | static int is_memory(struct acpi_resource *res, void *not_used) |
377 | { | |
378 | struct resource r; | |
bb415ed5 | 379 | |
f58b082a RW |
380 | return !acpi_dev_resource_memory(res, &r); |
381 | } | |
382 | ||
383 | /* LPSS main clock device. */ | |
384 | static struct platform_device *lpss_clk_dev; | |
385 | ||
386 | static inline void lpt_register_clock_device(void) | |
387 | { | |
388 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
389 | } | |
390 | ||
391 | static int register_device_clock(struct acpi_device *adev, | |
392 | struct lpss_private_data *pdata) | |
393 | { | |
394 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 395 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 396 | struct clk *clk; |
b59cc200 | 397 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
398 | const char *parent, *clk_name; |
399 | void __iomem *prv_base; | |
f58b082a RW |
400 | |
401 | if (!lpss_clk_dev) | |
402 | lpt_register_clock_device(); | |
403 | ||
b59cc200 RW |
404 | clk_data = platform_get_drvdata(lpss_clk_dev); |
405 | if (!clk_data) | |
406 | return -ENODEV; | |
b0d00f8b | 407 | clk = clk_data->clk; |
b59cc200 RW |
408 | |
409 | if (!pdata->mmio_base | |
2e0f8822 | 410 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
411 | return -ENODATA; |
412 | ||
f6272170 | 413 | parent = clk_data->name; |
ed3a872e | 414 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 415 | |
03f09f73 HK |
416 | if (pdata->fixed_clk_rate) { |
417 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
418 | pdata->fixed_clk_rate); | |
419 | goto out; | |
f6272170 MW |
420 | } |
421 | ||
ff8c1af5 | 422 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
423 | clk = clk_register_gate(NULL, devname, parent, 0, |
424 | prv_base, 0, 0, NULL); | |
425 | parent = devname; | |
426 | } | |
427 | ||
ff8c1af5 | 428 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
429 | /* Prevent division by zero */ |
430 | if (!readl(prv_base)) | |
431 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
432 | ||
433 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
434 | if (!clk_name) | |
435 | return -ENOMEM; | |
436 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
437 | 0, prv_base, | |
438 | 1, 15, 16, 15, 0, NULL); | |
439 | parent = clk_name; | |
440 | ||
441 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
442 | if (!clk_name) { | |
443 | kfree(parent); | |
444 | return -ENOMEM; | |
445 | } | |
446 | clk = clk_register_gate(NULL, clk_name, parent, | |
447 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
448 | prv_base, 31, 0, NULL); | |
449 | kfree(parent); | |
450 | kfree(clk_name); | |
f6272170 | 451 | } |
03f09f73 | 452 | out: |
f6272170 MW |
453 | if (IS_ERR(clk)) |
454 | return PTR_ERR(clk); | |
f58b082a | 455 | |
ed3a872e | 456 | pdata->clk = clk; |
fcf0789a | 457 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
458 | return 0; |
459 | } | |
460 | ||
e6ce0ce3 AH |
461 | struct lpss_device_links { |
462 | const char *supplier_hid; | |
463 | const char *supplier_uid; | |
464 | const char *consumer_hid; | |
465 | const char *consumer_uid; | |
466 | u32 flags; | |
6025e2fa HG |
467 | const struct dmi_system_id *dep_missing_ids; |
468 | }; | |
469 | ||
470 | /* Please keep this list sorted alphabetically by vendor and model */ | |
471 | static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { | |
472 | { | |
473 | .matches = { | |
474 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), | |
475 | DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), | |
476 | }, | |
477 | }, | |
478 | {} | |
e6ce0ce3 AH |
479 | }; |
480 | ||
481 | /* | |
482 | * The _DEP method is used to identify dependencies but instead of creating | |
483 | * device links for every handle in _DEP, only links in the following list are | |
484 | * created. That is necessary because, in the general case, _DEP can refer to | |
485 | * devices that might not have drivers, or that are on different buses, or where | |
486 | * the supplier is not enumerated until after the consumer is probed. | |
487 | */ | |
488 | static const struct lpss_device_links lpss_device_links[] = { | |
cc18735f | 489 | /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ |
e6ce0ce3 | 490 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, |
cc18735f | 491 | /* CHT iGPU depends on PMIC I2C controller */ |
bd0f4e34 | 492 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
b3b3519c | 493 | /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ |
6025e2fa HG |
494 | {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, |
495 | i2c1_dep_missing_dmi_ids}, | |
cc18735f | 496 | /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ |
2d71ee0c | 497 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
cc18735f HG |
498 | /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ |
499 | {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, | |
e6ce0ce3 AH |
500 | }; |
501 | ||
e6ce0ce3 AH |
502 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, |
503 | const struct lpss_device_links *link) | |
504 | { | |
7e70c8ac | 505 | return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
506 | } |
507 | ||
508 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
509 | const struct lpss_device_links *link) | |
510 | { | |
7e70c8ac | 511 | return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
512 | } |
513 | ||
514 | struct hid_uid { | |
515 | const char *hid; | |
516 | const char *uid; | |
517 | }; | |
518 | ||
418e3ea1 | 519 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
520 | { |
521 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 522 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
523 | |
524 | if (!adev) | |
525 | return 0; | |
526 | ||
7e70c8ac | 527 | return acpi_dev_hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
528 | } |
529 | ||
530 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
531 | { | |
1e30124a HG |
532 | struct device *dev; |
533 | ||
e6ce0ce3 AH |
534 | struct hid_uid data = { |
535 | .hid = hid, | |
536 | .uid = uid, | |
537 | }; | |
538 | ||
1e30124a HG |
539 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
540 | if (dev) | |
541 | return dev; | |
542 | ||
543 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
544 | } |
545 | ||
546 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
547 | { | |
548 | struct acpi_handle_list dep_devices; | |
549 | acpi_status status; | |
550 | int i; | |
551 | ||
552 | if (!acpi_has_method(adev->handle, "_DEP")) | |
553 | return false; | |
554 | ||
555 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
556 | &dep_devices); | |
557 | if (ACPI_FAILURE(status)) { | |
558 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
559 | return false; | |
560 | } | |
561 | ||
562 | for (i = 0; i < dep_devices.count; i++) { | |
563 | if (dep_devices.handles[i] == handle) | |
564 | return true; | |
565 | } | |
566 | ||
567 | return false; | |
568 | } | |
569 | ||
570 | static void acpi_lpss_link_consumer(struct device *dev1, | |
571 | const struct lpss_device_links *link) | |
572 | { | |
573 | struct device *dev2; | |
574 | ||
575 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
576 | if (!dev2) | |
577 | return; | |
578 | ||
6025e2fa HG |
579 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
580 | || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
e6ce0ce3 AH |
581 | device_link_add(dev2, dev1, link->flags); |
582 | ||
583 | put_device(dev2); | |
584 | } | |
585 | ||
586 | static void acpi_lpss_link_supplier(struct device *dev1, | |
587 | const struct lpss_device_links *link) | |
588 | { | |
589 | struct device *dev2; | |
590 | ||
591 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
592 | if (!dev2) | |
593 | return; | |
594 | ||
6025e2fa HG |
595 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
596 | || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
e6ce0ce3 AH |
597 | device_link_add(dev1, dev2, link->flags); |
598 | ||
599 | put_device(dev2); | |
600 | } | |
601 | ||
602 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
603 | struct platform_device *pdev) | |
604 | { | |
605 | int i; | |
606 | ||
607 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
608 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
609 | ||
610 | if (acpi_lpss_is_supplier(adev, link)) | |
611 | acpi_lpss_link_consumer(&pdev->dev, link); | |
612 | ||
613 | if (acpi_lpss_is_consumer(adev, link)) | |
614 | acpi_lpss_link_supplier(&pdev->dev, link); | |
615 | } | |
616 | } | |
617 | ||
f58b082a RW |
618 | static int acpi_lpss_create_device(struct acpi_device *adev, |
619 | const struct acpi_device_id *id) | |
620 | { | |
b2687cd7 | 621 | const struct lpss_device_desc *dev_desc; |
f58b082a | 622 | struct lpss_private_data *pdata; |
90e97820 | 623 | struct resource_entry *rentry; |
f58b082a | 624 | struct list_head resource_list; |
8ce62f85 | 625 | struct platform_device *pdev; |
f58b082a RW |
626 | int ret; |
627 | ||
b2687cd7 | 628 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 629 | if (!dev_desc) { |
1571875b | 630 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
631 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
632 | } | |
f58b082a RW |
633 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
634 | if (!pdata) | |
635 | return -ENOMEM; | |
636 | ||
637 | INIT_LIST_HEAD(&resource_list); | |
638 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
639 | if (ret < 0) | |
640 | goto err_out; | |
641 | ||
642 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 643 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
644 | if (dev_desc->prv_size_override) |
645 | pdata->mmio_size = dev_desc->prv_size_override; | |
646 | else | |
90e97820 JL |
647 | pdata->mmio_size = resource_size(rentry->res); |
648 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 649 | pdata->mmio_size); |
f58b082a RW |
650 | break; |
651 | } | |
652 | ||
653 | acpi_dev_free_resource_list(&resource_list); | |
654 | ||
d3e13ff3 | 655 | if (!pdata->mmio_base) { |
e1681599 HG |
656 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
657 | adev->pnp.type.platform_id = 0; | |
a4bb2b49 RT |
658 | /* Skip the device, but continue the namespace scan. */ |
659 | ret = 0; | |
d3e13ff3 RW |
660 | goto err_out; |
661 | } | |
662 | ||
dd242a08 | 663 | pdata->adev = adev; |
af65cfe9 MW |
664 | pdata->dev_desc = dev_desc; |
665 | ||
03f09f73 HK |
666 | if (dev_desc->setup) |
667 | dev_desc->setup(pdata); | |
668 | ||
ff8c1af5 | 669 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
670 | ret = register_device_clock(adev, pdata); |
671 | if (ret) { | |
b9e95fc6 RW |
672 | /* Skip the device, but continue the namespace scan. */ |
673 | ret = 0; | |
674 | goto err_out; | |
f58b082a RW |
675 | } |
676 | } | |
677 | ||
b9e95fc6 RW |
678 | /* |
679 | * This works around a known issue in ACPI tables where LPSS devices | |
680 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
681 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
682 | */ | |
1a2fa02f | 683 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 684 | |
f58b082a | 685 | adev->driver_data = pdata; |
1571875b | 686 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 687 | if (!IS_ERR_OR_NULL(pdev)) { |
e6ce0ce3 | 688 | acpi_lpss_create_device_links(adev, pdev); |
8ce62f85 RW |
689 | return 1; |
690 | } | |
f58b082a | 691 | |
8ce62f85 | 692 | ret = PTR_ERR(pdev); |
f58b082a RW |
693 | adev->driver_data = NULL; |
694 | ||
695 | err_out: | |
696 | kfree(pdata); | |
697 | return ret; | |
698 | } | |
699 | ||
1a8f8351 RW |
700 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
701 | { | |
702 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
703 | } | |
704 | ||
705 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
706 | unsigned int reg) | |
707 | { | |
708 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
709 | } | |
710 | ||
2e0f8822 RW |
711 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
712 | { | |
713 | struct acpi_device *adev; | |
714 | struct lpss_private_data *pdata; | |
715 | unsigned long flags; | |
716 | int ret; | |
717 | ||
718 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
719 | if (WARN_ON(ret)) | |
720 | return ret; | |
721 | ||
722 | spin_lock_irqsave(&dev->power.lock, flags); | |
723 | if (pm_runtime_suspended(dev)) { | |
724 | ret = -EAGAIN; | |
725 | goto out; | |
726 | } | |
727 | pdata = acpi_driver_data(adev); | |
728 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
729 | ret = -ENODEV; | |
730 | goto out; | |
731 | } | |
1a8f8351 | 732 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
733 | |
734 | out: | |
735 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
736 | return ret; | |
737 | } | |
738 | ||
739 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
740 | char *buf) | |
741 | { | |
742 | u32 ltr_value = 0; | |
743 | unsigned int reg; | |
744 | int ret; | |
745 | ||
746 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
747 | ret = lpss_reg_read(dev, reg, <r_value); | |
748 | if (ret) | |
749 | return ret; | |
750 | ||
751 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
752 | } | |
753 | ||
754 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
755 | struct device_attribute *attr, char *buf) | |
756 | { | |
757 | u32 ltr_mode = 0; | |
758 | char *outstr; | |
759 | int ret; | |
760 | ||
761 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
762 | if (ret) | |
763 | return ret; | |
764 | ||
765 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
766 | return sprintf(buf, "%s\n", outstr); | |
767 | } | |
768 | ||
769 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
770 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
771 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
772 | ||
773 | static struct attribute *lpss_attrs[] = { | |
774 | &dev_attr_auto_ltr.attr, | |
775 | &dev_attr_sw_ltr.attr, | |
776 | &dev_attr_ltr_mode.attr, | |
777 | NULL, | |
778 | }; | |
779 | ||
31945d0e | 780 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
781 | .attrs = lpss_attrs, |
782 | .name = "lpss_ltr", | |
783 | }; | |
784 | ||
1a8f8351 RW |
785 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
786 | { | |
787 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
788 | u32 ltr_mode, ltr_val; | |
789 | ||
790 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
791 | if (val < 0) { | |
792 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
793 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
794 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
795 | } | |
796 | return; | |
797 | } | |
798 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
799 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
800 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
801 | val = LPSS_LTR_MAX_VAL; | |
802 | } else if (val > LPSS_LTR_MAX_VAL) { | |
803 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
804 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
805 | } else { | |
806 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
807 | } | |
808 | ltr_val |= val; | |
809 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
810 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
811 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
812 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
813 | } | |
814 | } | |
815 | ||
c78b0830 HK |
816 | #ifdef CONFIG_PM |
817 | /** | |
818 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
819 | * @dev: LPSS device | |
cb39dcdd | 820 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
821 | * |
822 | * Most LPSS devices have private registers which may loose their context when | |
823 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
824 | * prv_reg_ctx array. | |
825 | */ | |
cb39dcdd AS |
826 | static void acpi_lpss_save_ctx(struct device *dev, |
827 | struct lpss_private_data *pdata) | |
c78b0830 | 828 | { |
c78b0830 HK |
829 | unsigned int i; |
830 | ||
831 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
832 | unsigned long offset = i * sizeof(u32); | |
833 | ||
834 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
835 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
836 | pdata->prv_reg_ctx[i], offset); | |
837 | } | |
838 | } | |
839 | ||
840 | /** | |
841 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
842 | * @dev: LPSS device | |
cb39dcdd | 843 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
844 | * |
845 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
846 | */ | |
cb39dcdd AS |
847 | static void acpi_lpss_restore_ctx(struct device *dev, |
848 | struct lpss_private_data *pdata) | |
c78b0830 | 849 | { |
c78b0830 HK |
850 | unsigned int i; |
851 | ||
02b98540 AS |
852 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
853 | unsigned long offset = i * sizeof(u32); | |
854 | ||
855 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
856 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
857 | pdata->prv_reg_ctx[i], offset); | |
858 | } | |
859 | } | |
860 | ||
861 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
862 | { | |
c78b0830 HK |
863 | /* |
864 | * The following delay is needed or the subsequent write operations may | |
865 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
866 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 867 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 868 | */ |
b00855ae SK |
869 | unsigned int delay = 10; /* default 10ms delay */ |
870 | ||
871 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
872 | delay = 0; | |
873 | ||
874 | msleep(delay); | |
c78b0830 HK |
875 | } |
876 | ||
c3a49cf3 AS |
877 | static int acpi_lpss_activate(struct device *dev) |
878 | { | |
879 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
880 | int ret; | |
881 | ||
63705c40 | 882 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
883 | if (ret) |
884 | return ret; | |
885 | ||
886 | acpi_lpss_d3_to_d0_delay(pdata); | |
887 | ||
888 | /* | |
889 | * This is called only on ->probe() stage where a device is either in | |
890 | * known state defined by BIOS or most likely powered off. Due to this | |
891 | * we have to deassert reset line to be sure that ->probe() will | |
892 | * recognize the device. | |
893 | */ | |
15aa5e4c | 894 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
c3a49cf3 AS |
895 | lpss_deassert_reset(pdata); |
896 | ||
15aa5e4c HG |
897 | #ifdef CONFIG_PM |
898 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) | |
899 | acpi_lpss_save_ctx(dev, pdata); | |
900 | #endif | |
901 | ||
c3a49cf3 AS |
902 | return 0; |
903 | } | |
904 | ||
905 | static void acpi_lpss_dismiss(struct device *dev) | |
906 | { | |
cbe25ce3 | 907 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
908 | } |
909 | ||
eebb3e8d AS |
910 | /* IOSF SB for LPSS island */ |
911 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
912 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
913 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
914 | ||
915 | #define LPSS_IOSF_PMCSR 0x84 | |
916 | #define LPSS_PMCSR_D0 0 | |
917 | #define LPSS_PMCSR_D3hot 3 | |
918 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
919 | ||
920 | #define LPSS_IOSF_GPIODEF0 0x154 | |
921 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
922 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
923 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 924 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
925 | |
926 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 927 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
928 | |
929 | static void lpss_iosf_enter_d3_state(void) | |
930 | { | |
931 | u32 value1 = 0; | |
d132d6d5 | 932 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
933 | u32 value2 = LPSS_PMCSR_D3hot; |
934 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
935 | /* | |
936 | * PMC provides an information about actual status of the LPSS devices. | |
937 | * Here we read the values related to LPSS power island, i.e. LPSS | |
938 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
939 | */ | |
86b62e5c | 940 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
941 | int ret; |
942 | ||
943 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
944 | if (ret) | |
945 | return; | |
946 | ||
947 | mutex_lock(&lpss_iosf_mutex); | |
948 | ||
949 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
950 | if (ret) | |
951 | goto exit; | |
952 | ||
953 | /* | |
954 | * Get the status of entire LPSS power island per device basis. | |
955 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
956 | * are already in D3hot. | |
957 | */ | |
86b62e5c | 958 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
959 | if (pmc_status) |
960 | goto exit; | |
961 | ||
962 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
963 | LPSS_IOSF_PMCSR, value2, mask2); | |
964 | ||
965 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
966 | LPSS_IOSF_PMCSR, value2, mask2); | |
967 | ||
968 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
969 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
970 | |
971 | lpss_iosf_d3_entered = true; | |
972 | ||
eebb3e8d AS |
973 | exit: |
974 | mutex_unlock(&lpss_iosf_mutex); | |
975 | } | |
976 | ||
977 | static void lpss_iosf_exit_d3_state(void) | |
978 | { | |
d132d6d5 AS |
979 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
980 | LPSS_GPIODEF0_DMA_LLP; | |
981 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
982 | u32 value2 = LPSS_PMCSR_D0; |
983 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
984 | ||
985 | mutex_lock(&lpss_iosf_mutex); | |
986 | ||
12864ff8 RW |
987 | if (!lpss_iosf_d3_entered) |
988 | goto exit; | |
989 | ||
990 | lpss_iosf_d3_entered = false; | |
991 | ||
eebb3e8d AS |
992 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
993 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
994 | ||
995 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
996 | LPSS_IOSF_PMCSR, value2, mask2); | |
997 | ||
998 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
999 | LPSS_IOSF_PMCSR, value2, mask2); | |
1000 | ||
12864ff8 | 1001 | exit: |
eebb3e8d AS |
1002 | mutex_unlock(&lpss_iosf_mutex); |
1003 | } | |
1004 | ||
12864ff8 | 1005 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 1006 | { |
cb39dcdd AS |
1007 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1008 | int ret; | |
c78b0830 | 1009 | |
cb39dcdd AS |
1010 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1011 | acpi_lpss_save_ctx(dev, pdata); | |
1012 | ||
a192aa92 | 1013 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1014 | |
1015 | /* | |
1016 | * This call must be last in the sequence, otherwise PMC will return | |
1017 | * wrong status for devices being about to be powered off. See | |
1018 | * lpss_iosf_enter_d3_state() for further information. | |
1019 | */ | |
12864ff8 | 1020 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1021 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1022 | lpss_iosf_enter_d3_state(); |
1023 | ||
1024 | return ret; | |
c78b0830 HK |
1025 | } |
1026 | ||
12864ff8 | 1027 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1028 | { |
cb39dcdd AS |
1029 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1030 | int ret; | |
c78b0830 | 1031 | |
eebb3e8d AS |
1032 | /* |
1033 | * This call is kept first to be in symmetry with | |
1034 | * acpi_lpss_runtime_suspend() one. | |
1035 | */ | |
12864ff8 | 1036 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1037 | lpss_iosf_exit_d3_state(); |
1038 | ||
63705c40 | 1039 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1040 | if (ret) |
1041 | return ret; | |
1042 | ||
02b98540 AS |
1043 | acpi_lpss_d3_to_d0_delay(pdata); |
1044 | ||
15aa5e4c | 1045 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
cb39dcdd AS |
1046 | acpi_lpss_restore_ctx(dev, pdata); |
1047 | ||
a192aa92 RW |
1048 | return 0; |
1049 | } | |
1050 | ||
1051 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1052 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1053 | { |
05087360 RW |
1054 | int ret; |
1055 | ||
fa2bfead | 1056 | if (dev_pm_skip_suspend(dev)) |
05087360 | 1057 | return 0; |
a192aa92 | 1058 | |
05087360 | 1059 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1060 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1061 | } |
1062 | ||
48402cee HG |
1063 | static int acpi_lpss_suspend_late(struct device *dev) |
1064 | { | |
1065 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1066 | ||
1067 | if (pdata->dev_desc->resume_from_noirq) | |
1068 | return 0; | |
1069 | ||
1070 | return acpi_lpss_do_suspend_late(dev); | |
1071 | } | |
1072 | ||
1073 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1074 | { | |
1075 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1076 | int ret; | |
1077 | ||
1078 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1079 | /* |
1080 | * The driver's ->suspend_late callback will be invoked by | |
1081 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1082 | * driver really wanted to run that code in ->suspend_noirq, but | |
1083 | * it could not run after acpi_dev_suspend() and the driver | |
1084 | * expected the latter to be called in the "late" phase. | |
1085 | */ | |
48402cee HG |
1086 | ret = acpi_lpss_do_suspend_late(dev); |
1087 | if (ret) | |
1088 | return ret; | |
1089 | } | |
1090 | ||
1091 | return acpi_subsys_suspend_noirq(dev); | |
1092 | } | |
1093 | ||
1094 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1095 | { |
12864ff8 | 1096 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1097 | |
1098 | return ret ? ret : pm_generic_resume_early(dev); | |
1099 | } | |
48402cee HG |
1100 | |
1101 | static int acpi_lpss_resume_early(struct device *dev) | |
1102 | { | |
1103 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1104 | ||
1105 | if (pdata->dev_desc->resume_from_noirq) | |
1106 | return 0; | |
1107 | ||
76c70cb5 | 1108 | if (dev_pm_skip_resume(dev)) |
6e176bf8 RW |
1109 | return 0; |
1110 | ||
48402cee HG |
1111 | return acpi_lpss_do_resume_early(dev); |
1112 | } | |
1113 | ||
1114 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1115 | { | |
1116 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1117 | int ret; | |
1118 | ||
3cd7957e | 1119 | /* Follow acpi_subsys_resume_noirq(). */ |
76c70cb5 | 1120 | if (dev_pm_skip_resume(dev)) |
3cd7957e RW |
1121 | return 0; |
1122 | ||
3cd7957e | 1123 | ret = pm_generic_resume_noirq(dev); |
48402cee HG |
1124 | if (ret) |
1125 | return ret; | |
1126 | ||
3cd7957e RW |
1127 | if (!pdata->dev_desc->resume_from_noirq) |
1128 | return 0; | |
48402cee | 1129 | |
3cd7957e RW |
1130 | /* |
1131 | * The driver's ->resume_early callback will be invoked by | |
1132 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1133 | * really wanted to run that code in ->resume_noirq, but it could not | |
1134 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1135 | * called in the "early" phase. | |
1136 | */ | |
1137 | return acpi_lpss_do_resume_early(dev); | |
1138 | } | |
1139 | ||
1140 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1141 | { | |
1142 | int ret = acpi_lpss_resume(dev); | |
1143 | ||
1144 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1145 | } |
1146 | ||
3cd7957e RW |
1147 | static int acpi_lpss_restore_early(struct device *dev) |
1148 | { | |
1149 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1150 | ||
1151 | if (pdata->dev_desc->resume_from_noirq) | |
1152 | return 0; | |
1153 | ||
1154 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1155 | } |
1156 | ||
3cd7957e RW |
1157 | static int acpi_lpss_restore_noirq(struct device *dev) |
1158 | { | |
1159 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1160 | int ret; | |
1161 | ||
1162 | ret = pm_generic_restore_noirq(dev); | |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
1166 | if (!pdata->dev_desc->resume_from_noirq) | |
1167 | return 0; | |
1168 | ||
1169 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1170 | return acpi_lpss_do_restore_early(dev); | |
1171 | } | |
c95b7595 RW |
1172 | |
1173 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1174 | { | |
1175 | int ret = pm_generic_poweroff_late(dev); | |
1176 | ||
1177 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1178 | } | |
1179 | ||
1180 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1181 | { | |
1182 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1183 | ||
fa2bfead | 1184 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1185 | return 0; |
1186 | ||
1187 | if (pdata->dev_desc->resume_from_noirq) | |
1188 | return 0; | |
1189 | ||
1190 | return acpi_lpss_do_poweroff_late(dev); | |
1191 | } | |
1192 | ||
1193 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1194 | { | |
1195 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1196 | ||
fa2bfead | 1197 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1198 | return 0; |
1199 | ||
1200 | if (pdata->dev_desc->resume_from_noirq) { | |
1201 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1202 | int ret = acpi_lpss_do_poweroff_late(dev); | |
bb415ed5 | 1203 | |
c95b7595 RW |
1204 | if (ret) |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | return pm_generic_poweroff_noirq(dev); | |
1209 | } | |
a192aa92 RW |
1210 | #endif /* CONFIG_PM_SLEEP */ |
1211 | ||
1212 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1213 | { | |
1214 | int ret = pm_generic_runtime_suspend(dev); | |
1215 | ||
1216 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1217 | } | |
1218 | ||
1219 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1220 | { | |
12864ff8 | 1221 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1222 | |
1223 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1224 | } |
c78b0830 HK |
1225 | #endif /* CONFIG_PM */ |
1226 | ||
1227 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1228 | #ifdef CONFIG_PM |
1229 | .activate = acpi_lpss_activate, | |
1230 | .dismiss = acpi_lpss_dismiss, | |
1231 | #endif | |
c78b0830 | 1232 | .ops = { |
5de21bb9 | 1233 | #ifdef CONFIG_PM |
c78b0830 | 1234 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1235 | .prepare = acpi_subsys_prepare, |
e4da817d | 1236 | .complete = acpi_subsys_complete, |
c78b0830 | 1237 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1238 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1239 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1240 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1241 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1242 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1243 | .poweroff = acpi_subsys_poweroff, |
1244 | .poweroff_late = acpi_lpss_poweroff_late, | |
1245 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1246 | .restore_noirq = acpi_lpss_restore_noirq, |
1247 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1248 | #endif |
c78b0830 HK |
1249 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1250 | .runtime_resume = acpi_lpss_runtime_resume, | |
1251 | #endif | |
1252 | }, | |
1253 | }; | |
1254 | ||
2e0f8822 RW |
1255 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1256 | unsigned long action, void *data) | |
1257 | { | |
1258 | struct platform_device *pdev = to_platform_device(data); | |
1259 | struct lpss_private_data *pdata; | |
1260 | struct acpi_device *adev; | |
1261 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1262 | |
1263 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1264 | if (!id || !id->driver_data) | |
1265 | return 0; | |
1266 | ||
1267 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1268 | return 0; | |
1269 | ||
1270 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1271 | if (!pdata) |
2e0f8822 RW |
1272 | return 0; |
1273 | ||
cb39dcdd AS |
1274 | if (pdata->mmio_base && |
1275 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1276 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1277 | return 0; | |
1278 | } | |
1279 | ||
c78b0830 | 1280 | switch (action) { |
de16d552 | 1281 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1282 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1283 | break; |
de16d552 | 1284 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1285 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1286 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1287 | break; |
1288 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1289 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1290 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1291 | return sysfs_create_group(&pdev->dev.kobj, |
1292 | &lpss_attr_group); | |
01ac170b | 1293 | break; |
c78b0830 | 1294 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1295 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1296 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1297 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1298 | break; |
c78b0830 HK |
1299 | default: |
1300 | break; | |
1301 | } | |
2e0f8822 | 1302 | |
c78b0830 | 1303 | return 0; |
2e0f8822 RW |
1304 | } |
1305 | ||
1306 | static struct notifier_block acpi_lpss_nb = { | |
1307 | .notifier_call = acpi_lpss_platform_notify, | |
1308 | }; | |
1309 | ||
1a8f8351 RW |
1310 | static void acpi_lpss_bind(struct device *dev) |
1311 | { | |
1312 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1313 | ||
ff8c1af5 | 1314 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1315 | return; |
1316 | ||
1317 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1318 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1319 | else | |
1320 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1321 | } | |
1322 | ||
1323 | static void acpi_lpss_unbind(struct device *dev) | |
1324 | { | |
1325 | dev->power.set_latency_tolerance = NULL; | |
1326 | } | |
1327 | ||
f58b082a RW |
1328 | static struct acpi_scan_handler lpss_handler = { |
1329 | .ids = acpi_lpss_device_ids, | |
1330 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1331 | .bind = acpi_lpss_bind, |
1332 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1333 | }; |
1334 | ||
1335 | void __init acpi_lpss_init(void) | |
1336 | { | |
eebb3e8d AS |
1337 | const struct x86_cpu_id *id; |
1338 | int ret; | |
1339 | ||
1340 | ret = lpt_clk_init(); | |
1341 | if (ret) | |
1342 | return; | |
1343 | ||
1344 | id = x86_match_cpu(lpss_cpu_ids); | |
1345 | if (id) | |
1346 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1347 | ||
1348 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1349 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1350 | } |
d6ddaaac RW |
1351 | |
1352 | #else | |
1353 | ||
1354 | static struct acpi_scan_handler lpss_handler = { | |
1355 | .ids = acpi_lpss_device_ids, | |
1356 | }; | |
1357 | ||
1358 | void __init acpi_lpss_init(void) | |
1359 | { | |
1360 | acpi_scan_add_handler(&lpss_handler); | |
1361 | } | |
1362 | ||
1363 | #endif /* CONFIG_X86_INTEL_LPSS */ |