Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
1e30124a | 19 | #include <linux/pci.h> |
f58b082a | 20 | #include <linux/platform_device.h> |
a9443a63 | 21 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 22 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 23 | #include <linux/pm_domain.h> |
2e0f8822 | 24 | #include <linux/pm_runtime.h> |
bf7696a1 | 25 | #include <linux/pwm.h> |
a09c5913 | 26 | #include <linux/suspend.h> |
c78b0830 | 27 | #include <linux/delay.h> |
f58b082a RW |
28 | |
29 | #include "internal.h" | |
30 | ||
31 | ACPI_MODULE_NAME("acpi_lpss"); | |
32 | ||
d6ddaaac RW |
33 | #ifdef CONFIG_X86_INTEL_LPSS |
34 | ||
eebb3e8d | 35 | #include <asm/cpu_device_id.h> |
4626d840 | 36 | #include <asm/intel-family.h> |
eebb3e8d | 37 | #include <asm/iosf_mbi.h> |
eebb3e8d | 38 | |
d6ddaaac RW |
39 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
40 | ||
f58b082a | 41 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
42 | #define LPSS_LTR_SIZE 0x18 |
43 | ||
44 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 45 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
46 | #define LPSS_RESETS 0x04 |
47 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
48 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
49 | #define LPSS_GENERAL 0x08 |
50 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 51 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
52 | #define LPSS_SW_LTR 0x10 |
53 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
54 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
55 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
56 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
57 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
58 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
59 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
60 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
61 | #define LPSS_TX_INT 0x20 |
62 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 63 | |
c78b0830 HK |
64 | #define LPSS_PRV_REG_COUNT 9 |
65 | ||
ff8c1af5 HK |
66 | /* LPSS Flags */ |
67 | #define LPSS_CLK BIT(0) | |
68 | #define LPSS_CLK_GATE BIT(1) | |
69 | #define LPSS_CLK_DIVIDER BIT(2) | |
70 | #define LPSS_LTR BIT(3) | |
71 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 72 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 73 | |
c975e472 HG |
74 | /* Crystal Cove PMIC shares same ACPI ID between different platforms */ |
75 | #define BYT_CRC_HRV 2 | |
76 | #define CHT_CRC_HRV 3 | |
77 | ||
06d86415 | 78 | struct lpss_private_data; |
f58b082a RW |
79 | |
80 | struct lpss_device_desc { | |
ff8c1af5 | 81 | unsigned int flags; |
fcf0789a | 82 | const char *clk_con_id; |
2e0f8822 | 83 | unsigned int prv_offset; |
958c4eb2 | 84 | size_t prv_size_override; |
a5565cf2 | 85 | struct property_entry *properties; |
06d86415 | 86 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 87 | bool resume_from_noirq; |
f58b082a RW |
88 | }; |
89 | ||
eebb3e8d | 90 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 91 | .flags = LPSS_CLK, |
b59cc200 RW |
92 | }; |
93 | ||
f58b082a | 94 | struct lpss_private_data { |
dd242a08 | 95 | struct acpi_device *adev; |
f58b082a RW |
96 | void __iomem *mmio_base; |
97 | resource_size_t mmio_size; | |
03f09f73 | 98 | unsigned int fixed_clk_rate; |
f58b082a RW |
99 | struct clk *clk; |
100 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 101 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
102 | }; |
103 | ||
86b62e5c HG |
104 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
105 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
106 | ||
eebb3e8d AS |
107 | /* LPSS run time quirks */ |
108 | static unsigned int lpss_quirks; | |
109 | ||
110 | /* | |
111 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
112 | * | |
fa9e93b1 | 113 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
114 | * it can be powered off automatically whenever the last LPSS device goes down. |
115 | * In case of no power any access to the DMA controller will hang the system. | |
116 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
117 | * well as on ASuS T100TA transformer. | |
118 | * | |
119 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
120 | * on whenever we have at least one other device in use. | |
121 | */ | |
122 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
123 | ||
1f47a77c HK |
124 | /* UART Component Parameter Register */ |
125 | #define LPSS_UART_CPR 0xF4 | |
126 | #define LPSS_UART_CPR_AFCE BIT(4) | |
127 | ||
06d86415 HK |
128 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
129 | { | |
088f1fd2 | 130 | unsigned int offset; |
1f47a77c | 131 | u32 val; |
06d86415 | 132 | |
088f1fd2 | 133 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
134 | val = readl(pdata->mmio_base + offset); |
135 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
136 | ||
137 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
138 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
139 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
140 | val = readl(pdata->mmio_base + offset); | |
141 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
142 | writel(val, pdata->mmio_base + offset); | |
143 | } | |
06d86415 HK |
144 | } |
145 | ||
3095794a | 146 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
147 | { |
148 | unsigned int offset; | |
149 | u32 val; | |
150 | ||
151 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
152 | val = readl(pdata->mmio_base + offset); | |
153 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
154 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
155 | } |
156 | ||
04434ab5 HG |
157 | /* |
158 | * BYT PWM used for backlight control by the i915 driver on systems without | |
159 | * the Crystal Cove PMIC. | |
160 | */ | |
161 | static struct pwm_lookup byt_pwm_lookup[] = { | |
162 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
163 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
164 | "pwm-lpss-platform"), | |
165 | }; | |
166 | ||
167 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
168 | { | |
dd242a08 HG |
169 | struct acpi_device *adev = pdata->adev; |
170 | ||
171 | /* Only call pwm_add_table for the first PWM controller */ | |
172 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
173 | return; | |
174 | ||
c975e472 | 175 | if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV)) |
04434ab5 HG |
176 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
177 | } | |
178 | ||
3095794a MW |
179 | #define LPSS_I2C_ENABLE 0x6c |
180 | ||
181 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
182 | { | |
86b62e5c HG |
183 | const char *uid_str = acpi_device_uid(pdata->adev); |
184 | acpi_handle handle = pdata->adev->handle; | |
185 | unsigned long long shared_host = 0; | |
186 | acpi_status status; | |
187 | long uid = 0; | |
188 | ||
189 | /* Expected to always be true, but better safe then sorry */ | |
190 | if (uid_str) | |
191 | uid = simple_strtol(uid_str, NULL, 10); | |
192 | ||
193 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ | |
194 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
195 | if (ACPI_SUCCESS(status) && shared_host && uid) | |
196 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
197 | ||
3095794a | 198 | lpss_deassert_reset(pdata); |
765bdd4e | 199 | |
03f09f73 HK |
200 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
201 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
202 | |
203 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 204 | } |
43218a1b | 205 | |
bf7696a1 HG |
206 | /* BSW PWM used for backlight control by the i915 driver */ |
207 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
208 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
209 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
210 | "pwm-lpss-platform"), | |
211 | }; | |
212 | ||
213 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
214 | { | |
dd242a08 HG |
215 | struct acpi_device *adev = pdata->adev; |
216 | ||
217 | /* Only call pwm_add_table for the first PWM controller */ | |
218 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
219 | return; | |
220 | ||
bf7696a1 HG |
221 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
222 | } | |
223 | ||
b2687cd7 | 224 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 225 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 226 | .prv_offset = 0x800, |
ed3a872e HK |
227 | }; |
228 | ||
b2687cd7 | 229 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 230 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 231 | .prv_offset = 0x800, |
2e0f8822 RW |
232 | }; |
233 | ||
a5565cf2 HK |
234 | static struct property_entry uart_properties[] = { |
235 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
236 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
237 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
238 | { }, | |
239 | }; | |
240 | ||
b2687cd7 | 241 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 242 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 243 | .clk_con_id = "baudclk", |
06d86415 | 244 | .prv_offset = 0x800, |
06d86415 | 245 | .setup = lpss_uart_setup, |
a5565cf2 | 246 | .properties = uart_properties, |
2e0f8822 RW |
247 | }; |
248 | ||
b2687cd7 | 249 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 250 | .flags = LPSS_LTR, |
2e0f8822 | 251 | .prv_offset = 0x1000, |
958c4eb2 | 252 | .prv_size_override = 0x1018, |
e1c74817 CCE |
253 | }; |
254 | ||
b2687cd7 | 255 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 256 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 257 | .prv_offset = 0x800, |
04434ab5 | 258 | .setup = byt_pwm_setup, |
e1c74817 CCE |
259 | }; |
260 | ||
b00855ae SK |
261 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
262 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
fdcb613d | 263 | .prv_offset = 0x800, |
bf7696a1 | 264 | .setup = bsw_pwm_setup, |
b00855ae SK |
265 | }; |
266 | ||
b2687cd7 | 267 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 268 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 269 | .clk_con_id = "baudclk", |
f6272170 | 270 | .prv_offset = 0x800, |
06d86415 | 271 | .setup = lpss_uart_setup, |
a5565cf2 | 272 | .properties = uart_properties, |
f6272170 MW |
273 | }; |
274 | ||
b00855ae SK |
275 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
276 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
277 | | LPSS_NO_D3_DELAY, | |
278 | .clk_con_id = "baudclk", | |
279 | .prv_offset = 0x800, | |
280 | .setup = lpss_uart_setup, | |
a5565cf2 | 281 | .properties = uart_properties, |
b00855ae SK |
282 | }; |
283 | ||
b2687cd7 | 284 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 285 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 286 | .prv_offset = 0x400, |
f6272170 MW |
287 | }; |
288 | ||
b2687cd7 | 289 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 290 | .flags = LPSS_CLK, |
f6272170 MW |
291 | }; |
292 | ||
b2687cd7 | 293 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 294 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 295 | .prv_offset = 0x800, |
03f09f73 | 296 | .setup = byt_i2c_setup, |
48402cee | 297 | .resume_from_noirq = true, |
1bfbd8eb AC |
298 | }; |
299 | ||
b00855ae SK |
300 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
301 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
302 | .prv_offset = 0x800, | |
303 | .setup = byt_i2c_setup, | |
48402cee | 304 | .resume_from_noirq = true, |
b00855ae SK |
305 | }; |
306 | ||
eebb3e8d | 307 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
308 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
309 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
310 | .prv_offset = 0x400, |
311 | .setup = lpss_deassert_reset, | |
312 | }; | |
313 | ||
eebb3e8d AS |
314 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
315 | ||
316 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
f2c4db1b | 317 | ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ |
4626d840 | 318 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ |
eebb3e8d AS |
319 | {} |
320 | }; | |
321 | ||
d6ddaaac RW |
322 | #else |
323 | ||
324 | #define LPSS_ADDR(desc) (0UL) | |
325 | ||
326 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
327 | ||
f58b082a | 328 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 329 | /* Generic LPSS devices */ |
d6ddaaac | 330 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 331 | |
f58b082a | 332 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
333 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
334 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
335 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
336 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
337 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
338 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
339 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
340 | { "INT33C7", }, |
341 | ||
f6272170 | 342 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
343 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
344 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
345 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
346 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
347 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 348 | { "INT33B2", }, |
20482d32 | 349 | { "INT33FC", }, |
f6272170 | 350 | |
1bfbd8eb | 351 | /* Braswell LPSS devices */ |
24071406 | 352 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae SK |
353 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
354 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 355 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 356 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 357 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 358 | |
b00855ae | 359 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
360 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
361 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
362 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
363 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
364 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
365 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
366 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
367 | { "INT3437", }, |
368 | ||
ff8c1af5 HK |
369 | /* Wildcat Point LPSS devices */ |
370 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 371 | |
f58b082a RW |
372 | { } |
373 | }; | |
374 | ||
d6ddaaac RW |
375 | #ifdef CONFIG_X86_INTEL_LPSS |
376 | ||
f58b082a RW |
377 | static int is_memory(struct acpi_resource *res, void *not_used) |
378 | { | |
379 | struct resource r; | |
380 | return !acpi_dev_resource_memory(res, &r); | |
381 | } | |
382 | ||
383 | /* LPSS main clock device. */ | |
384 | static struct platform_device *lpss_clk_dev; | |
385 | ||
386 | static inline void lpt_register_clock_device(void) | |
387 | { | |
388 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
389 | } | |
390 | ||
391 | static int register_device_clock(struct acpi_device *adev, | |
392 | struct lpss_private_data *pdata) | |
393 | { | |
394 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 395 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 396 | struct clk *clk; |
b59cc200 | 397 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
398 | const char *parent, *clk_name; |
399 | void __iomem *prv_base; | |
f58b082a RW |
400 | |
401 | if (!lpss_clk_dev) | |
402 | lpt_register_clock_device(); | |
403 | ||
b59cc200 RW |
404 | clk_data = platform_get_drvdata(lpss_clk_dev); |
405 | if (!clk_data) | |
406 | return -ENODEV; | |
b0d00f8b | 407 | clk = clk_data->clk; |
b59cc200 RW |
408 | |
409 | if (!pdata->mmio_base | |
2e0f8822 | 410 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
411 | return -ENODATA; |
412 | ||
f6272170 | 413 | parent = clk_data->name; |
ed3a872e | 414 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 415 | |
03f09f73 HK |
416 | if (pdata->fixed_clk_rate) { |
417 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
418 | pdata->fixed_clk_rate); | |
419 | goto out; | |
f6272170 MW |
420 | } |
421 | ||
ff8c1af5 | 422 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
423 | clk = clk_register_gate(NULL, devname, parent, 0, |
424 | prv_base, 0, 0, NULL); | |
425 | parent = devname; | |
426 | } | |
427 | ||
ff8c1af5 | 428 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
429 | /* Prevent division by zero */ |
430 | if (!readl(prv_base)) | |
431 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
432 | ||
433 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
434 | if (!clk_name) | |
435 | return -ENOMEM; | |
436 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
437 | 0, prv_base, | |
438 | 1, 15, 16, 15, 0, NULL); | |
439 | parent = clk_name; | |
440 | ||
441 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
442 | if (!clk_name) { | |
443 | kfree(parent); | |
444 | return -ENOMEM; | |
445 | } | |
446 | clk = clk_register_gate(NULL, clk_name, parent, | |
447 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
448 | prv_base, 31, 0, NULL); | |
449 | kfree(parent); | |
450 | kfree(clk_name); | |
f6272170 | 451 | } |
03f09f73 | 452 | out: |
f6272170 MW |
453 | if (IS_ERR(clk)) |
454 | return PTR_ERR(clk); | |
f58b082a | 455 | |
ed3a872e | 456 | pdata->clk = clk; |
fcf0789a | 457 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
458 | return 0; |
459 | } | |
460 | ||
e6ce0ce3 AH |
461 | struct lpss_device_links { |
462 | const char *supplier_hid; | |
463 | const char *supplier_uid; | |
464 | const char *consumer_hid; | |
465 | const char *consumer_uid; | |
466 | u32 flags; | |
467 | }; | |
468 | ||
469 | /* | |
470 | * The _DEP method is used to identify dependencies but instead of creating | |
471 | * device links for every handle in _DEP, only links in the following list are | |
472 | * created. That is necessary because, in the general case, _DEP can refer to | |
473 | * devices that might not have drivers, or that are on different buses, or where | |
474 | * the supplier is not enumerated until after the consumer is probed. | |
475 | */ | |
476 | static const struct lpss_device_links lpss_device_links[] = { | |
477 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, | |
bd0f4e34 | 478 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
2d71ee0c | 479 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
e6ce0ce3 AH |
480 | }; |
481 | ||
ea625ce1 | 482 | static bool hid_uid_match(struct acpi_device *adev, |
e6ce0ce3 AH |
483 | const char *hid2, const char *uid2) |
484 | { | |
ea625ce1 HG |
485 | const char *hid1 = acpi_device_hid(adev); |
486 | const char *uid1 = acpi_device_uid(adev); | |
487 | ||
a92a5563 HG |
488 | if (strcmp(hid1, hid2)) |
489 | return false; | |
490 | ||
491 | if (!uid2) | |
492 | return true; | |
493 | ||
494 | return uid1 && !strcmp(uid1, uid2); | |
e6ce0ce3 AH |
495 | } |
496 | ||
497 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, | |
498 | const struct lpss_device_links *link) | |
499 | { | |
ea625ce1 | 500 | return hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
501 | } |
502 | ||
503 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
504 | const struct lpss_device_links *link) | |
505 | { | |
ea625ce1 | 506 | return hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
507 | } |
508 | ||
509 | struct hid_uid { | |
510 | const char *hid; | |
511 | const char *uid; | |
512 | }; | |
513 | ||
514 | static int match_hid_uid(struct device *dev, void *data) | |
515 | { | |
516 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
517 | struct hid_uid *id = data; | |
518 | ||
519 | if (!adev) | |
520 | return 0; | |
521 | ||
ea625ce1 | 522 | return hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
523 | } |
524 | ||
525 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
526 | { | |
1e30124a HG |
527 | struct device *dev; |
528 | ||
e6ce0ce3 AH |
529 | struct hid_uid data = { |
530 | .hid = hid, | |
531 | .uid = uid, | |
532 | }; | |
533 | ||
1e30124a HG |
534 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
535 | if (dev) | |
536 | return dev; | |
537 | ||
538 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
539 | } |
540 | ||
541 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
542 | { | |
543 | struct acpi_handle_list dep_devices; | |
544 | acpi_status status; | |
545 | int i; | |
546 | ||
547 | if (!acpi_has_method(adev->handle, "_DEP")) | |
548 | return false; | |
549 | ||
550 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
551 | &dep_devices); | |
552 | if (ACPI_FAILURE(status)) { | |
553 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
554 | return false; | |
555 | } | |
556 | ||
557 | for (i = 0; i < dep_devices.count; i++) { | |
558 | if (dep_devices.handles[i] == handle) | |
559 | return true; | |
560 | } | |
561 | ||
562 | return false; | |
563 | } | |
564 | ||
565 | static void acpi_lpss_link_consumer(struct device *dev1, | |
566 | const struct lpss_device_links *link) | |
567 | { | |
568 | struct device *dev2; | |
569 | ||
570 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
571 | if (!dev2) | |
572 | return; | |
573 | ||
574 | if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
575 | device_link_add(dev2, dev1, link->flags); | |
576 | ||
577 | put_device(dev2); | |
578 | } | |
579 | ||
580 | static void acpi_lpss_link_supplier(struct device *dev1, | |
581 | const struct lpss_device_links *link) | |
582 | { | |
583 | struct device *dev2; | |
584 | ||
585 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
586 | if (!dev2) | |
587 | return; | |
588 | ||
589 | if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
590 | device_link_add(dev1, dev2, link->flags); | |
591 | ||
592 | put_device(dev2); | |
593 | } | |
594 | ||
595 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
596 | struct platform_device *pdev) | |
597 | { | |
598 | int i; | |
599 | ||
600 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
601 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
602 | ||
603 | if (acpi_lpss_is_supplier(adev, link)) | |
604 | acpi_lpss_link_consumer(&pdev->dev, link); | |
605 | ||
606 | if (acpi_lpss_is_consumer(adev, link)) | |
607 | acpi_lpss_link_supplier(&pdev->dev, link); | |
608 | } | |
609 | } | |
610 | ||
f58b082a RW |
611 | static int acpi_lpss_create_device(struct acpi_device *adev, |
612 | const struct acpi_device_id *id) | |
613 | { | |
b2687cd7 | 614 | const struct lpss_device_desc *dev_desc; |
f58b082a | 615 | struct lpss_private_data *pdata; |
90e97820 | 616 | struct resource_entry *rentry; |
f58b082a | 617 | struct list_head resource_list; |
8ce62f85 | 618 | struct platform_device *pdev; |
f58b082a RW |
619 | int ret; |
620 | ||
b2687cd7 | 621 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 622 | if (!dev_desc) { |
1571875b | 623 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
624 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
625 | } | |
f58b082a RW |
626 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
627 | if (!pdata) | |
628 | return -ENOMEM; | |
629 | ||
630 | INIT_LIST_HEAD(&resource_list); | |
631 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
632 | if (ret < 0) | |
633 | goto err_out; | |
634 | ||
635 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 636 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
637 | if (dev_desc->prv_size_override) |
638 | pdata->mmio_size = dev_desc->prv_size_override; | |
639 | else | |
90e97820 JL |
640 | pdata->mmio_size = resource_size(rentry->res); |
641 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 642 | pdata->mmio_size); |
f58b082a RW |
643 | break; |
644 | } | |
645 | ||
646 | acpi_dev_free_resource_list(&resource_list); | |
647 | ||
d3e13ff3 | 648 | if (!pdata->mmio_base) { |
e1681599 HG |
649 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
650 | adev->pnp.type.platform_id = 0; | |
a4bb2b49 RT |
651 | /* Skip the device, but continue the namespace scan. */ |
652 | ret = 0; | |
d3e13ff3 RW |
653 | goto err_out; |
654 | } | |
655 | ||
dd242a08 | 656 | pdata->adev = adev; |
af65cfe9 MW |
657 | pdata->dev_desc = dev_desc; |
658 | ||
03f09f73 HK |
659 | if (dev_desc->setup) |
660 | dev_desc->setup(pdata); | |
661 | ||
ff8c1af5 | 662 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
663 | ret = register_device_clock(adev, pdata); |
664 | if (ret) { | |
b9e95fc6 RW |
665 | /* Skip the device, but continue the namespace scan. */ |
666 | ret = 0; | |
667 | goto err_out; | |
f58b082a RW |
668 | } |
669 | } | |
670 | ||
b9e95fc6 RW |
671 | /* |
672 | * This works around a known issue in ACPI tables where LPSS devices | |
673 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
674 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
675 | */ | |
1a2fa02f | 676 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 677 | |
f58b082a | 678 | adev->driver_data = pdata; |
1571875b | 679 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 680 | if (!IS_ERR_OR_NULL(pdev)) { |
e6ce0ce3 | 681 | acpi_lpss_create_device_links(adev, pdev); |
8ce62f85 RW |
682 | return 1; |
683 | } | |
f58b082a | 684 | |
8ce62f85 | 685 | ret = PTR_ERR(pdev); |
f58b082a RW |
686 | adev->driver_data = NULL; |
687 | ||
688 | err_out: | |
689 | kfree(pdata); | |
690 | return ret; | |
691 | } | |
692 | ||
1a8f8351 RW |
693 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
694 | { | |
695 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
696 | } | |
697 | ||
698 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
699 | unsigned int reg) | |
700 | { | |
701 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
702 | } | |
703 | ||
2e0f8822 RW |
704 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
705 | { | |
706 | struct acpi_device *adev; | |
707 | struct lpss_private_data *pdata; | |
708 | unsigned long flags; | |
709 | int ret; | |
710 | ||
711 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
712 | if (WARN_ON(ret)) | |
713 | return ret; | |
714 | ||
715 | spin_lock_irqsave(&dev->power.lock, flags); | |
716 | if (pm_runtime_suspended(dev)) { | |
717 | ret = -EAGAIN; | |
718 | goto out; | |
719 | } | |
720 | pdata = acpi_driver_data(adev); | |
721 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
722 | ret = -ENODEV; | |
723 | goto out; | |
724 | } | |
1a8f8351 | 725 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
726 | |
727 | out: | |
728 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
729 | return ret; | |
730 | } | |
731 | ||
732 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
733 | char *buf) | |
734 | { | |
735 | u32 ltr_value = 0; | |
736 | unsigned int reg; | |
737 | int ret; | |
738 | ||
739 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
740 | ret = lpss_reg_read(dev, reg, <r_value); | |
741 | if (ret) | |
742 | return ret; | |
743 | ||
744 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
745 | } | |
746 | ||
747 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
748 | struct device_attribute *attr, char *buf) | |
749 | { | |
750 | u32 ltr_mode = 0; | |
751 | char *outstr; | |
752 | int ret; | |
753 | ||
754 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
755 | if (ret) | |
756 | return ret; | |
757 | ||
758 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
759 | return sprintf(buf, "%s\n", outstr); | |
760 | } | |
761 | ||
762 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
763 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
764 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
765 | ||
766 | static struct attribute *lpss_attrs[] = { | |
767 | &dev_attr_auto_ltr.attr, | |
768 | &dev_attr_sw_ltr.attr, | |
769 | &dev_attr_ltr_mode.attr, | |
770 | NULL, | |
771 | }; | |
772 | ||
31945d0e | 773 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
774 | .attrs = lpss_attrs, |
775 | .name = "lpss_ltr", | |
776 | }; | |
777 | ||
1a8f8351 RW |
778 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
779 | { | |
780 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
781 | u32 ltr_mode, ltr_val; | |
782 | ||
783 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
784 | if (val < 0) { | |
785 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
786 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
787 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
788 | } | |
789 | return; | |
790 | } | |
791 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
792 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
793 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
794 | val = LPSS_LTR_MAX_VAL; | |
795 | } else if (val > LPSS_LTR_MAX_VAL) { | |
796 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
797 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
798 | } else { | |
799 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
800 | } | |
801 | ltr_val |= val; | |
802 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
803 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
804 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
805 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
806 | } | |
807 | } | |
808 | ||
c78b0830 HK |
809 | #ifdef CONFIG_PM |
810 | /** | |
811 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
812 | * @dev: LPSS device | |
cb39dcdd | 813 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
814 | * |
815 | * Most LPSS devices have private registers which may loose their context when | |
816 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
817 | * prv_reg_ctx array. | |
818 | */ | |
cb39dcdd AS |
819 | static void acpi_lpss_save_ctx(struct device *dev, |
820 | struct lpss_private_data *pdata) | |
c78b0830 | 821 | { |
c78b0830 HK |
822 | unsigned int i; |
823 | ||
824 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
825 | unsigned long offset = i * sizeof(u32); | |
826 | ||
827 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
828 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
829 | pdata->prv_reg_ctx[i], offset); | |
830 | } | |
831 | } | |
832 | ||
833 | /** | |
834 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
835 | * @dev: LPSS device | |
cb39dcdd | 836 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
837 | * |
838 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
839 | */ | |
cb39dcdd AS |
840 | static void acpi_lpss_restore_ctx(struct device *dev, |
841 | struct lpss_private_data *pdata) | |
c78b0830 | 842 | { |
c78b0830 HK |
843 | unsigned int i; |
844 | ||
02b98540 AS |
845 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
846 | unsigned long offset = i * sizeof(u32); | |
847 | ||
848 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
849 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
850 | pdata->prv_reg_ctx[i], offset); | |
851 | } | |
852 | } | |
853 | ||
854 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
855 | { | |
c78b0830 HK |
856 | /* |
857 | * The following delay is needed or the subsequent write operations may | |
858 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
859 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 860 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 861 | */ |
b00855ae SK |
862 | unsigned int delay = 10; /* default 10ms delay */ |
863 | ||
864 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
865 | delay = 0; | |
866 | ||
867 | msleep(delay); | |
c78b0830 HK |
868 | } |
869 | ||
c3a49cf3 AS |
870 | static int acpi_lpss_activate(struct device *dev) |
871 | { | |
872 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
873 | int ret; | |
874 | ||
63705c40 | 875 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
876 | if (ret) |
877 | return ret; | |
878 | ||
879 | acpi_lpss_d3_to_d0_delay(pdata); | |
880 | ||
881 | /* | |
882 | * This is called only on ->probe() stage where a device is either in | |
883 | * known state defined by BIOS or most likely powered off. Due to this | |
884 | * we have to deassert reset line to be sure that ->probe() will | |
885 | * recognize the device. | |
886 | */ | |
887 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
888 | lpss_deassert_reset(pdata); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static void acpi_lpss_dismiss(struct device *dev) | |
894 | { | |
cbe25ce3 | 895 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
896 | } |
897 | ||
eebb3e8d AS |
898 | /* IOSF SB for LPSS island */ |
899 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
900 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
901 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
902 | ||
903 | #define LPSS_IOSF_PMCSR 0x84 | |
904 | #define LPSS_PMCSR_D0 0 | |
905 | #define LPSS_PMCSR_D3hot 3 | |
906 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
907 | ||
908 | #define LPSS_IOSF_GPIODEF0 0x154 | |
909 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
910 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
911 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 912 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
913 | |
914 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 915 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
916 | |
917 | static void lpss_iosf_enter_d3_state(void) | |
918 | { | |
919 | u32 value1 = 0; | |
d132d6d5 | 920 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
921 | u32 value2 = LPSS_PMCSR_D3hot; |
922 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
923 | /* | |
924 | * PMC provides an information about actual status of the LPSS devices. | |
925 | * Here we read the values related to LPSS power island, i.e. LPSS | |
926 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
927 | */ | |
86b62e5c | 928 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
929 | int ret; |
930 | ||
931 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
932 | if (ret) | |
933 | return; | |
934 | ||
935 | mutex_lock(&lpss_iosf_mutex); | |
936 | ||
937 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
938 | if (ret) | |
939 | goto exit; | |
940 | ||
941 | /* | |
942 | * Get the status of entire LPSS power island per device basis. | |
943 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
944 | * are already in D3hot. | |
945 | */ | |
86b62e5c | 946 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
947 | if (pmc_status) |
948 | goto exit; | |
949 | ||
950 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
951 | LPSS_IOSF_PMCSR, value2, mask2); | |
952 | ||
953 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
954 | LPSS_IOSF_PMCSR, value2, mask2); | |
955 | ||
956 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
957 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
958 | |
959 | lpss_iosf_d3_entered = true; | |
960 | ||
eebb3e8d AS |
961 | exit: |
962 | mutex_unlock(&lpss_iosf_mutex); | |
963 | } | |
964 | ||
965 | static void lpss_iosf_exit_d3_state(void) | |
966 | { | |
d132d6d5 AS |
967 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
968 | LPSS_GPIODEF0_DMA_LLP; | |
969 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
970 | u32 value2 = LPSS_PMCSR_D0; |
971 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
972 | ||
973 | mutex_lock(&lpss_iosf_mutex); | |
974 | ||
12864ff8 RW |
975 | if (!lpss_iosf_d3_entered) |
976 | goto exit; | |
977 | ||
978 | lpss_iosf_d3_entered = false; | |
979 | ||
eebb3e8d AS |
980 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
981 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
982 | ||
983 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
984 | LPSS_IOSF_PMCSR, value2, mask2); | |
985 | ||
986 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
987 | LPSS_IOSF_PMCSR, value2, mask2); | |
988 | ||
12864ff8 | 989 | exit: |
eebb3e8d AS |
990 | mutex_unlock(&lpss_iosf_mutex); |
991 | } | |
992 | ||
12864ff8 | 993 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 994 | { |
cb39dcdd AS |
995 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
996 | int ret; | |
c78b0830 | 997 | |
cb39dcdd AS |
998 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
999 | acpi_lpss_save_ctx(dev, pdata); | |
1000 | ||
a192aa92 | 1001 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1002 | |
1003 | /* | |
1004 | * This call must be last in the sequence, otherwise PMC will return | |
1005 | * wrong status for devices being about to be powered off. See | |
1006 | * lpss_iosf_enter_d3_state() for further information. | |
1007 | */ | |
12864ff8 | 1008 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1009 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1010 | lpss_iosf_enter_d3_state(); |
1011 | ||
1012 | return ret; | |
c78b0830 HK |
1013 | } |
1014 | ||
12864ff8 | 1015 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1016 | { |
cb39dcdd AS |
1017 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1018 | int ret; | |
c78b0830 | 1019 | |
eebb3e8d AS |
1020 | /* |
1021 | * This call is kept first to be in symmetry with | |
1022 | * acpi_lpss_runtime_suspend() one. | |
1023 | */ | |
12864ff8 | 1024 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1025 | lpss_iosf_exit_d3_state(); |
1026 | ||
63705c40 | 1027 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1028 | if (ret) |
1029 | return ret; | |
1030 | ||
02b98540 AS |
1031 | acpi_lpss_d3_to_d0_delay(pdata); |
1032 | ||
cb39dcdd AS |
1033 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1034 | acpi_lpss_restore_ctx(dev, pdata); | |
1035 | ||
a192aa92 RW |
1036 | return 0; |
1037 | } | |
1038 | ||
1039 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1040 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1041 | { |
05087360 RW |
1042 | int ret; |
1043 | ||
1044 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
1045 | return 0; | |
a192aa92 | 1046 | |
05087360 | 1047 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1048 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1049 | } |
1050 | ||
48402cee HG |
1051 | static int acpi_lpss_suspend_late(struct device *dev) |
1052 | { | |
1053 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1054 | ||
1055 | if (pdata->dev_desc->resume_from_noirq) | |
1056 | return 0; | |
1057 | ||
1058 | return acpi_lpss_do_suspend_late(dev); | |
1059 | } | |
1060 | ||
1061 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1062 | { | |
1063 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1064 | int ret; | |
1065 | ||
1066 | if (pdata->dev_desc->resume_from_noirq) { | |
1067 | ret = acpi_lpss_do_suspend_late(dev); | |
1068 | if (ret) | |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | return acpi_subsys_suspend_noirq(dev); | |
1073 | } | |
1074 | ||
1075 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1076 | { |
12864ff8 | 1077 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1078 | |
1079 | return ret ? ret : pm_generic_resume_early(dev); | |
1080 | } | |
48402cee HG |
1081 | |
1082 | static int acpi_lpss_resume_early(struct device *dev) | |
1083 | { | |
1084 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1085 | ||
1086 | if (pdata->dev_desc->resume_from_noirq) | |
1087 | return 0; | |
1088 | ||
1089 | return acpi_lpss_do_resume_early(dev); | |
1090 | } | |
1091 | ||
1092 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1093 | { | |
1094 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1095 | int ret; | |
1096 | ||
1097 | ret = acpi_subsys_resume_noirq(dev); | |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
1101 | if (!dev_pm_may_skip_resume(dev) && pdata->dev_desc->resume_from_noirq) | |
1102 | ret = acpi_lpss_do_resume_early(dev); | |
1103 | ||
1104 | return ret; | |
1105 | } | |
1106 | ||
a192aa92 RW |
1107 | #endif /* CONFIG_PM_SLEEP */ |
1108 | ||
1109 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1110 | { | |
1111 | int ret = pm_generic_runtime_suspend(dev); | |
1112 | ||
1113 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1114 | } | |
1115 | ||
1116 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1117 | { | |
12864ff8 | 1118 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1119 | |
1120 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1121 | } |
c78b0830 HK |
1122 | #endif /* CONFIG_PM */ |
1123 | ||
1124 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1125 | #ifdef CONFIG_PM |
1126 | .activate = acpi_lpss_activate, | |
1127 | .dismiss = acpi_lpss_dismiss, | |
1128 | #endif | |
c78b0830 | 1129 | .ops = { |
5de21bb9 | 1130 | #ifdef CONFIG_PM |
c78b0830 | 1131 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1132 | .prepare = acpi_subsys_prepare, |
e4da817d | 1133 | .complete = acpi_subsys_complete, |
c78b0830 | 1134 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1135 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1136 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1137 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1138 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1139 | .freeze = acpi_subsys_freeze, |
05087360 RW |
1140 | .freeze_late = acpi_subsys_freeze_late, |
1141 | .freeze_noirq = acpi_subsys_freeze_noirq, | |
1142 | .thaw_noirq = acpi_subsys_thaw_noirq, | |
c78b0830 | 1143 | .poweroff = acpi_subsys_suspend, |
f4168b61 | 1144 | .poweroff_late = acpi_lpss_suspend_late, |
c8afd034 HG |
1145 | .poweroff_noirq = acpi_lpss_suspend_noirq, |
1146 | .restore_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1147 | .restore_early = acpi_lpss_resume_early, |
c78b0830 | 1148 | #endif |
c78b0830 HK |
1149 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1150 | .runtime_resume = acpi_lpss_runtime_resume, | |
1151 | #endif | |
1152 | }, | |
1153 | }; | |
1154 | ||
2e0f8822 RW |
1155 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1156 | unsigned long action, void *data) | |
1157 | { | |
1158 | struct platform_device *pdev = to_platform_device(data); | |
1159 | struct lpss_private_data *pdata; | |
1160 | struct acpi_device *adev; | |
1161 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1162 | |
1163 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1164 | if (!id || !id->driver_data) | |
1165 | return 0; | |
1166 | ||
1167 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1168 | return 0; | |
1169 | ||
1170 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1171 | if (!pdata) |
2e0f8822 RW |
1172 | return 0; |
1173 | ||
cb39dcdd AS |
1174 | if (pdata->mmio_base && |
1175 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1176 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1177 | return 0; | |
1178 | } | |
1179 | ||
c78b0830 | 1180 | switch (action) { |
de16d552 | 1181 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1182 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1183 | break; |
de16d552 | 1184 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1185 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1186 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1187 | break; |
1188 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1189 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1190 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1191 | return sysfs_create_group(&pdev->dev.kobj, |
1192 | &lpss_attr_group); | |
01ac170b | 1193 | break; |
c78b0830 | 1194 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1195 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1196 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1197 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1198 | break; |
c78b0830 HK |
1199 | default: |
1200 | break; | |
1201 | } | |
2e0f8822 | 1202 | |
c78b0830 | 1203 | return 0; |
2e0f8822 RW |
1204 | } |
1205 | ||
1206 | static struct notifier_block acpi_lpss_nb = { | |
1207 | .notifier_call = acpi_lpss_platform_notify, | |
1208 | }; | |
1209 | ||
1a8f8351 RW |
1210 | static void acpi_lpss_bind(struct device *dev) |
1211 | { | |
1212 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1213 | ||
ff8c1af5 | 1214 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1215 | return; |
1216 | ||
1217 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1218 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1219 | else | |
1220 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1221 | } | |
1222 | ||
1223 | static void acpi_lpss_unbind(struct device *dev) | |
1224 | { | |
1225 | dev->power.set_latency_tolerance = NULL; | |
1226 | } | |
1227 | ||
f58b082a RW |
1228 | static struct acpi_scan_handler lpss_handler = { |
1229 | .ids = acpi_lpss_device_ids, | |
1230 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1231 | .bind = acpi_lpss_bind, |
1232 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1233 | }; |
1234 | ||
1235 | void __init acpi_lpss_init(void) | |
1236 | { | |
eebb3e8d AS |
1237 | const struct x86_cpu_id *id; |
1238 | int ret; | |
1239 | ||
1240 | ret = lpt_clk_init(); | |
1241 | if (ret) | |
1242 | return; | |
1243 | ||
1244 | id = x86_match_cpu(lpss_cpu_ids); | |
1245 | if (id) | |
1246 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1247 | ||
1248 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1249 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1250 | } |
d6ddaaac RW |
1251 | |
1252 | #else | |
1253 | ||
1254 | static struct acpi_scan_handler lpss_handler = { | |
1255 | .ids = acpi_lpss_device_ids, | |
1256 | }; | |
1257 | ||
1258 | void __init acpi_lpss_init(void) | |
1259 | { | |
1260 | acpi_scan_add_handler(&lpss_handler); | |
1261 | } | |
1262 | ||
1263 | #endif /* CONFIG_X86_INTEL_LPSS */ |