Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/platform_data/clk-lpss.h> | |
2e0f8822 | 20 | #include <linux/pm_runtime.h> |
c78b0830 | 21 | #include <linux/delay.h> |
f58b082a RW |
22 | |
23 | #include "internal.h" | |
24 | ||
25 | ACPI_MODULE_NAME("acpi_lpss"); | |
26 | ||
d6ddaaac RW |
27 | #ifdef CONFIG_X86_INTEL_LPSS |
28 | ||
29 | #define LPSS_ADDR(desc) ((unsigned long)&desc) | |
30 | ||
f58b082a | 31 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
32 | #define LPSS_LTR_SIZE 0x18 |
33 | ||
34 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 35 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
36 | #define LPSS_RESETS 0x04 |
37 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
38 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
39 | #define LPSS_GENERAL 0x08 |
40 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 41 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
42 | #define LPSS_SW_LTR 0x10 |
43 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
44 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
45 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
46 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
47 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
48 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
49 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
50 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
51 | #define LPSS_TX_INT 0x20 |
52 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 53 | |
c78b0830 HK |
54 | #define LPSS_PRV_REG_COUNT 9 |
55 | ||
ff8c1af5 HK |
56 | /* LPSS Flags */ |
57 | #define LPSS_CLK BIT(0) | |
58 | #define LPSS_CLK_GATE BIT(1) | |
59 | #define LPSS_CLK_DIVIDER BIT(2) | |
60 | #define LPSS_LTR BIT(3) | |
61 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 62 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 63 | |
06d86415 | 64 | struct lpss_private_data; |
f58b082a RW |
65 | |
66 | struct lpss_device_desc { | |
ff8c1af5 | 67 | unsigned int flags; |
fcf0789a | 68 | const char *clk_con_id; |
2e0f8822 | 69 | unsigned int prv_offset; |
958c4eb2 | 70 | size_t prv_size_override; |
06d86415 | 71 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
72 | }; |
73 | ||
b59cc200 | 74 | static struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 75 | .flags = LPSS_CLK, |
b59cc200 RW |
76 | }; |
77 | ||
f58b082a RW |
78 | struct lpss_private_data { |
79 | void __iomem *mmio_base; | |
80 | resource_size_t mmio_size; | |
03f09f73 | 81 | unsigned int fixed_clk_rate; |
f58b082a RW |
82 | struct clk *clk; |
83 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 84 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
85 | }; |
86 | ||
1f47a77c HK |
87 | /* UART Component Parameter Register */ |
88 | #define LPSS_UART_CPR 0xF4 | |
89 | #define LPSS_UART_CPR_AFCE BIT(4) | |
90 | ||
06d86415 HK |
91 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
92 | { | |
088f1fd2 | 93 | unsigned int offset; |
1f47a77c | 94 | u32 val; |
06d86415 | 95 | |
088f1fd2 | 96 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
97 | val = readl(pdata->mmio_base + offset); |
98 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
99 | ||
100 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
101 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
102 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
103 | val = readl(pdata->mmio_base + offset); | |
104 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
105 | writel(val, pdata->mmio_base + offset); | |
106 | } | |
06d86415 HK |
107 | } |
108 | ||
3095794a | 109 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
110 | { |
111 | unsigned int offset; | |
112 | u32 val; | |
113 | ||
114 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
115 | val = readl(pdata->mmio_base + offset); | |
116 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
117 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
118 | } |
119 | ||
120 | #define LPSS_I2C_ENABLE 0x6c | |
121 | ||
122 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
123 | { | |
124 | lpss_deassert_reset(pdata); | |
765bdd4e | 125 | |
03f09f73 HK |
126 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
127 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
128 | |
129 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 130 | } |
43218a1b | 131 | |
b2687cd7 | 132 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 133 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 134 | .prv_offset = 0x800, |
ed3a872e HK |
135 | }; |
136 | ||
b2687cd7 | 137 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 138 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 139 | .prv_offset = 0x800, |
2e0f8822 RW |
140 | }; |
141 | ||
b2687cd7 | 142 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 143 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 144 | .clk_con_id = "baudclk", |
06d86415 | 145 | .prv_offset = 0x800, |
06d86415 | 146 | .setup = lpss_uart_setup, |
2e0f8822 RW |
147 | }; |
148 | ||
b2687cd7 | 149 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 150 | .flags = LPSS_LTR, |
2e0f8822 | 151 | .prv_offset = 0x1000, |
958c4eb2 | 152 | .prv_size_override = 0x1018, |
e1c74817 CCE |
153 | }; |
154 | ||
b2687cd7 | 155 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 156 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
157 | }; |
158 | ||
b00855ae SK |
159 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
160 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
161 | }; | |
162 | ||
b2687cd7 | 163 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 164 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 165 | .clk_con_id = "baudclk", |
f6272170 | 166 | .prv_offset = 0x800, |
06d86415 | 167 | .setup = lpss_uart_setup, |
f6272170 MW |
168 | }; |
169 | ||
b00855ae SK |
170 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
171 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
172 | | LPSS_NO_D3_DELAY, | |
173 | .clk_con_id = "baudclk", | |
174 | .prv_offset = 0x800, | |
175 | .setup = lpss_uart_setup, | |
176 | }; | |
177 | ||
b2687cd7 | 178 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 179 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 180 | .prv_offset = 0x400, |
f6272170 MW |
181 | }; |
182 | ||
b2687cd7 | 183 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 184 | .flags = LPSS_CLK, |
f6272170 MW |
185 | }; |
186 | ||
b2687cd7 | 187 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 188 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 189 | .prv_offset = 0x800, |
03f09f73 | 190 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
191 | }; |
192 | ||
b00855ae SK |
193 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
194 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
195 | .prv_offset = 0x800, | |
196 | .setup = byt_i2c_setup, | |
197 | }; | |
198 | ||
3095794a | 199 | static struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
200 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
201 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
202 | .prv_offset = 0x400, |
203 | .setup = lpss_deassert_reset, | |
204 | }; | |
205 | ||
d6ddaaac RW |
206 | #else |
207 | ||
208 | #define LPSS_ADDR(desc) (0UL) | |
209 | ||
210 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
211 | ||
f58b082a | 212 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 213 | /* Generic LPSS devices */ |
d6ddaaac | 214 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 215 | |
f58b082a | 216 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
217 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
218 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
219 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
220 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
221 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
222 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
223 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
224 | { "INT33C7", }, |
225 | ||
f6272170 | 226 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
227 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
228 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
229 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
230 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
231 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 232 | { "INT33B2", }, |
20482d32 | 233 | { "INT33FC", }, |
f6272170 | 234 | |
1bfbd8eb | 235 | /* Braswell LPSS devices */ |
b00855ae SK |
236 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
237 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 238 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 239 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 240 | |
b00855ae | 241 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
242 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
243 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
244 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
245 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
246 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
247 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
248 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
249 | { "INT3437", }, |
250 | ||
ff8c1af5 HK |
251 | /* Wildcat Point LPSS devices */ |
252 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 253 | |
f58b082a RW |
254 | { } |
255 | }; | |
256 | ||
d6ddaaac RW |
257 | #ifdef CONFIG_X86_INTEL_LPSS |
258 | ||
f58b082a RW |
259 | static int is_memory(struct acpi_resource *res, void *not_used) |
260 | { | |
261 | struct resource r; | |
262 | return !acpi_dev_resource_memory(res, &r); | |
263 | } | |
264 | ||
265 | /* LPSS main clock device. */ | |
266 | static struct platform_device *lpss_clk_dev; | |
267 | ||
268 | static inline void lpt_register_clock_device(void) | |
269 | { | |
270 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
271 | } | |
272 | ||
273 | static int register_device_clock(struct acpi_device *adev, | |
274 | struct lpss_private_data *pdata) | |
275 | { | |
276 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 277 | const char *devname = dev_name(&adev->dev); |
f6272170 | 278 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 279 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
280 | const char *parent, *clk_name; |
281 | void __iomem *prv_base; | |
f58b082a RW |
282 | |
283 | if (!lpss_clk_dev) | |
284 | lpt_register_clock_device(); | |
285 | ||
b59cc200 RW |
286 | clk_data = platform_get_drvdata(lpss_clk_dev); |
287 | if (!clk_data) | |
288 | return -ENODEV; | |
b0d00f8b | 289 | clk = clk_data->clk; |
b59cc200 RW |
290 | |
291 | if (!pdata->mmio_base | |
2e0f8822 | 292 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
293 | return -ENODATA; |
294 | ||
f6272170 | 295 | parent = clk_data->name; |
ed3a872e | 296 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 297 | |
03f09f73 HK |
298 | if (pdata->fixed_clk_rate) { |
299 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
300 | pdata->fixed_clk_rate); | |
301 | goto out; | |
f6272170 MW |
302 | } |
303 | ||
ff8c1af5 | 304 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
305 | clk = clk_register_gate(NULL, devname, parent, 0, |
306 | prv_base, 0, 0, NULL); | |
307 | parent = devname; | |
308 | } | |
309 | ||
ff8c1af5 | 310 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
311 | /* Prevent division by zero */ |
312 | if (!readl(prv_base)) | |
313 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
314 | ||
315 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
316 | if (!clk_name) | |
317 | return -ENOMEM; | |
318 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
319 | 0, prv_base, | |
320 | 1, 15, 16, 15, 0, NULL); | |
321 | parent = clk_name; | |
322 | ||
323 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
324 | if (!clk_name) { | |
325 | kfree(parent); | |
326 | return -ENOMEM; | |
327 | } | |
328 | clk = clk_register_gate(NULL, clk_name, parent, | |
329 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
330 | prv_base, 31, 0, NULL); | |
331 | kfree(parent); | |
332 | kfree(clk_name); | |
f6272170 | 333 | } |
03f09f73 | 334 | out: |
f6272170 MW |
335 | if (IS_ERR(clk)) |
336 | return PTR_ERR(clk); | |
f58b082a | 337 | |
ed3a872e | 338 | pdata->clk = clk; |
fcf0789a | 339 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
340 | return 0; |
341 | } | |
342 | ||
343 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
344 | const struct acpi_device_id *id) | |
345 | { | |
b2687cd7 | 346 | const struct lpss_device_desc *dev_desc; |
f58b082a | 347 | struct lpss_private_data *pdata; |
90e97820 | 348 | struct resource_entry *rentry; |
f58b082a | 349 | struct list_head resource_list; |
8ce62f85 | 350 | struct platform_device *pdev; |
f58b082a RW |
351 | int ret; |
352 | ||
b2687cd7 | 353 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 RW |
354 | if (!dev_desc) { |
355 | pdev = acpi_create_platform_device(adev); | |
356 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
357 | } | |
f58b082a RW |
358 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
359 | if (!pdata) | |
360 | return -ENOMEM; | |
361 | ||
362 | INIT_LIST_HEAD(&resource_list); | |
363 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
364 | if (ret < 0) | |
365 | goto err_out; | |
366 | ||
367 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 368 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
369 | if (dev_desc->prv_size_override) |
370 | pdata->mmio_size = dev_desc->prv_size_override; | |
371 | else | |
90e97820 JL |
372 | pdata->mmio_size = resource_size(rentry->res); |
373 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 374 | pdata->mmio_size); |
f58b082a RW |
375 | break; |
376 | } | |
377 | ||
378 | acpi_dev_free_resource_list(&resource_list); | |
379 | ||
d3e13ff3 RW |
380 | if (!pdata->mmio_base) { |
381 | ret = -ENOMEM; | |
382 | goto err_out; | |
383 | } | |
384 | ||
af65cfe9 MW |
385 | pdata->dev_desc = dev_desc; |
386 | ||
03f09f73 HK |
387 | if (dev_desc->setup) |
388 | dev_desc->setup(pdata); | |
389 | ||
ff8c1af5 | 390 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
391 | ret = register_device_clock(adev, pdata); |
392 | if (ret) { | |
b9e95fc6 RW |
393 | /* Skip the device, but continue the namespace scan. */ |
394 | ret = 0; | |
395 | goto err_out; | |
f58b082a RW |
396 | } |
397 | } | |
398 | ||
b9e95fc6 RW |
399 | /* |
400 | * This works around a known issue in ACPI tables where LPSS devices | |
401 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
402 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
403 | */ | |
404 | ret = acpi_device_fix_up_power(adev); | |
405 | if (ret) { | |
406 | /* Skip the device, but continue the namespace scan. */ | |
407 | ret = 0; | |
408 | goto err_out; | |
409 | } | |
410 | ||
f58b082a | 411 | adev->driver_data = pdata; |
8ce62f85 RW |
412 | pdev = acpi_create_platform_device(adev); |
413 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
414 | return 1; |
415 | } | |
f58b082a | 416 | |
8ce62f85 | 417 | ret = PTR_ERR(pdev); |
f58b082a RW |
418 | adev->driver_data = NULL; |
419 | ||
420 | err_out: | |
421 | kfree(pdata); | |
422 | return ret; | |
423 | } | |
424 | ||
1a8f8351 RW |
425 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
426 | { | |
427 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
428 | } | |
429 | ||
430 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
431 | unsigned int reg) | |
432 | { | |
433 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
434 | } | |
435 | ||
2e0f8822 RW |
436 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
437 | { | |
438 | struct acpi_device *adev; | |
439 | struct lpss_private_data *pdata; | |
440 | unsigned long flags; | |
441 | int ret; | |
442 | ||
443 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
444 | if (WARN_ON(ret)) | |
445 | return ret; | |
446 | ||
447 | spin_lock_irqsave(&dev->power.lock, flags); | |
448 | if (pm_runtime_suspended(dev)) { | |
449 | ret = -EAGAIN; | |
450 | goto out; | |
451 | } | |
452 | pdata = acpi_driver_data(adev); | |
453 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
454 | ret = -ENODEV; | |
455 | goto out; | |
456 | } | |
1a8f8351 | 457 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
458 | |
459 | out: | |
460 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
461 | return ret; | |
462 | } | |
463 | ||
464 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
465 | char *buf) | |
466 | { | |
467 | u32 ltr_value = 0; | |
468 | unsigned int reg; | |
469 | int ret; | |
470 | ||
471 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
472 | ret = lpss_reg_read(dev, reg, <r_value); | |
473 | if (ret) | |
474 | return ret; | |
475 | ||
476 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
477 | } | |
478 | ||
479 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
480 | struct device_attribute *attr, char *buf) | |
481 | { | |
482 | u32 ltr_mode = 0; | |
483 | char *outstr; | |
484 | int ret; | |
485 | ||
486 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
487 | if (ret) | |
488 | return ret; | |
489 | ||
490 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
491 | return sprintf(buf, "%s\n", outstr); | |
492 | } | |
493 | ||
494 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
495 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
496 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
497 | ||
498 | static struct attribute *lpss_attrs[] = { | |
499 | &dev_attr_auto_ltr.attr, | |
500 | &dev_attr_sw_ltr.attr, | |
501 | &dev_attr_ltr_mode.attr, | |
502 | NULL, | |
503 | }; | |
504 | ||
505 | static struct attribute_group lpss_attr_group = { | |
506 | .attrs = lpss_attrs, | |
507 | .name = "lpss_ltr", | |
508 | }; | |
509 | ||
1a8f8351 RW |
510 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
511 | { | |
512 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
513 | u32 ltr_mode, ltr_val; | |
514 | ||
515 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
516 | if (val < 0) { | |
517 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
518 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
519 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
520 | } | |
521 | return; | |
522 | } | |
523 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
524 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
525 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
526 | val = LPSS_LTR_MAX_VAL; | |
527 | } else if (val > LPSS_LTR_MAX_VAL) { | |
528 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
529 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
530 | } else { | |
531 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
532 | } | |
533 | ltr_val |= val; | |
534 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
535 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
536 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
537 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
538 | } | |
539 | } | |
540 | ||
c78b0830 HK |
541 | #ifdef CONFIG_PM |
542 | /** | |
543 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
544 | * @dev: LPSS device | |
cb39dcdd | 545 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
546 | * |
547 | * Most LPSS devices have private registers which may loose their context when | |
548 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
549 | * prv_reg_ctx array. | |
550 | */ | |
cb39dcdd AS |
551 | static void acpi_lpss_save_ctx(struct device *dev, |
552 | struct lpss_private_data *pdata) | |
c78b0830 | 553 | { |
c78b0830 HK |
554 | unsigned int i; |
555 | ||
556 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
557 | unsigned long offset = i * sizeof(u32); | |
558 | ||
559 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
560 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
561 | pdata->prv_reg_ctx[i], offset); | |
562 | } | |
563 | } | |
564 | ||
565 | /** | |
566 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
567 | * @dev: LPSS device | |
cb39dcdd | 568 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
569 | * |
570 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
571 | */ | |
cb39dcdd AS |
572 | static void acpi_lpss_restore_ctx(struct device *dev, |
573 | struct lpss_private_data *pdata) | |
c78b0830 | 574 | { |
c78b0830 HK |
575 | unsigned int i; |
576 | ||
577 | /* | |
578 | * The following delay is needed or the subsequent write operations may | |
579 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
580 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 581 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 582 | */ |
b00855ae SK |
583 | unsigned int delay = 10; /* default 10ms delay */ |
584 | ||
585 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
586 | delay = 0; | |
587 | ||
588 | msleep(delay); | |
c78b0830 HK |
589 | |
590 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
591 | unsigned long offset = i * sizeof(u32); | |
592 | ||
593 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
594 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
595 | pdata->prv_reg_ctx[i], offset); | |
596 | } | |
597 | } | |
598 | ||
599 | #ifdef CONFIG_PM_SLEEP | |
600 | static int acpi_lpss_suspend_late(struct device *dev) | |
601 | { | |
cb39dcdd AS |
602 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
603 | int ret; | |
c78b0830 | 604 | |
cb39dcdd | 605 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
606 | if (ret) |
607 | return ret; | |
608 | ||
cb39dcdd AS |
609 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
610 | acpi_lpss_save_ctx(dev, pdata); | |
611 | ||
c78b0830 HK |
612 | return acpi_dev_suspend_late(dev); |
613 | } | |
614 | ||
f4168b61 | 615 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 616 | { |
cb39dcdd AS |
617 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
618 | int ret; | |
c78b0830 | 619 | |
cb39dcdd | 620 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
621 | if (ret) |
622 | return ret; | |
623 | ||
cb39dcdd AS |
624 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
625 | acpi_lpss_restore_ctx(dev, pdata); | |
626 | ||
c78b0830 HK |
627 | return pm_generic_resume_early(dev); |
628 | } | |
629 | #endif /* CONFIG_PM_SLEEP */ | |
630 | ||
c78b0830 HK |
631 | static int acpi_lpss_runtime_suspend(struct device *dev) |
632 | { | |
cb39dcdd AS |
633 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
634 | int ret; | |
c78b0830 | 635 | |
cb39dcdd | 636 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
637 | if (ret) |
638 | return ret; | |
639 | ||
cb39dcdd AS |
640 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
641 | acpi_lpss_save_ctx(dev, pdata); | |
642 | ||
3df2da96 | 643 | return acpi_dev_runtime_suspend(dev); |
c78b0830 HK |
644 | } |
645 | ||
646 | static int acpi_lpss_runtime_resume(struct device *dev) | |
647 | { | |
cb39dcdd AS |
648 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
649 | int ret; | |
c78b0830 | 650 | |
cb39dcdd | 651 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
652 | if (ret) |
653 | return ret; | |
654 | ||
cb39dcdd AS |
655 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
656 | acpi_lpss_restore_ctx(dev, pdata); | |
657 | ||
c78b0830 HK |
658 | return pm_generic_runtime_resume(dev); |
659 | } | |
c78b0830 HK |
660 | #endif /* CONFIG_PM */ |
661 | ||
662 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
663 | .ops = { | |
5de21bb9 | 664 | #ifdef CONFIG_PM |
c78b0830 | 665 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 666 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 667 | .complete = pm_complete_with_resume_check, |
c78b0830 | 668 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
669 | .suspend_late = acpi_lpss_suspend_late, |
670 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
671 | .freeze = acpi_subsys_freeze, |
672 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
673 | .poweroff_late = acpi_lpss_suspend_late, |
674 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 675 | #endif |
c78b0830 HK |
676 | .runtime_suspend = acpi_lpss_runtime_suspend, |
677 | .runtime_resume = acpi_lpss_runtime_resume, | |
678 | #endif | |
679 | }, | |
680 | }; | |
681 | ||
2e0f8822 RW |
682 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
683 | unsigned long action, void *data) | |
684 | { | |
685 | struct platform_device *pdev = to_platform_device(data); | |
686 | struct lpss_private_data *pdata; | |
687 | struct acpi_device *adev; | |
688 | const struct acpi_device_id *id; | |
2e0f8822 RW |
689 | |
690 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
691 | if (!id || !id->driver_data) | |
692 | return 0; | |
693 | ||
694 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
695 | return 0; | |
696 | ||
697 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 698 | if (!pdata) |
2e0f8822 RW |
699 | return 0; |
700 | ||
cb39dcdd AS |
701 | if (pdata->mmio_base && |
702 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
703 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
704 | return 0; | |
705 | } | |
706 | ||
c78b0830 | 707 | switch (action) { |
b5f88dd1 | 708 | case BUS_NOTIFY_BOUND_DRIVER: |
01ac170b | 709 | pdev->dev.pm_domain = &acpi_lpss_pm_domain; |
b5f88dd1 AS |
710 | break; |
711 | case BUS_NOTIFY_UNBOUND_DRIVER: | |
712 | pdev->dev.pm_domain = NULL; | |
713 | break; | |
714 | case BUS_NOTIFY_ADD_DEVICE: | |
ff8c1af5 | 715 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
716 | return sysfs_create_group(&pdev->dev.kobj, |
717 | &lpss_attr_group); | |
01ac170b | 718 | break; |
c78b0830 | 719 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 720 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 721 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
01ac170b | 722 | break; |
c78b0830 HK |
723 | default: |
724 | break; | |
725 | } | |
2e0f8822 | 726 | |
c78b0830 | 727 | return 0; |
2e0f8822 RW |
728 | } |
729 | ||
730 | static struct notifier_block acpi_lpss_nb = { | |
731 | .notifier_call = acpi_lpss_platform_notify, | |
732 | }; | |
733 | ||
1a8f8351 RW |
734 | static void acpi_lpss_bind(struct device *dev) |
735 | { | |
736 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
737 | ||
ff8c1af5 | 738 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
739 | return; |
740 | ||
741 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
742 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
743 | else | |
744 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
745 | } | |
746 | ||
747 | static void acpi_lpss_unbind(struct device *dev) | |
748 | { | |
749 | dev->power.set_latency_tolerance = NULL; | |
750 | } | |
751 | ||
f58b082a RW |
752 | static struct acpi_scan_handler lpss_handler = { |
753 | .ids = acpi_lpss_device_ids, | |
754 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
755 | .bind = acpi_lpss_bind, |
756 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
757 | }; |
758 | ||
759 | void __init acpi_lpss_init(void) | |
760 | { | |
2e0f8822 RW |
761 | if (!lpt_clk_init()) { |
762 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
f58b082a | 763 | acpi_scan_add_handler(&lpss_handler); |
2e0f8822 | 764 | } |
f58b082a | 765 | } |
d6ddaaac RW |
766 | |
767 | #else | |
768 | ||
769 | static struct acpi_scan_handler lpss_handler = { | |
770 | .ids = acpi_lpss_device_ids, | |
771 | }; | |
772 | ||
773 | void __init acpi_lpss_init(void) | |
774 | { | |
775 | acpi_scan_add_handler(&lpss_handler); | |
776 | } | |
777 | ||
778 | #endif /* CONFIG_X86_INTEL_LPSS */ |