Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
2e0f8822 | 21 | #include <linux/pm_runtime.h> |
c78b0830 | 22 | #include <linux/delay.h> |
f58b082a RW |
23 | |
24 | #include "internal.h" | |
25 | ||
26 | ACPI_MODULE_NAME("acpi_lpss"); | |
27 | ||
d6ddaaac RW |
28 | #ifdef CONFIG_X86_INTEL_LPSS |
29 | ||
eebb3e8d AS |
30 | #include <asm/cpu_device_id.h> |
31 | #include <asm/iosf_mbi.h> | |
32 | #include <asm/pmc_atom.h> | |
33 | ||
d6ddaaac RW |
34 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
35 | ||
f58b082a | 36 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
37 | #define LPSS_LTR_SIZE 0x18 |
38 | ||
39 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 40 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
41 | #define LPSS_RESETS 0x04 |
42 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
43 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
44 | #define LPSS_GENERAL 0x08 |
45 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 46 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
47 | #define LPSS_SW_LTR 0x10 |
48 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
49 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
50 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
51 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
52 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
53 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
54 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
55 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
56 | #define LPSS_TX_INT 0x20 |
57 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 58 | |
c78b0830 HK |
59 | #define LPSS_PRV_REG_COUNT 9 |
60 | ||
ff8c1af5 HK |
61 | /* LPSS Flags */ |
62 | #define LPSS_CLK BIT(0) | |
63 | #define LPSS_CLK_GATE BIT(1) | |
64 | #define LPSS_CLK_DIVIDER BIT(2) | |
65 | #define LPSS_LTR BIT(3) | |
66 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 67 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 68 | |
06d86415 | 69 | struct lpss_private_data; |
f58b082a RW |
70 | |
71 | struct lpss_device_desc { | |
ff8c1af5 | 72 | unsigned int flags; |
fcf0789a | 73 | const char *clk_con_id; |
2e0f8822 | 74 | unsigned int prv_offset; |
958c4eb2 | 75 | size_t prv_size_override; |
06d86415 | 76 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
77 | }; |
78 | ||
eebb3e8d | 79 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 80 | .flags = LPSS_CLK, |
b59cc200 RW |
81 | }; |
82 | ||
f58b082a RW |
83 | struct lpss_private_data { |
84 | void __iomem *mmio_base; | |
85 | resource_size_t mmio_size; | |
03f09f73 | 86 | unsigned int fixed_clk_rate; |
f58b082a RW |
87 | struct clk *clk; |
88 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 89 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
90 | }; |
91 | ||
eebb3e8d AS |
92 | /* LPSS run time quirks */ |
93 | static unsigned int lpss_quirks; | |
94 | ||
95 | /* | |
96 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
97 | * | |
fa9e93b1 | 98 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
99 | * it can be powered off automatically whenever the last LPSS device goes down. |
100 | * In case of no power any access to the DMA controller will hang the system. | |
101 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
102 | * well as on ASuS T100TA transformer. | |
103 | * | |
104 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
105 | * on whenever we have at least one other device in use. | |
106 | */ | |
107 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
108 | ||
1f47a77c HK |
109 | /* UART Component Parameter Register */ |
110 | #define LPSS_UART_CPR 0xF4 | |
111 | #define LPSS_UART_CPR_AFCE BIT(4) | |
112 | ||
06d86415 HK |
113 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
114 | { | |
088f1fd2 | 115 | unsigned int offset; |
1f47a77c | 116 | u32 val; |
06d86415 | 117 | |
088f1fd2 | 118 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
119 | val = readl(pdata->mmio_base + offset); |
120 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
121 | ||
122 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
123 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
124 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
125 | val = readl(pdata->mmio_base + offset); | |
126 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
127 | writel(val, pdata->mmio_base + offset); | |
128 | } | |
06d86415 HK |
129 | } |
130 | ||
3095794a | 131 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
132 | { |
133 | unsigned int offset; | |
134 | u32 val; | |
135 | ||
136 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
137 | val = readl(pdata->mmio_base + offset); | |
138 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
139 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
140 | } |
141 | ||
142 | #define LPSS_I2C_ENABLE 0x6c | |
143 | ||
144 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
145 | { | |
146 | lpss_deassert_reset(pdata); | |
765bdd4e | 147 | |
03f09f73 HK |
148 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
149 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
150 | |
151 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 152 | } |
43218a1b | 153 | |
b2687cd7 | 154 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 155 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 156 | .prv_offset = 0x800, |
ed3a872e HK |
157 | }; |
158 | ||
b2687cd7 | 159 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 160 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 161 | .prv_offset = 0x800, |
2e0f8822 RW |
162 | }; |
163 | ||
b2687cd7 | 164 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 165 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 166 | .clk_con_id = "baudclk", |
06d86415 | 167 | .prv_offset = 0x800, |
06d86415 | 168 | .setup = lpss_uart_setup, |
2e0f8822 RW |
169 | }; |
170 | ||
b2687cd7 | 171 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 172 | .flags = LPSS_LTR, |
2e0f8822 | 173 | .prv_offset = 0x1000, |
958c4eb2 | 174 | .prv_size_override = 0x1018, |
e1c74817 CCE |
175 | }; |
176 | ||
b2687cd7 | 177 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 178 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
179 | }; |
180 | ||
b00855ae SK |
181 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
182 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
183 | }; | |
184 | ||
b2687cd7 | 185 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 186 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 187 | .clk_con_id = "baudclk", |
f6272170 | 188 | .prv_offset = 0x800, |
06d86415 | 189 | .setup = lpss_uart_setup, |
f6272170 MW |
190 | }; |
191 | ||
b00855ae SK |
192 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
193 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
194 | | LPSS_NO_D3_DELAY, | |
195 | .clk_con_id = "baudclk", | |
196 | .prv_offset = 0x800, | |
197 | .setup = lpss_uart_setup, | |
198 | }; | |
199 | ||
b2687cd7 | 200 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 201 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 202 | .prv_offset = 0x400, |
f6272170 MW |
203 | }; |
204 | ||
b2687cd7 | 205 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 206 | .flags = LPSS_CLK, |
f6272170 MW |
207 | }; |
208 | ||
b2687cd7 | 209 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 210 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 211 | .prv_offset = 0x800, |
03f09f73 | 212 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
213 | }; |
214 | ||
b00855ae SK |
215 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
216 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
217 | .prv_offset = 0x800, | |
218 | .setup = byt_i2c_setup, | |
219 | }; | |
220 | ||
eebb3e8d | 221 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
222 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
223 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
224 | .prv_offset = 0x400, |
225 | .setup = lpss_deassert_reset, | |
226 | }; | |
227 | ||
eebb3e8d AS |
228 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
229 | ||
230 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
231 | ICPU(0x37), /* Valleyview, Bay Trail */ | |
232 | ICPU(0x4c), /* Braswell, Cherry Trail */ | |
233 | {} | |
234 | }; | |
235 | ||
d6ddaaac RW |
236 | #else |
237 | ||
238 | #define LPSS_ADDR(desc) (0UL) | |
239 | ||
240 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
241 | ||
f58b082a | 242 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 243 | /* Generic LPSS devices */ |
d6ddaaac | 244 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 245 | |
f58b082a | 246 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
247 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
248 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
249 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
250 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
251 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
252 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
253 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
254 | { "INT33C7", }, |
255 | ||
f6272170 | 256 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
257 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
258 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
259 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
260 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
261 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 262 | { "INT33B2", }, |
20482d32 | 263 | { "INT33FC", }, |
f6272170 | 264 | |
1bfbd8eb | 265 | /* Braswell LPSS devices */ |
b00855ae SK |
266 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
267 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 268 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 269 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 270 | |
b00855ae | 271 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
272 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
273 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
274 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
275 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
276 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
277 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
278 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
279 | { "INT3437", }, |
280 | ||
ff8c1af5 HK |
281 | /* Wildcat Point LPSS devices */ |
282 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 283 | |
f58b082a RW |
284 | { } |
285 | }; | |
286 | ||
d6ddaaac RW |
287 | #ifdef CONFIG_X86_INTEL_LPSS |
288 | ||
f58b082a RW |
289 | static int is_memory(struct acpi_resource *res, void *not_used) |
290 | { | |
291 | struct resource r; | |
292 | return !acpi_dev_resource_memory(res, &r); | |
293 | } | |
294 | ||
295 | /* LPSS main clock device. */ | |
296 | static struct platform_device *lpss_clk_dev; | |
297 | ||
298 | static inline void lpt_register_clock_device(void) | |
299 | { | |
300 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
301 | } | |
302 | ||
303 | static int register_device_clock(struct acpi_device *adev, | |
304 | struct lpss_private_data *pdata) | |
305 | { | |
306 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 307 | const char *devname = dev_name(&adev->dev); |
f6272170 | 308 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 309 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
310 | const char *parent, *clk_name; |
311 | void __iomem *prv_base; | |
f58b082a RW |
312 | |
313 | if (!lpss_clk_dev) | |
314 | lpt_register_clock_device(); | |
315 | ||
b59cc200 RW |
316 | clk_data = platform_get_drvdata(lpss_clk_dev); |
317 | if (!clk_data) | |
318 | return -ENODEV; | |
b0d00f8b | 319 | clk = clk_data->clk; |
b59cc200 RW |
320 | |
321 | if (!pdata->mmio_base | |
2e0f8822 | 322 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
323 | return -ENODATA; |
324 | ||
f6272170 | 325 | parent = clk_data->name; |
ed3a872e | 326 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 327 | |
03f09f73 HK |
328 | if (pdata->fixed_clk_rate) { |
329 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
330 | pdata->fixed_clk_rate); | |
331 | goto out; | |
f6272170 MW |
332 | } |
333 | ||
ff8c1af5 | 334 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
335 | clk = clk_register_gate(NULL, devname, parent, 0, |
336 | prv_base, 0, 0, NULL); | |
337 | parent = devname; | |
338 | } | |
339 | ||
ff8c1af5 | 340 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
341 | /* Prevent division by zero */ |
342 | if (!readl(prv_base)) | |
343 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
344 | ||
345 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
346 | if (!clk_name) | |
347 | return -ENOMEM; | |
348 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
349 | 0, prv_base, | |
350 | 1, 15, 16, 15, 0, NULL); | |
351 | parent = clk_name; | |
352 | ||
353 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
354 | if (!clk_name) { | |
355 | kfree(parent); | |
356 | return -ENOMEM; | |
357 | } | |
358 | clk = clk_register_gate(NULL, clk_name, parent, | |
359 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
360 | prv_base, 31, 0, NULL); | |
361 | kfree(parent); | |
362 | kfree(clk_name); | |
f6272170 | 363 | } |
03f09f73 | 364 | out: |
f6272170 MW |
365 | if (IS_ERR(clk)) |
366 | return PTR_ERR(clk); | |
f58b082a | 367 | |
ed3a872e | 368 | pdata->clk = clk; |
fcf0789a | 369 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
370 | return 0; |
371 | } | |
372 | ||
373 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
374 | const struct acpi_device_id *id) | |
375 | { | |
b2687cd7 | 376 | const struct lpss_device_desc *dev_desc; |
f58b082a | 377 | struct lpss_private_data *pdata; |
90e97820 | 378 | struct resource_entry *rentry; |
f58b082a | 379 | struct list_head resource_list; |
8ce62f85 | 380 | struct platform_device *pdev; |
f58b082a RW |
381 | int ret; |
382 | ||
b2687cd7 | 383 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 RW |
384 | if (!dev_desc) { |
385 | pdev = acpi_create_platform_device(adev); | |
386 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
387 | } | |
f58b082a RW |
388 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
389 | if (!pdata) | |
390 | return -ENOMEM; | |
391 | ||
392 | INIT_LIST_HEAD(&resource_list); | |
393 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
394 | if (ret < 0) | |
395 | goto err_out; | |
396 | ||
397 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 398 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
399 | if (dev_desc->prv_size_override) |
400 | pdata->mmio_size = dev_desc->prv_size_override; | |
401 | else | |
90e97820 JL |
402 | pdata->mmio_size = resource_size(rentry->res); |
403 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 404 | pdata->mmio_size); |
f58b082a RW |
405 | break; |
406 | } | |
407 | ||
408 | acpi_dev_free_resource_list(&resource_list); | |
409 | ||
d3e13ff3 RW |
410 | if (!pdata->mmio_base) { |
411 | ret = -ENOMEM; | |
412 | goto err_out; | |
413 | } | |
414 | ||
af65cfe9 MW |
415 | pdata->dev_desc = dev_desc; |
416 | ||
03f09f73 HK |
417 | if (dev_desc->setup) |
418 | dev_desc->setup(pdata); | |
419 | ||
ff8c1af5 | 420 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
421 | ret = register_device_clock(adev, pdata); |
422 | if (ret) { | |
b9e95fc6 RW |
423 | /* Skip the device, but continue the namespace scan. */ |
424 | ret = 0; | |
425 | goto err_out; | |
f58b082a RW |
426 | } |
427 | } | |
428 | ||
b9e95fc6 RW |
429 | /* |
430 | * This works around a known issue in ACPI tables where LPSS devices | |
431 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
432 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
433 | */ | |
434 | ret = acpi_device_fix_up_power(adev); | |
435 | if (ret) { | |
436 | /* Skip the device, but continue the namespace scan. */ | |
437 | ret = 0; | |
438 | goto err_out; | |
439 | } | |
440 | ||
f58b082a | 441 | adev->driver_data = pdata; |
8ce62f85 RW |
442 | pdev = acpi_create_platform_device(adev); |
443 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
444 | return 1; |
445 | } | |
f58b082a | 446 | |
8ce62f85 | 447 | ret = PTR_ERR(pdev); |
f58b082a RW |
448 | adev->driver_data = NULL; |
449 | ||
450 | err_out: | |
451 | kfree(pdata); | |
452 | return ret; | |
453 | } | |
454 | ||
1a8f8351 RW |
455 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
456 | { | |
457 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
458 | } | |
459 | ||
460 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
461 | unsigned int reg) | |
462 | { | |
463 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
464 | } | |
465 | ||
2e0f8822 RW |
466 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
467 | { | |
468 | struct acpi_device *adev; | |
469 | struct lpss_private_data *pdata; | |
470 | unsigned long flags; | |
471 | int ret; | |
472 | ||
473 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
474 | if (WARN_ON(ret)) | |
475 | return ret; | |
476 | ||
477 | spin_lock_irqsave(&dev->power.lock, flags); | |
478 | if (pm_runtime_suspended(dev)) { | |
479 | ret = -EAGAIN; | |
480 | goto out; | |
481 | } | |
482 | pdata = acpi_driver_data(adev); | |
483 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
484 | ret = -ENODEV; | |
485 | goto out; | |
486 | } | |
1a8f8351 | 487 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
488 | |
489 | out: | |
490 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
491 | return ret; | |
492 | } | |
493 | ||
494 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
495 | char *buf) | |
496 | { | |
497 | u32 ltr_value = 0; | |
498 | unsigned int reg; | |
499 | int ret; | |
500 | ||
501 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
502 | ret = lpss_reg_read(dev, reg, <r_value); | |
503 | if (ret) | |
504 | return ret; | |
505 | ||
506 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
507 | } | |
508 | ||
509 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
510 | struct device_attribute *attr, char *buf) | |
511 | { | |
512 | u32 ltr_mode = 0; | |
513 | char *outstr; | |
514 | int ret; | |
515 | ||
516 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
517 | if (ret) | |
518 | return ret; | |
519 | ||
520 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
521 | return sprintf(buf, "%s\n", outstr); | |
522 | } | |
523 | ||
524 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
525 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
526 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
527 | ||
528 | static struct attribute *lpss_attrs[] = { | |
529 | &dev_attr_auto_ltr.attr, | |
530 | &dev_attr_sw_ltr.attr, | |
531 | &dev_attr_ltr_mode.attr, | |
532 | NULL, | |
533 | }; | |
534 | ||
535 | static struct attribute_group lpss_attr_group = { | |
536 | .attrs = lpss_attrs, | |
537 | .name = "lpss_ltr", | |
538 | }; | |
539 | ||
1a8f8351 RW |
540 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
541 | { | |
542 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
543 | u32 ltr_mode, ltr_val; | |
544 | ||
545 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
546 | if (val < 0) { | |
547 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
548 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
549 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
550 | } | |
551 | return; | |
552 | } | |
553 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
554 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
555 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
556 | val = LPSS_LTR_MAX_VAL; | |
557 | } else if (val > LPSS_LTR_MAX_VAL) { | |
558 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
559 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
560 | } else { | |
561 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
562 | } | |
563 | ltr_val |= val; | |
564 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
565 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
566 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
567 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
568 | } | |
569 | } | |
570 | ||
c78b0830 HK |
571 | #ifdef CONFIG_PM |
572 | /** | |
573 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
574 | * @dev: LPSS device | |
cb39dcdd | 575 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
576 | * |
577 | * Most LPSS devices have private registers which may loose their context when | |
578 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
579 | * prv_reg_ctx array. | |
580 | */ | |
cb39dcdd AS |
581 | static void acpi_lpss_save_ctx(struct device *dev, |
582 | struct lpss_private_data *pdata) | |
c78b0830 | 583 | { |
c78b0830 HK |
584 | unsigned int i; |
585 | ||
586 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
587 | unsigned long offset = i * sizeof(u32); | |
588 | ||
589 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
590 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
591 | pdata->prv_reg_ctx[i], offset); | |
592 | } | |
593 | } | |
594 | ||
595 | /** | |
596 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
597 | * @dev: LPSS device | |
cb39dcdd | 598 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
599 | * |
600 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
601 | */ | |
cb39dcdd AS |
602 | static void acpi_lpss_restore_ctx(struct device *dev, |
603 | struct lpss_private_data *pdata) | |
c78b0830 | 604 | { |
c78b0830 HK |
605 | unsigned int i; |
606 | ||
02b98540 AS |
607 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
608 | unsigned long offset = i * sizeof(u32); | |
609 | ||
610 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
611 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
612 | pdata->prv_reg_ctx[i], offset); | |
613 | } | |
614 | } | |
615 | ||
616 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
617 | { | |
c78b0830 HK |
618 | /* |
619 | * The following delay is needed or the subsequent write operations may | |
620 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
621 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 622 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 623 | */ |
b00855ae SK |
624 | unsigned int delay = 10; /* default 10ms delay */ |
625 | ||
626 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
627 | delay = 0; | |
628 | ||
629 | msleep(delay); | |
c78b0830 HK |
630 | } |
631 | ||
c3a49cf3 AS |
632 | static int acpi_lpss_activate(struct device *dev) |
633 | { | |
634 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
635 | int ret; | |
636 | ||
637 | ret = acpi_dev_runtime_resume(dev); | |
638 | if (ret) | |
639 | return ret; | |
640 | ||
641 | acpi_lpss_d3_to_d0_delay(pdata); | |
642 | ||
643 | /* | |
644 | * This is called only on ->probe() stage where a device is either in | |
645 | * known state defined by BIOS or most likely powered off. Due to this | |
646 | * we have to deassert reset line to be sure that ->probe() will | |
647 | * recognize the device. | |
648 | */ | |
649 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
650 | lpss_deassert_reset(pdata); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | static void acpi_lpss_dismiss(struct device *dev) | |
656 | { | |
657 | acpi_dev_runtime_suspend(dev); | |
658 | } | |
659 | ||
c78b0830 HK |
660 | #ifdef CONFIG_PM_SLEEP |
661 | static int acpi_lpss_suspend_late(struct device *dev) | |
662 | { | |
cb39dcdd AS |
663 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
664 | int ret; | |
c78b0830 | 665 | |
cb39dcdd | 666 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
667 | if (ret) |
668 | return ret; | |
669 | ||
cb39dcdd AS |
670 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
671 | acpi_lpss_save_ctx(dev, pdata); | |
672 | ||
c78b0830 HK |
673 | return acpi_dev_suspend_late(dev); |
674 | } | |
675 | ||
f4168b61 | 676 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 677 | { |
cb39dcdd AS |
678 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
679 | int ret; | |
c78b0830 | 680 | |
cb39dcdd | 681 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
682 | if (ret) |
683 | return ret; | |
684 | ||
02b98540 AS |
685 | acpi_lpss_d3_to_d0_delay(pdata); |
686 | ||
cb39dcdd AS |
687 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
688 | acpi_lpss_restore_ctx(dev, pdata); | |
689 | ||
c78b0830 HK |
690 | return pm_generic_resume_early(dev); |
691 | } | |
692 | #endif /* CONFIG_PM_SLEEP */ | |
693 | ||
eebb3e8d AS |
694 | /* IOSF SB for LPSS island */ |
695 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
696 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
697 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
698 | ||
699 | #define LPSS_IOSF_PMCSR 0x84 | |
700 | #define LPSS_PMCSR_D0 0 | |
701 | #define LPSS_PMCSR_D3hot 3 | |
702 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
703 | ||
704 | #define LPSS_IOSF_GPIODEF0 0x154 | |
705 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
706 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
707 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
708 | ||
709 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
710 | ||
711 | static void lpss_iosf_enter_d3_state(void) | |
712 | { | |
713 | u32 value1 = 0; | |
714 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
715 | u32 value2 = LPSS_PMCSR_D3hot; | |
716 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
717 | /* | |
718 | * PMC provides an information about actual status of the LPSS devices. | |
719 | * Here we read the values related to LPSS power island, i.e. LPSS | |
720 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
721 | */ | |
722 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
723 | int ret; | |
724 | ||
725 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
726 | if (ret) | |
727 | return; | |
728 | ||
729 | mutex_lock(&lpss_iosf_mutex); | |
730 | ||
731 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
732 | if (ret) | |
733 | goto exit; | |
734 | ||
735 | /* | |
736 | * Get the status of entire LPSS power island per device basis. | |
737 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
738 | * are already in D3hot. | |
739 | */ | |
740 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
741 | if (pmc_status) | |
742 | goto exit; | |
743 | ||
744 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
745 | LPSS_IOSF_PMCSR, value2, mask2); | |
746 | ||
747 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
748 | LPSS_IOSF_PMCSR, value2, mask2); | |
749 | ||
750 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
751 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
752 | exit: | |
753 | mutex_unlock(&lpss_iosf_mutex); | |
754 | } | |
755 | ||
756 | static void lpss_iosf_exit_d3_state(void) | |
757 | { | |
758 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3; | |
759 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
760 | u32 value2 = LPSS_PMCSR_D0; | |
761 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
762 | ||
763 | mutex_lock(&lpss_iosf_mutex); | |
764 | ||
765 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
766 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
767 | ||
768 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
769 | LPSS_IOSF_PMCSR, value2, mask2); | |
770 | ||
771 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
772 | LPSS_IOSF_PMCSR, value2, mask2); | |
773 | ||
774 | mutex_unlock(&lpss_iosf_mutex); | |
775 | } | |
776 | ||
c78b0830 HK |
777 | static int acpi_lpss_runtime_suspend(struct device *dev) |
778 | { | |
cb39dcdd AS |
779 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
780 | int ret; | |
c78b0830 | 781 | |
cb39dcdd | 782 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
783 | if (ret) |
784 | return ret; | |
785 | ||
cb39dcdd AS |
786 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
787 | acpi_lpss_save_ctx(dev, pdata); | |
788 | ||
eebb3e8d AS |
789 | ret = acpi_dev_runtime_suspend(dev); |
790 | ||
791 | /* | |
792 | * This call must be last in the sequence, otherwise PMC will return | |
793 | * wrong status for devices being about to be powered off. See | |
794 | * lpss_iosf_enter_d3_state() for further information. | |
795 | */ | |
796 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
797 | lpss_iosf_enter_d3_state(); | |
798 | ||
799 | return ret; | |
c78b0830 HK |
800 | } |
801 | ||
802 | static int acpi_lpss_runtime_resume(struct device *dev) | |
803 | { | |
cb39dcdd AS |
804 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
805 | int ret; | |
c78b0830 | 806 | |
eebb3e8d AS |
807 | /* |
808 | * This call is kept first to be in symmetry with | |
809 | * acpi_lpss_runtime_suspend() one. | |
810 | */ | |
811 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
812 | lpss_iosf_exit_d3_state(); | |
813 | ||
cb39dcdd | 814 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
815 | if (ret) |
816 | return ret; | |
817 | ||
02b98540 AS |
818 | acpi_lpss_d3_to_d0_delay(pdata); |
819 | ||
cb39dcdd AS |
820 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
821 | acpi_lpss_restore_ctx(dev, pdata); | |
822 | ||
c78b0830 HK |
823 | return pm_generic_runtime_resume(dev); |
824 | } | |
c78b0830 HK |
825 | #endif /* CONFIG_PM */ |
826 | ||
827 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
828 | #ifdef CONFIG_PM |
829 | .activate = acpi_lpss_activate, | |
830 | .dismiss = acpi_lpss_dismiss, | |
831 | #endif | |
c78b0830 | 832 | .ops = { |
5de21bb9 | 833 | #ifdef CONFIG_PM |
c78b0830 | 834 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 835 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 836 | .complete = pm_complete_with_resume_check, |
c78b0830 | 837 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
838 | .suspend_late = acpi_lpss_suspend_late, |
839 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
840 | .freeze = acpi_subsys_freeze, |
841 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
842 | .poweroff_late = acpi_lpss_suspend_late, |
843 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 844 | #endif |
c78b0830 HK |
845 | .runtime_suspend = acpi_lpss_runtime_suspend, |
846 | .runtime_resume = acpi_lpss_runtime_resume, | |
847 | #endif | |
848 | }, | |
849 | }; | |
850 | ||
2e0f8822 RW |
851 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
852 | unsigned long action, void *data) | |
853 | { | |
854 | struct platform_device *pdev = to_platform_device(data); | |
855 | struct lpss_private_data *pdata; | |
856 | struct acpi_device *adev; | |
857 | const struct acpi_device_id *id; | |
2e0f8822 RW |
858 | |
859 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
860 | if (!id || !id->driver_data) | |
861 | return 0; | |
862 | ||
863 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
864 | return 0; | |
865 | ||
866 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 867 | if (!pdata) |
2e0f8822 RW |
868 | return 0; |
869 | ||
cb39dcdd AS |
870 | if (pdata->mmio_base && |
871 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
872 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
873 | return 0; | |
874 | } | |
875 | ||
c78b0830 | 876 | switch (action) { |
de16d552 | 877 | case BUS_NOTIFY_BIND_DRIVER: |
01ac170b | 878 | pdev->dev.pm_domain = &acpi_lpss_pm_domain; |
b5f88dd1 | 879 | break; |
de16d552 | 880 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 AS |
881 | case BUS_NOTIFY_UNBOUND_DRIVER: |
882 | pdev->dev.pm_domain = NULL; | |
883 | break; | |
884 | case BUS_NOTIFY_ADD_DEVICE: | |
ff8c1af5 | 885 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
886 | return sysfs_create_group(&pdev->dev.kobj, |
887 | &lpss_attr_group); | |
01ac170b | 888 | break; |
c78b0830 | 889 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 890 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 891 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
01ac170b | 892 | break; |
c78b0830 HK |
893 | default: |
894 | break; | |
895 | } | |
2e0f8822 | 896 | |
c78b0830 | 897 | return 0; |
2e0f8822 RW |
898 | } |
899 | ||
900 | static struct notifier_block acpi_lpss_nb = { | |
901 | .notifier_call = acpi_lpss_platform_notify, | |
902 | }; | |
903 | ||
1a8f8351 RW |
904 | static void acpi_lpss_bind(struct device *dev) |
905 | { | |
906 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
907 | ||
ff8c1af5 | 908 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
909 | return; |
910 | ||
911 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
912 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
913 | else | |
914 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
915 | } | |
916 | ||
917 | static void acpi_lpss_unbind(struct device *dev) | |
918 | { | |
919 | dev->power.set_latency_tolerance = NULL; | |
920 | } | |
921 | ||
f58b082a RW |
922 | static struct acpi_scan_handler lpss_handler = { |
923 | .ids = acpi_lpss_device_ids, | |
924 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
925 | .bind = acpi_lpss_bind, |
926 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
927 | }; |
928 | ||
929 | void __init acpi_lpss_init(void) | |
930 | { | |
eebb3e8d AS |
931 | const struct x86_cpu_id *id; |
932 | int ret; | |
933 | ||
934 | ret = lpt_clk_init(); | |
935 | if (ret) | |
936 | return; | |
937 | ||
938 | id = x86_match_cpu(lpss_cpu_ids); | |
939 | if (id) | |
940 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
941 | ||
942 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
943 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 944 | } |
d6ddaaac RW |
945 | |
946 | #else | |
947 | ||
948 | static struct acpi_scan_handler lpss_handler = { | |
949 | .ids = acpi_lpss_device_ids, | |
950 | }; | |
951 | ||
952 | void __init acpi_lpss_init(void) | |
953 | { | |
954 | acpi_scan_add_handler(&lpss_handler); | |
955 | } | |
956 | ||
957 | #endif /* CONFIG_X86_INTEL_LPSS */ |