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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
6025e2fa | 13 | #include <linux/dmi.h> |
f58b082a RW |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
eebb3e8d | 16 | #include <linux/mutex.h> |
1e30124a | 17 | #include <linux/pci.h> |
f58b082a | 18 | #include <linux/platform_device.h> |
a9443a63 | 19 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 20 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
bf7696a1 | 23 | #include <linux/pwm.h> |
620c803f | 24 | #include <linux/pxa2xx_ssp.h> |
a09c5913 | 25 | #include <linux/suspend.h> |
c78b0830 | 26 | #include <linux/delay.h> |
f58b082a RW |
27 | |
28 | #include "internal.h" | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
15aa5e4c HG |
69 | /* |
70 | * For some devices the DSDT AML code for another device turns off the device | |
71 | * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) | |
72 | * as ctx register values. | |
73 | * Luckily these devices always use the same ctx register values, so we can | |
74 | * work around this by saving the ctx registers once on activation. | |
75 | */ | |
76 | #define LPSS_SAVE_CTX_ONCE BIT(5) | |
77 | #define LPSS_NO_D3_DELAY BIT(6) | |
f6272170 | 78 | |
06d86415 | 79 | struct lpss_private_data; |
f58b082a RW |
80 | |
81 | struct lpss_device_desc { | |
ff8c1af5 | 82 | unsigned int flags; |
fcf0789a | 83 | const char *clk_con_id; |
2e0f8822 | 84 | unsigned int prv_offset; |
958c4eb2 | 85 | size_t prv_size_override; |
f167c1a1 | 86 | const struct property_entry *properties; |
06d86415 | 87 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 88 | bool resume_from_noirq; |
f58b082a RW |
89 | }; |
90 | ||
eebb3e8d | 91 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 92 | .flags = LPSS_CLK, |
b59cc200 RW |
93 | }; |
94 | ||
f58b082a | 95 | struct lpss_private_data { |
dd242a08 | 96 | struct acpi_device *adev; |
f58b082a RW |
97 | void __iomem *mmio_base; |
98 | resource_size_t mmio_size; | |
03f09f73 | 99 | unsigned int fixed_clk_rate; |
f58b082a RW |
100 | struct clk *clk; |
101 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 102 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
103 | }; |
104 | ||
86b62e5c HG |
105 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
106 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
107 | ||
eebb3e8d AS |
108 | /* LPSS run time quirks */ |
109 | static unsigned int lpss_quirks; | |
110 | ||
111 | /* | |
112 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
113 | * | |
fa9e93b1 | 114 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
115 | * it can be powered off automatically whenever the last LPSS device goes down. |
116 | * In case of no power any access to the DMA controller will hang the system. | |
117 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
118 | * well as on ASuS T100TA transformer. | |
119 | * | |
120 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
121 | * on whenever we have at least one other device in use. | |
122 | */ | |
123 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
124 | ||
1f47a77c HK |
125 | /* UART Component Parameter Register */ |
126 | #define LPSS_UART_CPR 0xF4 | |
127 | #define LPSS_UART_CPR_AFCE BIT(4) | |
128 | ||
06d86415 HK |
129 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
130 | { | |
088f1fd2 | 131 | unsigned int offset; |
1f47a77c | 132 | u32 val; |
06d86415 | 133 | |
088f1fd2 | 134 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
135 | val = readl(pdata->mmio_base + offset); |
136 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
137 | ||
138 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
139 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
140 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
141 | val = readl(pdata->mmio_base + offset); | |
142 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
143 | writel(val, pdata->mmio_base + offset); | |
144 | } | |
06d86415 HK |
145 | } |
146 | ||
3095794a | 147 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
148 | { |
149 | unsigned int offset; | |
150 | u32 val; | |
151 | ||
152 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
153 | val = readl(pdata->mmio_base + offset); | |
154 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
155 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
156 | } |
157 | ||
04434ab5 HG |
158 | /* |
159 | * BYT PWM used for backlight control by the i915 driver on systems without | |
160 | * the Crystal Cove PMIC. | |
161 | */ | |
162 | static struct pwm_lookup byt_pwm_lookup[] = { | |
163 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
b2147a3a | 164 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
04434ab5 HG |
165 | "pwm-lpss-platform"), |
166 | }; | |
167 | ||
168 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
169 | { | |
dd242a08 HG |
170 | struct acpi_device *adev = pdata->adev; |
171 | ||
172 | /* Only call pwm_add_table for the first PWM controller */ | |
173 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
174 | return; | |
175 | ||
b2147a3a | 176 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
04434ab5 HG |
177 | } |
178 | ||
3095794a MW |
179 | #define LPSS_I2C_ENABLE 0x6c |
180 | ||
181 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
182 | { | |
86b62e5c HG |
183 | const char *uid_str = acpi_device_uid(pdata->adev); |
184 | acpi_handle handle = pdata->adev->handle; | |
185 | unsigned long long shared_host = 0; | |
186 | acpi_status status; | |
187 | long uid = 0; | |
188 | ||
189 | /* Expected to always be true, but better safe then sorry */ | |
8e3ecc68 LS |
190 | if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) { |
191 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ | |
192 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
193 | if (ACPI_SUCCESS(status) && shared_host) | |
194 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
195 | } | |
86b62e5c | 196 | |
3095794a | 197 | lpss_deassert_reset(pdata); |
765bdd4e | 198 | |
03f09f73 HK |
199 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
200 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
201 | |
202 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 203 | } |
43218a1b | 204 | |
bf7696a1 HG |
205 | /* BSW PWM used for backlight control by the i915 driver */ |
206 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
207 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
b2147a3a | 208 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
bf7696a1 HG |
209 | "pwm-lpss-platform"), |
210 | }; | |
211 | ||
212 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
213 | { | |
dd242a08 HG |
214 | struct acpi_device *adev = pdata->adev; |
215 | ||
216 | /* Only call pwm_add_table for the first PWM controller */ | |
217 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
218 | return; | |
219 | ||
bf7696a1 HG |
220 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
221 | } | |
222 | ||
620c803f AS |
223 | static const struct property_entry lpt_spi_properties[] = { |
224 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), | |
225 | { } | |
226 | }; | |
227 | ||
228 | static const struct lpss_device_desc lpt_spi_dev_desc = { | |
57b30064 JN |
229 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
230 | | LPSS_SAVE_CTX, | |
ed3a872e | 231 | .prv_offset = 0x800, |
620c803f | 232 | .properties = lpt_spi_properties, |
ed3a872e HK |
233 | }; |
234 | ||
b2687cd7 | 235 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
57b30064 | 236 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, |
2e0f8822 | 237 | .prv_offset = 0x800, |
2e0f8822 RW |
238 | }; |
239 | ||
a5565cf2 HK |
240 | static struct property_entry uart_properties[] = { |
241 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
242 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
243 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
244 | { }, | |
245 | }; | |
246 | ||
b2687cd7 | 247 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
57b30064 JN |
248 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
249 | | LPSS_SAVE_CTX, | |
fcf0789a | 250 | .clk_con_id = "baudclk", |
06d86415 | 251 | .prv_offset = 0x800, |
06d86415 | 252 | .setup = lpss_uart_setup, |
a5565cf2 | 253 | .properties = uart_properties, |
2e0f8822 RW |
254 | }; |
255 | ||
b2687cd7 | 256 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 257 | .flags = LPSS_LTR, |
2e0f8822 | 258 | .prv_offset = 0x1000, |
958c4eb2 | 259 | .prv_size_override = 0x1018, |
e1c74817 CCE |
260 | }; |
261 | ||
b2687cd7 | 262 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 263 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 264 | .prv_offset = 0x800, |
04434ab5 | 265 | .setup = byt_pwm_setup, |
e1c74817 CCE |
266 | }; |
267 | ||
b00855ae | 268 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
15aa5e4c | 269 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, |
fdcb613d | 270 | .prv_offset = 0x800, |
bf7696a1 | 271 | .setup = bsw_pwm_setup, |
5e31ee84 | 272 | .resume_from_noirq = true, |
b00855ae SK |
273 | }; |
274 | ||
b2687cd7 | 275 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 276 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 277 | .clk_con_id = "baudclk", |
f6272170 | 278 | .prv_offset = 0x800, |
06d86415 | 279 | .setup = lpss_uart_setup, |
a5565cf2 | 280 | .properties = uart_properties, |
f6272170 MW |
281 | }; |
282 | ||
b00855ae SK |
283 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
284 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
285 | | LPSS_NO_D3_DELAY, | |
286 | .clk_con_id = "baudclk", | |
287 | .prv_offset = 0x800, | |
288 | .setup = lpss_uart_setup, | |
a5565cf2 | 289 | .properties = uart_properties, |
b00855ae SK |
290 | }; |
291 | ||
620c803f AS |
292 | static const struct property_entry byt_spi_properties[] = { |
293 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), | |
294 | { } | |
295 | }; | |
296 | ||
b2687cd7 | 297 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 298 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 299 | .prv_offset = 0x400, |
620c803f | 300 | .properties = byt_spi_properties, |
f6272170 MW |
301 | }; |
302 | ||
b2687cd7 | 303 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 304 | .flags = LPSS_CLK, |
f6272170 MW |
305 | }; |
306 | ||
b2687cd7 | 307 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 308 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 309 | .prv_offset = 0x800, |
03f09f73 | 310 | .setup = byt_i2c_setup, |
48402cee | 311 | .resume_from_noirq = true, |
1bfbd8eb AC |
312 | }; |
313 | ||
b00855ae SK |
314 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
315 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
316 | .prv_offset = 0x800, | |
317 | .setup = byt_i2c_setup, | |
48402cee | 318 | .resume_from_noirq = true, |
b00855ae SK |
319 | }; |
320 | ||
620c803f AS |
321 | static const struct property_entry bsw_spi_properties[] = { |
322 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), | |
323 | { } | |
324 | }; | |
325 | ||
eebb3e8d | 326 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
327 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
328 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
329 | .prv_offset = 0x400, |
330 | .setup = lpss_deassert_reset, | |
620c803f | 331 | .properties = bsw_spi_properties, |
3095794a MW |
332 | }; |
333 | ||
eebb3e8d | 334 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
e36cf2f7 TG |
335 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), |
336 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), | |
eebb3e8d AS |
337 | {} |
338 | }; | |
339 | ||
d6ddaaac RW |
340 | #else |
341 | ||
342 | #define LPSS_ADDR(desc) (0UL) | |
343 | ||
344 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
345 | ||
f58b082a | 346 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 347 | /* Generic LPSS devices */ |
d6ddaaac | 348 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 349 | |
f58b082a | 350 | /* Lynxpoint LPSS devices */ |
620c803f AS |
351 | { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, |
352 | { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
353 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, |
354 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
355 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
356 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
357 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
358 | { "INT33C7", }, |
359 | ||
f6272170 | 360 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
361 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
362 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
363 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
364 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
365 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 366 | { "INT33B2", }, |
20482d32 | 367 | { "INT33FC", }, |
f6272170 | 368 | |
1bfbd8eb | 369 | /* Braswell LPSS devices */ |
24071406 | 370 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae SK |
371 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
372 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 373 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 374 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 375 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 376 | |
b00855ae | 377 | /* Broadwell LPSS devices */ |
620c803f AS |
378 | { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, |
379 | { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
380 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, |
381 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
382 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
383 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
384 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
385 | { "INT3437", }, |
386 | ||
ff8c1af5 | 387 | /* Wildcat Point LPSS devices */ |
620c803f | 388 | { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, |
43218a1b | 389 | |
f58b082a RW |
390 | { } |
391 | }; | |
392 | ||
d6ddaaac RW |
393 | #ifdef CONFIG_X86_INTEL_LPSS |
394 | ||
f58b082a RW |
395 | static int is_memory(struct acpi_resource *res, void *not_used) |
396 | { | |
397 | struct resource r; | |
bb415ed5 | 398 | |
f58b082a RW |
399 | return !acpi_dev_resource_memory(res, &r); |
400 | } | |
401 | ||
402 | /* LPSS main clock device. */ | |
403 | static struct platform_device *lpss_clk_dev; | |
404 | ||
405 | static inline void lpt_register_clock_device(void) | |
406 | { | |
cf0a9565 AS |
407 | lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", |
408 | PLATFORM_DEVID_NONE, | |
409 | NULL, 0); | |
f58b082a RW |
410 | } |
411 | ||
412 | static int register_device_clock(struct acpi_device *adev, | |
413 | struct lpss_private_data *pdata) | |
414 | { | |
415 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 416 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 417 | struct clk *clk; |
b59cc200 | 418 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
419 | const char *parent, *clk_name; |
420 | void __iomem *prv_base; | |
f58b082a RW |
421 | |
422 | if (!lpss_clk_dev) | |
423 | lpt_register_clock_device(); | |
424 | ||
b59cc200 RW |
425 | clk_data = platform_get_drvdata(lpss_clk_dev); |
426 | if (!clk_data) | |
427 | return -ENODEV; | |
b0d00f8b | 428 | clk = clk_data->clk; |
b59cc200 RW |
429 | |
430 | if (!pdata->mmio_base | |
2e0f8822 | 431 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
432 | return -ENODATA; |
433 | ||
f6272170 | 434 | parent = clk_data->name; |
ed3a872e | 435 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 436 | |
03f09f73 HK |
437 | if (pdata->fixed_clk_rate) { |
438 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
439 | pdata->fixed_clk_rate); | |
440 | goto out; | |
f6272170 MW |
441 | } |
442 | ||
ff8c1af5 | 443 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
444 | clk = clk_register_gate(NULL, devname, parent, 0, |
445 | prv_base, 0, 0, NULL); | |
446 | parent = devname; | |
447 | } | |
448 | ||
ff8c1af5 | 449 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
450 | /* Prevent division by zero */ |
451 | if (!readl(prv_base)) | |
452 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
453 | ||
454 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
455 | if (!clk_name) | |
456 | return -ENOMEM; | |
457 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
82f53f9e AS |
458 | CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, |
459 | prv_base, 1, 15, 16, 15, 0, NULL); | |
ed3a872e HK |
460 | parent = clk_name; |
461 | ||
462 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
463 | if (!clk_name) { | |
464 | kfree(parent); | |
465 | return -ENOMEM; | |
466 | } | |
467 | clk = clk_register_gate(NULL, clk_name, parent, | |
468 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
469 | prv_base, 31, 0, NULL); | |
470 | kfree(parent); | |
471 | kfree(clk_name); | |
f6272170 | 472 | } |
03f09f73 | 473 | out: |
f6272170 MW |
474 | if (IS_ERR(clk)) |
475 | return PTR_ERR(clk); | |
f58b082a | 476 | |
ed3a872e | 477 | pdata->clk = clk; |
fcf0789a | 478 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
479 | return 0; |
480 | } | |
481 | ||
e6ce0ce3 AH |
482 | struct lpss_device_links { |
483 | const char *supplier_hid; | |
484 | const char *supplier_uid; | |
485 | const char *consumer_hid; | |
486 | const char *consumer_uid; | |
487 | u32 flags; | |
6025e2fa HG |
488 | const struct dmi_system_id *dep_missing_ids; |
489 | }; | |
490 | ||
491 | /* Please keep this list sorted alphabetically by vendor and model */ | |
492 | static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { | |
493 | { | |
494 | .matches = { | |
495 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), | |
496 | DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), | |
497 | }, | |
498 | }, | |
499 | {} | |
e6ce0ce3 AH |
500 | }; |
501 | ||
502 | /* | |
503 | * The _DEP method is used to identify dependencies but instead of creating | |
504 | * device links for every handle in _DEP, only links in the following list are | |
505 | * created. That is necessary because, in the general case, _DEP can refer to | |
506 | * devices that might not have drivers, or that are on different buses, or where | |
507 | * the supplier is not enumerated until after the consumer is probed. | |
508 | */ | |
509 | static const struct lpss_device_links lpss_device_links[] = { | |
cc18735f | 510 | /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ |
e6ce0ce3 | 511 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, |
cc18735f | 512 | /* CHT iGPU depends on PMIC I2C controller */ |
bd0f4e34 | 513 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
b3b3519c | 514 | /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ |
6025e2fa HG |
515 | {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, |
516 | i2c1_dep_missing_dmi_ids}, | |
cc18735f | 517 | /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ |
2d71ee0c | 518 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
cc18735f HG |
519 | /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ |
520 | {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, | |
e6ce0ce3 AH |
521 | }; |
522 | ||
e6ce0ce3 AH |
523 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, |
524 | const struct lpss_device_links *link) | |
525 | { | |
7e70c8ac | 526 | return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
527 | } |
528 | ||
529 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
530 | const struct lpss_device_links *link) | |
531 | { | |
7e70c8ac | 532 | return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
533 | } |
534 | ||
535 | struct hid_uid { | |
536 | const char *hid; | |
537 | const char *uid; | |
538 | }; | |
539 | ||
418e3ea1 | 540 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
541 | { |
542 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 543 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
544 | |
545 | if (!adev) | |
546 | return 0; | |
547 | ||
7e70c8ac | 548 | return acpi_dev_hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
549 | } |
550 | ||
551 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
552 | { | |
1e30124a HG |
553 | struct device *dev; |
554 | ||
e6ce0ce3 AH |
555 | struct hid_uid data = { |
556 | .hid = hid, | |
557 | .uid = uid, | |
558 | }; | |
559 | ||
1e30124a HG |
560 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
561 | if (dev) | |
562 | return dev; | |
563 | ||
564 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
565 | } |
566 | ||
567 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
568 | { | |
569 | struct acpi_handle_list dep_devices; | |
570 | acpi_status status; | |
571 | int i; | |
572 | ||
573 | if (!acpi_has_method(adev->handle, "_DEP")) | |
574 | return false; | |
575 | ||
576 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
577 | &dep_devices); | |
578 | if (ACPI_FAILURE(status)) { | |
579 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
580 | return false; | |
581 | } | |
582 | ||
583 | for (i = 0; i < dep_devices.count; i++) { | |
584 | if (dep_devices.handles[i] == handle) | |
585 | return true; | |
586 | } | |
587 | ||
588 | return false; | |
589 | } | |
590 | ||
591 | static void acpi_lpss_link_consumer(struct device *dev1, | |
592 | const struct lpss_device_links *link) | |
593 | { | |
594 | struct device *dev2; | |
595 | ||
596 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
597 | if (!dev2) | |
598 | return; | |
599 | ||
6025e2fa HG |
600 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
601 | || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
e6ce0ce3 AH |
602 | device_link_add(dev2, dev1, link->flags); |
603 | ||
604 | put_device(dev2); | |
605 | } | |
606 | ||
607 | static void acpi_lpss_link_supplier(struct device *dev1, | |
608 | const struct lpss_device_links *link) | |
609 | { | |
610 | struct device *dev2; | |
611 | ||
612 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
613 | if (!dev2) | |
614 | return; | |
615 | ||
6025e2fa HG |
616 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
617 | || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
e6ce0ce3 AH |
618 | device_link_add(dev1, dev2, link->flags); |
619 | ||
620 | put_device(dev2); | |
621 | } | |
622 | ||
623 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
624 | struct platform_device *pdev) | |
625 | { | |
626 | int i; | |
627 | ||
628 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
629 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
630 | ||
631 | if (acpi_lpss_is_supplier(adev, link)) | |
632 | acpi_lpss_link_consumer(&pdev->dev, link); | |
633 | ||
634 | if (acpi_lpss_is_consumer(adev, link)) | |
635 | acpi_lpss_link_supplier(&pdev->dev, link); | |
636 | } | |
637 | } | |
638 | ||
f58b082a RW |
639 | static int acpi_lpss_create_device(struct acpi_device *adev, |
640 | const struct acpi_device_id *id) | |
641 | { | |
b2687cd7 | 642 | const struct lpss_device_desc *dev_desc; |
f58b082a | 643 | struct lpss_private_data *pdata; |
90e97820 | 644 | struct resource_entry *rentry; |
f58b082a | 645 | struct list_head resource_list; |
8ce62f85 | 646 | struct platform_device *pdev; |
f58b082a RW |
647 | int ret; |
648 | ||
b2687cd7 | 649 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 650 | if (!dev_desc) { |
1571875b | 651 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
652 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
653 | } | |
f58b082a RW |
654 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
655 | if (!pdata) | |
656 | return -ENOMEM; | |
657 | ||
658 | INIT_LIST_HEAD(&resource_list); | |
659 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
660 | if (ret < 0) | |
661 | goto err_out; | |
662 | ||
663 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 664 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
665 | if (dev_desc->prv_size_override) |
666 | pdata->mmio_size = dev_desc->prv_size_override; | |
667 | else | |
90e97820 JL |
668 | pdata->mmio_size = resource_size(rentry->res); |
669 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 670 | pdata->mmio_size); |
f58b082a RW |
671 | break; |
672 | } | |
673 | ||
674 | acpi_dev_free_resource_list(&resource_list); | |
675 | ||
d3e13ff3 | 676 | if (!pdata->mmio_base) { |
e1681599 HG |
677 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
678 | adev->pnp.type.platform_id = 0; | |
a4bb2b49 RT |
679 | /* Skip the device, but continue the namespace scan. */ |
680 | ret = 0; | |
d3e13ff3 RW |
681 | goto err_out; |
682 | } | |
683 | ||
dd242a08 | 684 | pdata->adev = adev; |
af65cfe9 MW |
685 | pdata->dev_desc = dev_desc; |
686 | ||
03f09f73 HK |
687 | if (dev_desc->setup) |
688 | dev_desc->setup(pdata); | |
689 | ||
ff8c1af5 | 690 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
691 | ret = register_device_clock(adev, pdata); |
692 | if (ret) { | |
b9e95fc6 RW |
693 | /* Skip the device, but continue the namespace scan. */ |
694 | ret = 0; | |
695 | goto err_out; | |
f58b082a RW |
696 | } |
697 | } | |
698 | ||
b9e95fc6 RW |
699 | /* |
700 | * This works around a known issue in ACPI tables where LPSS devices | |
701 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
702 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
703 | */ | |
1a2fa02f | 704 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 705 | |
f58b082a | 706 | adev->driver_data = pdata; |
1571875b | 707 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 708 | if (!IS_ERR_OR_NULL(pdev)) { |
e6ce0ce3 | 709 | acpi_lpss_create_device_links(adev, pdev); |
8ce62f85 RW |
710 | return 1; |
711 | } | |
f58b082a | 712 | |
8ce62f85 | 713 | ret = PTR_ERR(pdev); |
f58b082a RW |
714 | adev->driver_data = NULL; |
715 | ||
716 | err_out: | |
717 | kfree(pdata); | |
718 | return ret; | |
719 | } | |
720 | ||
1a8f8351 RW |
721 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
722 | { | |
723 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
724 | } | |
725 | ||
726 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
727 | unsigned int reg) | |
728 | { | |
729 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
730 | } | |
731 | ||
2e0f8822 RW |
732 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
733 | { | |
50861d43 | 734 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2e0f8822 RW |
735 | struct lpss_private_data *pdata; |
736 | unsigned long flags; | |
737 | int ret; | |
738 | ||
50861d43 RW |
739 | if (WARN_ON(!adev)) |
740 | return -ENODEV; | |
2e0f8822 RW |
741 | |
742 | spin_lock_irqsave(&dev->power.lock, flags); | |
743 | if (pm_runtime_suspended(dev)) { | |
744 | ret = -EAGAIN; | |
745 | goto out; | |
746 | } | |
747 | pdata = acpi_driver_data(adev); | |
748 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
749 | ret = -ENODEV; | |
750 | goto out; | |
751 | } | |
1a8f8351 | 752 | *val = __lpss_reg_read(pdata, reg); |
50861d43 | 753 | ret = 0; |
2e0f8822 RW |
754 | |
755 | out: | |
756 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
757 | return ret; | |
758 | } | |
759 | ||
760 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
761 | char *buf) | |
762 | { | |
763 | u32 ltr_value = 0; | |
764 | unsigned int reg; | |
765 | int ret; | |
766 | ||
767 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
768 | ret = lpss_reg_read(dev, reg, <r_value); | |
769 | if (ret) | |
770 | return ret; | |
771 | ||
d47e983e | 772 | return sysfs_emit(buf, "%08x\n", ltr_value); |
2e0f8822 RW |
773 | } |
774 | ||
775 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
776 | struct device_attribute *attr, char *buf) | |
777 | { | |
778 | u32 ltr_mode = 0; | |
779 | char *outstr; | |
780 | int ret; | |
781 | ||
782 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
783 | if (ret) | |
784 | return ret; | |
785 | ||
786 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
787 | return sprintf(buf, "%s\n", outstr); | |
788 | } | |
789 | ||
790 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
791 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
792 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
793 | ||
794 | static struct attribute *lpss_attrs[] = { | |
795 | &dev_attr_auto_ltr.attr, | |
796 | &dev_attr_sw_ltr.attr, | |
797 | &dev_attr_ltr_mode.attr, | |
798 | NULL, | |
799 | }; | |
800 | ||
31945d0e | 801 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
802 | .attrs = lpss_attrs, |
803 | .name = "lpss_ltr", | |
804 | }; | |
805 | ||
1a8f8351 RW |
806 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
807 | { | |
808 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
809 | u32 ltr_mode, ltr_val; | |
810 | ||
811 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
812 | if (val < 0) { | |
813 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
814 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
815 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
816 | } | |
817 | return; | |
818 | } | |
819 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
820 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
821 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
822 | val = LPSS_LTR_MAX_VAL; | |
823 | } else if (val > LPSS_LTR_MAX_VAL) { | |
824 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
825 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
826 | } else { | |
827 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
828 | } | |
829 | ltr_val |= val; | |
830 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
831 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
832 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
833 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
834 | } | |
835 | } | |
836 | ||
c78b0830 HK |
837 | #ifdef CONFIG_PM |
838 | /** | |
839 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
840 | * @dev: LPSS device | |
cb39dcdd | 841 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
842 | * |
843 | * Most LPSS devices have private registers which may loose their context when | |
844 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
845 | * prv_reg_ctx array. | |
846 | */ | |
cb39dcdd AS |
847 | static void acpi_lpss_save_ctx(struct device *dev, |
848 | struct lpss_private_data *pdata) | |
c78b0830 | 849 | { |
c78b0830 HK |
850 | unsigned int i; |
851 | ||
852 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
853 | unsigned long offset = i * sizeof(u32); | |
854 | ||
855 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
856 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
857 | pdata->prv_reg_ctx[i], offset); | |
858 | } | |
859 | } | |
860 | ||
861 | /** | |
862 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
863 | * @dev: LPSS device | |
cb39dcdd | 864 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
865 | * |
866 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
867 | */ | |
cb39dcdd AS |
868 | static void acpi_lpss_restore_ctx(struct device *dev, |
869 | struct lpss_private_data *pdata) | |
c78b0830 | 870 | { |
c78b0830 HK |
871 | unsigned int i; |
872 | ||
02b98540 AS |
873 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
874 | unsigned long offset = i * sizeof(u32); | |
875 | ||
876 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
877 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
878 | pdata->prv_reg_ctx[i], offset); | |
879 | } | |
880 | } | |
881 | ||
882 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
883 | { | |
c78b0830 HK |
884 | /* |
885 | * The following delay is needed or the subsequent write operations may | |
886 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
887 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 888 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 889 | */ |
b00855ae SK |
890 | unsigned int delay = 10; /* default 10ms delay */ |
891 | ||
892 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
893 | delay = 0; | |
894 | ||
895 | msleep(delay); | |
c78b0830 HK |
896 | } |
897 | ||
c3a49cf3 AS |
898 | static int acpi_lpss_activate(struct device *dev) |
899 | { | |
900 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
901 | int ret; | |
902 | ||
63705c40 | 903 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
904 | if (ret) |
905 | return ret; | |
906 | ||
907 | acpi_lpss_d3_to_d0_delay(pdata); | |
908 | ||
909 | /* | |
910 | * This is called only on ->probe() stage where a device is either in | |
911 | * known state defined by BIOS or most likely powered off. Due to this | |
912 | * we have to deassert reset line to be sure that ->probe() will | |
913 | * recognize the device. | |
914 | */ | |
15aa5e4c | 915 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
c3a49cf3 AS |
916 | lpss_deassert_reset(pdata); |
917 | ||
15aa5e4c HG |
918 | #ifdef CONFIG_PM |
919 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) | |
920 | acpi_lpss_save_ctx(dev, pdata); | |
921 | #endif | |
922 | ||
c3a49cf3 AS |
923 | return 0; |
924 | } | |
925 | ||
926 | static void acpi_lpss_dismiss(struct device *dev) | |
927 | { | |
cbe25ce3 | 928 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
929 | } |
930 | ||
eebb3e8d AS |
931 | /* IOSF SB for LPSS island */ |
932 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
933 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
934 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
935 | ||
936 | #define LPSS_IOSF_PMCSR 0x84 | |
937 | #define LPSS_PMCSR_D0 0 | |
938 | #define LPSS_PMCSR_D3hot 3 | |
939 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
940 | ||
941 | #define LPSS_IOSF_GPIODEF0 0x154 | |
942 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
943 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
944 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 945 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
946 | |
947 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 948 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
949 | |
950 | static void lpss_iosf_enter_d3_state(void) | |
951 | { | |
952 | u32 value1 = 0; | |
d132d6d5 | 953 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
954 | u32 value2 = LPSS_PMCSR_D3hot; |
955 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
956 | /* | |
957 | * PMC provides an information about actual status of the LPSS devices. | |
958 | * Here we read the values related to LPSS power island, i.e. LPSS | |
959 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
960 | */ | |
86b62e5c | 961 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
962 | int ret; |
963 | ||
964 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
965 | if (ret) | |
966 | return; | |
967 | ||
968 | mutex_lock(&lpss_iosf_mutex); | |
969 | ||
970 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
971 | if (ret) | |
972 | goto exit; | |
973 | ||
974 | /* | |
975 | * Get the status of entire LPSS power island per device basis. | |
976 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
977 | * are already in D3hot. | |
978 | */ | |
86b62e5c | 979 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
980 | if (pmc_status) |
981 | goto exit; | |
982 | ||
983 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
984 | LPSS_IOSF_PMCSR, value2, mask2); | |
985 | ||
986 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
987 | LPSS_IOSF_PMCSR, value2, mask2); | |
988 | ||
989 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
990 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
991 | |
992 | lpss_iosf_d3_entered = true; | |
993 | ||
eebb3e8d AS |
994 | exit: |
995 | mutex_unlock(&lpss_iosf_mutex); | |
996 | } | |
997 | ||
998 | static void lpss_iosf_exit_d3_state(void) | |
999 | { | |
d132d6d5 AS |
1000 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
1001 | LPSS_GPIODEF0_DMA_LLP; | |
1002 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
1003 | u32 value2 = LPSS_PMCSR_D0; |
1004 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
1005 | ||
1006 | mutex_lock(&lpss_iosf_mutex); | |
1007 | ||
12864ff8 RW |
1008 | if (!lpss_iosf_d3_entered) |
1009 | goto exit; | |
1010 | ||
1011 | lpss_iosf_d3_entered = false; | |
1012 | ||
eebb3e8d AS |
1013 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
1014 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
1015 | ||
1016 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
1017 | LPSS_IOSF_PMCSR, value2, mask2); | |
1018 | ||
1019 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
1020 | LPSS_IOSF_PMCSR, value2, mask2); | |
1021 | ||
12864ff8 | 1022 | exit: |
eebb3e8d AS |
1023 | mutex_unlock(&lpss_iosf_mutex); |
1024 | } | |
1025 | ||
12864ff8 | 1026 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 1027 | { |
cb39dcdd AS |
1028 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1029 | int ret; | |
c78b0830 | 1030 | |
cb39dcdd AS |
1031 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1032 | acpi_lpss_save_ctx(dev, pdata); | |
1033 | ||
a192aa92 | 1034 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1035 | |
1036 | /* | |
1037 | * This call must be last in the sequence, otherwise PMC will return | |
1038 | * wrong status for devices being about to be powered off. See | |
1039 | * lpss_iosf_enter_d3_state() for further information. | |
1040 | */ | |
12864ff8 | 1041 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1042 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1043 | lpss_iosf_enter_d3_state(); |
1044 | ||
1045 | return ret; | |
c78b0830 HK |
1046 | } |
1047 | ||
12864ff8 | 1048 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1049 | { |
cb39dcdd AS |
1050 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1051 | int ret; | |
c78b0830 | 1052 | |
eebb3e8d AS |
1053 | /* |
1054 | * This call is kept first to be in symmetry with | |
1055 | * acpi_lpss_runtime_suspend() one. | |
1056 | */ | |
12864ff8 | 1057 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1058 | lpss_iosf_exit_d3_state(); |
1059 | ||
63705c40 | 1060 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1061 | if (ret) |
1062 | return ret; | |
1063 | ||
02b98540 AS |
1064 | acpi_lpss_d3_to_d0_delay(pdata); |
1065 | ||
15aa5e4c | 1066 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
cb39dcdd AS |
1067 | acpi_lpss_restore_ctx(dev, pdata); |
1068 | ||
a192aa92 RW |
1069 | return 0; |
1070 | } | |
1071 | ||
1072 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1073 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1074 | { |
05087360 RW |
1075 | int ret; |
1076 | ||
fa2bfead | 1077 | if (dev_pm_skip_suspend(dev)) |
05087360 | 1078 | return 0; |
a192aa92 | 1079 | |
05087360 | 1080 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1081 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1082 | } |
1083 | ||
48402cee HG |
1084 | static int acpi_lpss_suspend_late(struct device *dev) |
1085 | { | |
1086 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1087 | ||
1088 | if (pdata->dev_desc->resume_from_noirq) | |
1089 | return 0; | |
1090 | ||
1091 | return acpi_lpss_do_suspend_late(dev); | |
1092 | } | |
1093 | ||
1094 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1095 | { | |
1096 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1097 | int ret; | |
1098 | ||
1099 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1100 | /* |
1101 | * The driver's ->suspend_late callback will be invoked by | |
1102 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1103 | * driver really wanted to run that code in ->suspend_noirq, but | |
1104 | * it could not run after acpi_dev_suspend() and the driver | |
1105 | * expected the latter to be called in the "late" phase. | |
1106 | */ | |
48402cee HG |
1107 | ret = acpi_lpss_do_suspend_late(dev); |
1108 | if (ret) | |
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | return acpi_subsys_suspend_noirq(dev); | |
1113 | } | |
1114 | ||
1115 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1116 | { |
12864ff8 | 1117 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1118 | |
1119 | return ret ? ret : pm_generic_resume_early(dev); | |
1120 | } | |
48402cee HG |
1121 | |
1122 | static int acpi_lpss_resume_early(struct device *dev) | |
1123 | { | |
1124 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1125 | ||
1126 | if (pdata->dev_desc->resume_from_noirq) | |
1127 | return 0; | |
1128 | ||
76c70cb5 | 1129 | if (dev_pm_skip_resume(dev)) |
6e176bf8 RW |
1130 | return 0; |
1131 | ||
48402cee HG |
1132 | return acpi_lpss_do_resume_early(dev); |
1133 | } | |
1134 | ||
1135 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1136 | { | |
1137 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1138 | int ret; | |
1139 | ||
3cd7957e | 1140 | /* Follow acpi_subsys_resume_noirq(). */ |
76c70cb5 | 1141 | if (dev_pm_skip_resume(dev)) |
3cd7957e RW |
1142 | return 0; |
1143 | ||
3cd7957e | 1144 | ret = pm_generic_resume_noirq(dev); |
48402cee HG |
1145 | if (ret) |
1146 | return ret; | |
1147 | ||
3cd7957e RW |
1148 | if (!pdata->dev_desc->resume_from_noirq) |
1149 | return 0; | |
48402cee | 1150 | |
3cd7957e RW |
1151 | /* |
1152 | * The driver's ->resume_early callback will be invoked by | |
1153 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1154 | * really wanted to run that code in ->resume_noirq, but it could not | |
1155 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1156 | * called in the "early" phase. | |
1157 | */ | |
1158 | return acpi_lpss_do_resume_early(dev); | |
1159 | } | |
1160 | ||
1161 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1162 | { | |
1163 | int ret = acpi_lpss_resume(dev); | |
1164 | ||
1165 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1166 | } |
1167 | ||
3cd7957e RW |
1168 | static int acpi_lpss_restore_early(struct device *dev) |
1169 | { | |
1170 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1171 | ||
1172 | if (pdata->dev_desc->resume_from_noirq) | |
1173 | return 0; | |
1174 | ||
1175 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1176 | } |
1177 | ||
3cd7957e RW |
1178 | static int acpi_lpss_restore_noirq(struct device *dev) |
1179 | { | |
1180 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1181 | int ret; | |
1182 | ||
1183 | ret = pm_generic_restore_noirq(dev); | |
1184 | if (ret) | |
1185 | return ret; | |
1186 | ||
1187 | if (!pdata->dev_desc->resume_from_noirq) | |
1188 | return 0; | |
1189 | ||
1190 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1191 | return acpi_lpss_do_restore_early(dev); | |
1192 | } | |
c95b7595 RW |
1193 | |
1194 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1195 | { | |
1196 | int ret = pm_generic_poweroff_late(dev); | |
1197 | ||
1198 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1199 | } | |
1200 | ||
1201 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1202 | { | |
1203 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1204 | ||
fa2bfead | 1205 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1206 | return 0; |
1207 | ||
1208 | if (pdata->dev_desc->resume_from_noirq) | |
1209 | return 0; | |
1210 | ||
1211 | return acpi_lpss_do_poweroff_late(dev); | |
1212 | } | |
1213 | ||
1214 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1215 | { | |
1216 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1217 | ||
fa2bfead | 1218 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1219 | return 0; |
1220 | ||
1221 | if (pdata->dev_desc->resume_from_noirq) { | |
1222 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1223 | int ret = acpi_lpss_do_poweroff_late(dev); | |
bb415ed5 | 1224 | |
c95b7595 RW |
1225 | if (ret) |
1226 | return ret; | |
1227 | } | |
1228 | ||
1229 | return pm_generic_poweroff_noirq(dev); | |
1230 | } | |
a192aa92 RW |
1231 | #endif /* CONFIG_PM_SLEEP */ |
1232 | ||
1233 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1234 | { | |
1235 | int ret = pm_generic_runtime_suspend(dev); | |
1236 | ||
1237 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1238 | } | |
1239 | ||
1240 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1241 | { | |
12864ff8 | 1242 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1243 | |
1244 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1245 | } |
c78b0830 HK |
1246 | #endif /* CONFIG_PM */ |
1247 | ||
1248 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1249 | #ifdef CONFIG_PM |
1250 | .activate = acpi_lpss_activate, | |
1251 | .dismiss = acpi_lpss_dismiss, | |
1252 | #endif | |
c78b0830 | 1253 | .ops = { |
5de21bb9 | 1254 | #ifdef CONFIG_PM |
c78b0830 | 1255 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1256 | .prepare = acpi_subsys_prepare, |
e4da817d | 1257 | .complete = acpi_subsys_complete, |
c78b0830 | 1258 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1259 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1260 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1261 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1262 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1263 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1264 | .poweroff = acpi_subsys_poweroff, |
1265 | .poweroff_late = acpi_lpss_poweroff_late, | |
1266 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1267 | .restore_noirq = acpi_lpss_restore_noirq, |
1268 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1269 | #endif |
c78b0830 HK |
1270 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1271 | .runtime_resume = acpi_lpss_runtime_resume, | |
1272 | #endif | |
1273 | }, | |
1274 | }; | |
1275 | ||
2e0f8822 RW |
1276 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1277 | unsigned long action, void *data) | |
1278 | { | |
1279 | struct platform_device *pdev = to_platform_device(data); | |
1280 | struct lpss_private_data *pdata; | |
1281 | struct acpi_device *adev; | |
1282 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1283 | |
1284 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1285 | if (!id || !id->driver_data) | |
1286 | return 0; | |
1287 | ||
50861d43 RW |
1288 | adev = ACPI_COMPANION(&pdev->dev); |
1289 | if (!adev) | |
2e0f8822 RW |
1290 | return 0; |
1291 | ||
1292 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1293 | if (!pdata) |
2e0f8822 RW |
1294 | return 0; |
1295 | ||
cb39dcdd AS |
1296 | if (pdata->mmio_base && |
1297 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1298 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1299 | return 0; | |
1300 | } | |
1301 | ||
c78b0830 | 1302 | switch (action) { |
de16d552 | 1303 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1304 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1305 | break; |
de16d552 | 1306 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1307 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1308 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1309 | break; |
1310 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1311 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1312 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1313 | return sysfs_create_group(&pdev->dev.kobj, |
1314 | &lpss_attr_group); | |
01ac170b | 1315 | break; |
c78b0830 | 1316 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1317 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1318 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1319 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1320 | break; |
c78b0830 HK |
1321 | default: |
1322 | break; | |
1323 | } | |
2e0f8822 | 1324 | |
c78b0830 | 1325 | return 0; |
2e0f8822 RW |
1326 | } |
1327 | ||
1328 | static struct notifier_block acpi_lpss_nb = { | |
1329 | .notifier_call = acpi_lpss_platform_notify, | |
1330 | }; | |
1331 | ||
1a8f8351 RW |
1332 | static void acpi_lpss_bind(struct device *dev) |
1333 | { | |
1334 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1335 | ||
ff8c1af5 | 1336 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1337 | return; |
1338 | ||
1339 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1340 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1341 | else | |
1342 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1343 | } | |
1344 | ||
1345 | static void acpi_lpss_unbind(struct device *dev) | |
1346 | { | |
1347 | dev->power.set_latency_tolerance = NULL; | |
1348 | } | |
1349 | ||
f58b082a RW |
1350 | static struct acpi_scan_handler lpss_handler = { |
1351 | .ids = acpi_lpss_device_ids, | |
1352 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1353 | .bind = acpi_lpss_bind, |
1354 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1355 | }; |
1356 | ||
1357 | void __init acpi_lpss_init(void) | |
1358 | { | |
eebb3e8d AS |
1359 | const struct x86_cpu_id *id; |
1360 | int ret; | |
1361 | ||
cf0a9565 | 1362 | ret = lpss_atom_clk_init(); |
eebb3e8d AS |
1363 | if (ret) |
1364 | return; | |
1365 | ||
1366 | id = x86_match_cpu(lpss_cpu_ids); | |
1367 | if (id) | |
1368 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1369 | ||
1370 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1371 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1372 | } |
d6ddaaac RW |
1373 | |
1374 | #else | |
1375 | ||
1376 | static struct acpi_scan_handler lpss_handler = { | |
1377 | .ids = acpi_lpss_device_ids, | |
1378 | }; | |
1379 | ||
1380 | void __init acpi_lpss_init(void) | |
1381 | { | |
1382 | acpi_scan_add_handler(&lpss_handler); | |
1383 | } | |
1384 | ||
1385 | #endif /* CONFIG_X86_INTEL_LPSS */ |