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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
6025e2fa | 13 | #include <linux/dmi.h> |
f58b082a RW |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
eebb3e8d | 16 | #include <linux/mutex.h> |
1e30124a | 17 | #include <linux/pci.h> |
f58b082a | 18 | #include <linux/platform_device.h> |
a9443a63 | 19 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 20 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
bf7696a1 | 23 | #include <linux/pwm.h> |
620c803f | 24 | #include <linux/pxa2xx_ssp.h> |
a09c5913 | 25 | #include <linux/suspend.h> |
c78b0830 | 26 | #include <linux/delay.h> |
f58b082a RW |
27 | |
28 | #include "internal.h" | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
15aa5e4c HG |
69 | /* |
70 | * For some devices the DSDT AML code for another device turns off the device | |
71 | * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) | |
72 | * as ctx register values. | |
73 | * Luckily these devices always use the same ctx register values, so we can | |
74 | * work around this by saving the ctx registers once on activation. | |
75 | */ | |
76 | #define LPSS_SAVE_CTX_ONCE BIT(5) | |
77 | #define LPSS_NO_D3_DELAY BIT(6) | |
f6272170 | 78 | |
06d86415 | 79 | struct lpss_private_data; |
f58b082a RW |
80 | |
81 | struct lpss_device_desc { | |
ff8c1af5 | 82 | unsigned int flags; |
fcf0789a | 83 | const char *clk_con_id; |
2e0f8822 | 84 | unsigned int prv_offset; |
958c4eb2 | 85 | size_t prv_size_override; |
f167c1a1 | 86 | const struct property_entry *properties; |
06d86415 | 87 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 88 | bool resume_from_noirq; |
f58b082a RW |
89 | }; |
90 | ||
eebb3e8d | 91 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 92 | .flags = LPSS_CLK, |
b59cc200 RW |
93 | }; |
94 | ||
f58b082a | 95 | struct lpss_private_data { |
dd242a08 | 96 | struct acpi_device *adev; |
f58b082a RW |
97 | void __iomem *mmio_base; |
98 | resource_size_t mmio_size; | |
03f09f73 | 99 | unsigned int fixed_clk_rate; |
f58b082a RW |
100 | struct clk *clk; |
101 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 102 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
103 | }; |
104 | ||
86b62e5c HG |
105 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
106 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
107 | ||
eebb3e8d AS |
108 | /* LPSS run time quirks */ |
109 | static unsigned int lpss_quirks; | |
110 | ||
111 | /* | |
112 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
113 | * | |
fa9e93b1 | 114 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
115 | * it can be powered off automatically whenever the last LPSS device goes down. |
116 | * In case of no power any access to the DMA controller will hang the system. | |
117 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
118 | * well as on ASuS T100TA transformer. | |
119 | * | |
120 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
121 | * on whenever we have at least one other device in use. | |
122 | */ | |
123 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
124 | ||
1f47a77c HK |
125 | /* UART Component Parameter Register */ |
126 | #define LPSS_UART_CPR 0xF4 | |
127 | #define LPSS_UART_CPR_AFCE BIT(4) | |
128 | ||
06d86415 HK |
129 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
130 | { | |
088f1fd2 | 131 | unsigned int offset; |
1f47a77c | 132 | u32 val; |
06d86415 | 133 | |
088f1fd2 | 134 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
135 | val = readl(pdata->mmio_base + offset); |
136 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
137 | ||
138 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
139 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
140 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
141 | val = readl(pdata->mmio_base + offset); | |
142 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
143 | writel(val, pdata->mmio_base + offset); | |
144 | } | |
06d86415 HK |
145 | } |
146 | ||
3095794a | 147 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
148 | { |
149 | unsigned int offset; | |
150 | u32 val; | |
151 | ||
152 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
153 | val = readl(pdata->mmio_base + offset); | |
154 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
155 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
156 | } |
157 | ||
04434ab5 HG |
158 | /* |
159 | * BYT PWM used for backlight control by the i915 driver on systems without | |
160 | * the Crystal Cove PMIC. | |
161 | */ | |
162 | static struct pwm_lookup byt_pwm_lookup[] = { | |
163 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
b2147a3a | 164 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
04434ab5 HG |
165 | "pwm-lpss-platform"), |
166 | }; | |
167 | ||
168 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
169 | { | |
2a036e48 | 170 | u64 uid; |
dd242a08 HG |
171 | |
172 | /* Only call pwm_add_table for the first PWM controller */ | |
2a036e48 | 173 | if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) |
dd242a08 HG |
174 | return; |
175 | ||
b2147a3a | 176 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
04434ab5 HG |
177 | } |
178 | ||
3095794a MW |
179 | #define LPSS_I2C_ENABLE 0x6c |
180 | ||
181 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
182 | { | |
86b62e5c HG |
183 | acpi_handle handle = pdata->adev->handle; |
184 | unsigned long long shared_host = 0; | |
185 | acpi_status status; | |
2a036e48 | 186 | u64 uid; |
86b62e5c | 187 | |
2a036e48 AS |
188 | /* Expected to always be successfull, but better safe then sorry */ |
189 | if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) { | |
8e3ecc68 LS |
190 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ |
191 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
192 | if (ACPI_SUCCESS(status) && shared_host) | |
193 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
194 | } | |
86b62e5c | 195 | |
3095794a | 196 | lpss_deassert_reset(pdata); |
765bdd4e | 197 | |
03f09f73 HK |
198 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
199 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
200 | |
201 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 202 | } |
43218a1b | 203 | |
bf7696a1 HG |
204 | /* BSW PWM used for backlight control by the i915 driver */ |
205 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
206 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
b2147a3a | 207 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
bf7696a1 HG |
208 | "pwm-lpss-platform"), |
209 | }; | |
210 | ||
211 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
212 | { | |
2a036e48 | 213 | u64 uid; |
dd242a08 HG |
214 | |
215 | /* Only call pwm_add_table for the first PWM controller */ | |
2a036e48 | 216 | if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) |
dd242a08 HG |
217 | return; |
218 | ||
bf7696a1 HG |
219 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
220 | } | |
221 | ||
620c803f AS |
222 | static const struct property_entry lpt_spi_properties[] = { |
223 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), | |
224 | { } | |
225 | }; | |
226 | ||
227 | static const struct lpss_device_desc lpt_spi_dev_desc = { | |
57b30064 JN |
228 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
229 | | LPSS_SAVE_CTX, | |
ed3a872e | 230 | .prv_offset = 0x800, |
620c803f | 231 | .properties = lpt_spi_properties, |
ed3a872e HK |
232 | }; |
233 | ||
b2687cd7 | 234 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
57b30064 | 235 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, |
2e0f8822 | 236 | .prv_offset = 0x800, |
2e0f8822 RW |
237 | }; |
238 | ||
a5565cf2 HK |
239 | static struct property_entry uart_properties[] = { |
240 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
241 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
242 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
243 | { }, | |
244 | }; | |
245 | ||
b2687cd7 | 246 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
57b30064 JN |
247 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
248 | | LPSS_SAVE_CTX, | |
fcf0789a | 249 | .clk_con_id = "baudclk", |
06d86415 | 250 | .prv_offset = 0x800, |
06d86415 | 251 | .setup = lpss_uart_setup, |
a5565cf2 | 252 | .properties = uart_properties, |
2e0f8822 RW |
253 | }; |
254 | ||
b2687cd7 | 255 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 256 | .flags = LPSS_LTR, |
2e0f8822 | 257 | .prv_offset = 0x1000, |
958c4eb2 | 258 | .prv_size_override = 0x1018, |
e1c74817 CCE |
259 | }; |
260 | ||
b2687cd7 | 261 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 262 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 263 | .prv_offset = 0x800, |
04434ab5 | 264 | .setup = byt_pwm_setup, |
e1c74817 CCE |
265 | }; |
266 | ||
b00855ae | 267 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
15aa5e4c | 268 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, |
fdcb613d | 269 | .prv_offset = 0x800, |
bf7696a1 | 270 | .setup = bsw_pwm_setup, |
5e31ee84 | 271 | .resume_from_noirq = true, |
b00855ae SK |
272 | }; |
273 | ||
b2687cd7 | 274 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 275 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 276 | .clk_con_id = "baudclk", |
f6272170 | 277 | .prv_offset = 0x800, |
06d86415 | 278 | .setup = lpss_uart_setup, |
a5565cf2 | 279 | .properties = uart_properties, |
f6272170 MW |
280 | }; |
281 | ||
b00855ae SK |
282 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
283 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
284 | | LPSS_NO_D3_DELAY, | |
285 | .clk_con_id = "baudclk", | |
286 | .prv_offset = 0x800, | |
287 | .setup = lpss_uart_setup, | |
a5565cf2 | 288 | .properties = uart_properties, |
b00855ae SK |
289 | }; |
290 | ||
620c803f AS |
291 | static const struct property_entry byt_spi_properties[] = { |
292 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), | |
293 | { } | |
294 | }; | |
295 | ||
b2687cd7 | 296 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 297 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 298 | .prv_offset = 0x400, |
620c803f | 299 | .properties = byt_spi_properties, |
f6272170 MW |
300 | }; |
301 | ||
b2687cd7 | 302 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 303 | .flags = LPSS_CLK, |
f6272170 MW |
304 | }; |
305 | ||
b2687cd7 | 306 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 307 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 308 | .prv_offset = 0x800, |
03f09f73 | 309 | .setup = byt_i2c_setup, |
48402cee | 310 | .resume_from_noirq = true, |
1bfbd8eb AC |
311 | }; |
312 | ||
b00855ae SK |
313 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
314 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
315 | .prv_offset = 0x800, | |
316 | .setup = byt_i2c_setup, | |
48402cee | 317 | .resume_from_noirq = true, |
b00855ae SK |
318 | }; |
319 | ||
620c803f AS |
320 | static const struct property_entry bsw_spi_properties[] = { |
321 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), | |
322 | { } | |
323 | }; | |
324 | ||
eebb3e8d | 325 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
326 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
327 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
328 | .prv_offset = 0x400, |
329 | .setup = lpss_deassert_reset, | |
620c803f | 330 | .properties = bsw_spi_properties, |
3095794a MW |
331 | }; |
332 | ||
eebb3e8d | 333 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
e36cf2f7 TG |
334 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), |
335 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), | |
eebb3e8d AS |
336 | {} |
337 | }; | |
338 | ||
d6ddaaac RW |
339 | #else |
340 | ||
341 | #define LPSS_ADDR(desc) (0UL) | |
342 | ||
343 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
344 | ||
f58b082a | 345 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 346 | /* Generic LPSS devices */ |
d6ddaaac | 347 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 348 | |
f58b082a | 349 | /* Lynxpoint LPSS devices */ |
620c803f AS |
350 | { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, |
351 | { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
352 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, |
353 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
354 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
355 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
356 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
357 | { "INT33C7", }, |
358 | ||
f6272170 | 359 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
360 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
361 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
362 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
363 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
364 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 365 | { "INT33B2", }, |
20482d32 | 366 | { "INT33FC", }, |
f6272170 | 367 | |
1bfbd8eb | 368 | /* Braswell LPSS devices */ |
24071406 | 369 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae SK |
370 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
371 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 372 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 373 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 374 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 375 | |
b00855ae | 376 | /* Broadwell LPSS devices */ |
620c803f AS |
377 | { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, |
378 | { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
379 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, |
380 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
381 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
382 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
383 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
384 | { "INT3437", }, |
385 | ||
ff8c1af5 | 386 | /* Wildcat Point LPSS devices */ |
620c803f | 387 | { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, |
43218a1b | 388 | |
f58b082a RW |
389 | { } |
390 | }; | |
391 | ||
d6ddaaac RW |
392 | #ifdef CONFIG_X86_INTEL_LPSS |
393 | ||
f58b082a RW |
394 | /* LPSS main clock device. */ |
395 | static struct platform_device *lpss_clk_dev; | |
396 | ||
397 | static inline void lpt_register_clock_device(void) | |
398 | { | |
cf0a9565 AS |
399 | lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", |
400 | PLATFORM_DEVID_NONE, | |
401 | NULL, 0); | |
f58b082a RW |
402 | } |
403 | ||
404 | static int register_device_clock(struct acpi_device *adev, | |
405 | struct lpss_private_data *pdata) | |
406 | { | |
407 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 408 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 409 | struct clk *clk; |
b59cc200 | 410 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
411 | const char *parent, *clk_name; |
412 | void __iomem *prv_base; | |
f58b082a RW |
413 | |
414 | if (!lpss_clk_dev) | |
415 | lpt_register_clock_device(); | |
416 | ||
b4f1f61e | 417 | if (IS_ERR(lpss_clk_dev)) |
418 | return PTR_ERR(lpss_clk_dev); | |
419 | ||
b59cc200 RW |
420 | clk_data = platform_get_drvdata(lpss_clk_dev); |
421 | if (!clk_data) | |
422 | return -ENODEV; | |
b0d00f8b | 423 | clk = clk_data->clk; |
b59cc200 RW |
424 | |
425 | if (!pdata->mmio_base | |
2e0f8822 | 426 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
427 | return -ENODATA; |
428 | ||
f6272170 | 429 | parent = clk_data->name; |
ed3a872e | 430 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 431 | |
03f09f73 HK |
432 | if (pdata->fixed_clk_rate) { |
433 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
434 | pdata->fixed_clk_rate); | |
435 | goto out; | |
f6272170 MW |
436 | } |
437 | ||
ff8c1af5 | 438 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
439 | clk = clk_register_gate(NULL, devname, parent, 0, |
440 | prv_base, 0, 0, NULL); | |
441 | parent = devname; | |
442 | } | |
443 | ||
ff8c1af5 | 444 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
445 | /* Prevent division by zero */ |
446 | if (!readl(prv_base)) | |
447 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
448 | ||
449 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
450 | if (!clk_name) | |
451 | return -ENOMEM; | |
452 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
82f53f9e AS |
453 | CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, |
454 | prv_base, 1, 15, 16, 15, 0, NULL); | |
ed3a872e HK |
455 | parent = clk_name; |
456 | ||
457 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
458 | if (!clk_name) { | |
459 | kfree(parent); | |
460 | return -ENOMEM; | |
461 | } | |
462 | clk = clk_register_gate(NULL, clk_name, parent, | |
463 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
464 | prv_base, 31, 0, NULL); | |
465 | kfree(parent); | |
466 | kfree(clk_name); | |
f6272170 | 467 | } |
03f09f73 | 468 | out: |
f6272170 MW |
469 | if (IS_ERR(clk)) |
470 | return PTR_ERR(clk); | |
f58b082a | 471 | |
ed3a872e | 472 | pdata->clk = clk; |
fcf0789a | 473 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
474 | return 0; |
475 | } | |
476 | ||
e6ce0ce3 AH |
477 | struct lpss_device_links { |
478 | const char *supplier_hid; | |
479 | const char *supplier_uid; | |
480 | const char *consumer_hid; | |
481 | const char *consumer_uid; | |
482 | u32 flags; | |
6025e2fa HG |
483 | const struct dmi_system_id *dep_missing_ids; |
484 | }; | |
485 | ||
486 | /* Please keep this list sorted alphabetically by vendor and model */ | |
487 | static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { | |
488 | { | |
489 | .matches = { | |
490 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), | |
491 | DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), | |
492 | }, | |
493 | }, | |
494 | {} | |
e6ce0ce3 AH |
495 | }; |
496 | ||
497 | /* | |
498 | * The _DEP method is used to identify dependencies but instead of creating | |
499 | * device links for every handle in _DEP, only links in the following list are | |
500 | * created. That is necessary because, in the general case, _DEP can refer to | |
501 | * devices that might not have drivers, or that are on different buses, or where | |
502 | * the supplier is not enumerated until after the consumer is probed. | |
503 | */ | |
504 | static const struct lpss_device_links lpss_device_links[] = { | |
cc18735f | 505 | /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ |
e6ce0ce3 | 506 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, |
cc18735f | 507 | /* CHT iGPU depends on PMIC I2C controller */ |
bd0f4e34 | 508 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
b3b3519c | 509 | /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ |
6025e2fa HG |
510 | {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, |
511 | i2c1_dep_missing_dmi_ids}, | |
cc18735f | 512 | /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ |
2d71ee0c | 513 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
cc18735f HG |
514 | /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ |
515 | {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, | |
e6ce0ce3 AH |
516 | }; |
517 | ||
e6ce0ce3 AH |
518 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, |
519 | const struct lpss_device_links *link) | |
520 | { | |
7e70c8ac | 521 | return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
522 | } |
523 | ||
524 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
525 | const struct lpss_device_links *link) | |
526 | { | |
7e70c8ac | 527 | return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
528 | } |
529 | ||
530 | struct hid_uid { | |
531 | const char *hid; | |
532 | const char *uid; | |
533 | }; | |
534 | ||
418e3ea1 | 535 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
536 | { |
537 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 538 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
539 | |
540 | if (!adev) | |
541 | return 0; | |
542 | ||
7e70c8ac | 543 | return acpi_dev_hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
544 | } |
545 | ||
546 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
547 | { | |
1e30124a HG |
548 | struct device *dev; |
549 | ||
e6ce0ce3 AH |
550 | struct hid_uid data = { |
551 | .hid = hid, | |
552 | .uid = uid, | |
553 | }; | |
554 | ||
1e30124a HG |
555 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
556 | if (dev) | |
557 | return dev; | |
558 | ||
559 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
560 | } |
561 | ||
562 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
563 | { | |
564 | struct acpi_handle_list dep_devices; | |
565 | acpi_status status; | |
566 | int i; | |
567 | ||
568 | if (!acpi_has_method(adev->handle, "_DEP")) | |
569 | return false; | |
570 | ||
571 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
572 | &dep_devices); | |
573 | if (ACPI_FAILURE(status)) { | |
574 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
575 | return false; | |
576 | } | |
577 | ||
578 | for (i = 0; i < dep_devices.count; i++) { | |
579 | if (dep_devices.handles[i] == handle) | |
580 | return true; | |
581 | } | |
582 | ||
583 | return false; | |
584 | } | |
585 | ||
586 | static void acpi_lpss_link_consumer(struct device *dev1, | |
587 | const struct lpss_device_links *link) | |
588 | { | |
589 | struct device *dev2; | |
590 | ||
591 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
592 | if (!dev2) | |
593 | return; | |
594 | ||
6025e2fa HG |
595 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
596 | || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
e6ce0ce3 AH |
597 | device_link_add(dev2, dev1, link->flags); |
598 | ||
599 | put_device(dev2); | |
600 | } | |
601 | ||
602 | static void acpi_lpss_link_supplier(struct device *dev1, | |
603 | const struct lpss_device_links *link) | |
604 | { | |
605 | struct device *dev2; | |
606 | ||
607 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
608 | if (!dev2) | |
609 | return; | |
610 | ||
6025e2fa HG |
611 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
612 | || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
e6ce0ce3 AH |
613 | device_link_add(dev1, dev2, link->flags); |
614 | ||
615 | put_device(dev2); | |
616 | } | |
617 | ||
618 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
619 | struct platform_device *pdev) | |
620 | { | |
621 | int i; | |
622 | ||
623 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
624 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
625 | ||
626 | if (acpi_lpss_is_supplier(adev, link)) | |
627 | acpi_lpss_link_consumer(&pdev->dev, link); | |
628 | ||
629 | if (acpi_lpss_is_consumer(adev, link)) | |
630 | acpi_lpss_link_supplier(&pdev->dev, link); | |
631 | } | |
632 | } | |
633 | ||
f58b082a RW |
634 | static int acpi_lpss_create_device(struct acpi_device *adev, |
635 | const struct acpi_device_id *id) | |
636 | { | |
b2687cd7 | 637 | const struct lpss_device_desc *dev_desc; |
f58b082a | 638 | struct lpss_private_data *pdata; |
90e97820 | 639 | struct resource_entry *rentry; |
f58b082a | 640 | struct list_head resource_list; |
8ce62f85 | 641 | struct platform_device *pdev; |
f58b082a RW |
642 | int ret; |
643 | ||
b2687cd7 | 644 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 645 | if (!dev_desc) { |
1571875b | 646 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
647 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
648 | } | |
f58b082a RW |
649 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
650 | if (!pdata) | |
651 | return -ENOMEM; | |
652 | ||
653 | INIT_LIST_HEAD(&resource_list); | |
840baca4 | 654 | ret = acpi_dev_get_memory_resources(adev, &resource_list); |
f58b082a RW |
655 | if (ret < 0) |
656 | goto err_out; | |
657 | ||
da13b336 AS |
658 | rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node); |
659 | if (rentry) { | |
660 | if (dev_desc->prv_size_override) | |
661 | pdata->mmio_size = dev_desc->prv_size_override; | |
662 | else | |
663 | pdata->mmio_size = resource_size(rentry->res); | |
664 | pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size); | |
665 | } | |
f58b082a RW |
666 | |
667 | acpi_dev_free_resource_list(&resource_list); | |
668 | ||
d3e13ff3 | 669 | if (!pdata->mmio_base) { |
e1681599 HG |
670 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
671 | adev->pnp.type.platform_id = 0; | |
6cc401be | 672 | goto out_free; |
d3e13ff3 RW |
673 | } |
674 | ||
dd242a08 | 675 | pdata->adev = adev; |
af65cfe9 MW |
676 | pdata->dev_desc = dev_desc; |
677 | ||
03f09f73 HK |
678 | if (dev_desc->setup) |
679 | dev_desc->setup(pdata); | |
680 | ||
ff8c1af5 | 681 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a | 682 | ret = register_device_clock(adev, pdata); |
6cc401be AS |
683 | if (ret) |
684 | goto out_free; | |
f58b082a RW |
685 | } |
686 | ||
b9e95fc6 RW |
687 | /* |
688 | * This works around a known issue in ACPI tables where LPSS devices | |
689 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
690 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
691 | */ | |
1a2fa02f | 692 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 693 | |
f58b082a | 694 | adev->driver_data = pdata; |
1571875b | 695 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
6cc401be AS |
696 | if (IS_ERR_OR_NULL(pdev)) { |
697 | adev->driver_data = NULL; | |
698 | ret = PTR_ERR(pdev); | |
699 | goto err_out; | |
8ce62f85 | 700 | } |
f58b082a | 701 | |
6cc401be AS |
702 | acpi_lpss_create_device_links(adev, pdev); |
703 | return 1; | |
f58b082a | 704 | |
6cc401be AS |
705 | out_free: |
706 | /* Skip the device, but continue the namespace scan */ | |
707 | ret = 0; | |
708 | err_out: | |
f58b082a RW |
709 | kfree(pdata); |
710 | return ret; | |
711 | } | |
712 | ||
1a8f8351 RW |
713 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
714 | { | |
715 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
716 | } | |
717 | ||
718 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
719 | unsigned int reg) | |
720 | { | |
721 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
722 | } | |
723 | ||
2e0f8822 RW |
724 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
725 | { | |
50861d43 | 726 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2e0f8822 RW |
727 | struct lpss_private_data *pdata; |
728 | unsigned long flags; | |
729 | int ret; | |
730 | ||
50861d43 RW |
731 | if (WARN_ON(!adev)) |
732 | return -ENODEV; | |
2e0f8822 RW |
733 | |
734 | spin_lock_irqsave(&dev->power.lock, flags); | |
735 | if (pm_runtime_suspended(dev)) { | |
736 | ret = -EAGAIN; | |
737 | goto out; | |
738 | } | |
739 | pdata = acpi_driver_data(adev); | |
740 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
741 | ret = -ENODEV; | |
742 | goto out; | |
743 | } | |
1a8f8351 | 744 | *val = __lpss_reg_read(pdata, reg); |
50861d43 | 745 | ret = 0; |
2e0f8822 RW |
746 | |
747 | out: | |
748 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
749 | return ret; | |
750 | } | |
751 | ||
752 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
753 | char *buf) | |
754 | { | |
755 | u32 ltr_value = 0; | |
756 | unsigned int reg; | |
757 | int ret; | |
758 | ||
759 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
760 | ret = lpss_reg_read(dev, reg, <r_value); | |
761 | if (ret) | |
762 | return ret; | |
763 | ||
d47e983e | 764 | return sysfs_emit(buf, "%08x\n", ltr_value); |
2e0f8822 RW |
765 | } |
766 | ||
767 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
768 | struct device_attribute *attr, char *buf) | |
769 | { | |
770 | u32 ltr_mode = 0; | |
771 | char *outstr; | |
772 | int ret; | |
773 | ||
774 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
775 | if (ret) | |
776 | return ret; | |
777 | ||
778 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
779 | return sprintf(buf, "%s\n", outstr); | |
780 | } | |
781 | ||
782 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
783 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
784 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
785 | ||
786 | static struct attribute *lpss_attrs[] = { | |
787 | &dev_attr_auto_ltr.attr, | |
788 | &dev_attr_sw_ltr.attr, | |
789 | &dev_attr_ltr_mode.attr, | |
790 | NULL, | |
791 | }; | |
792 | ||
31945d0e | 793 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
794 | .attrs = lpss_attrs, |
795 | .name = "lpss_ltr", | |
796 | }; | |
797 | ||
1a8f8351 RW |
798 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
799 | { | |
800 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
801 | u32 ltr_mode, ltr_val; | |
802 | ||
803 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
804 | if (val < 0) { | |
805 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
806 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
807 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
808 | } | |
809 | return; | |
810 | } | |
811 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
812 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
813 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
814 | val = LPSS_LTR_MAX_VAL; | |
815 | } else if (val > LPSS_LTR_MAX_VAL) { | |
816 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
817 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
818 | } else { | |
819 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
820 | } | |
821 | ltr_val |= val; | |
822 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
823 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
824 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
825 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
826 | } | |
827 | } | |
828 | ||
c78b0830 HK |
829 | #ifdef CONFIG_PM |
830 | /** | |
831 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
832 | * @dev: LPSS device | |
cb39dcdd | 833 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
834 | * |
835 | * Most LPSS devices have private registers which may loose their context when | |
836 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
837 | * prv_reg_ctx array. | |
838 | */ | |
cb39dcdd AS |
839 | static void acpi_lpss_save_ctx(struct device *dev, |
840 | struct lpss_private_data *pdata) | |
c78b0830 | 841 | { |
c78b0830 HK |
842 | unsigned int i; |
843 | ||
844 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
845 | unsigned long offset = i * sizeof(u32); | |
846 | ||
847 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
848 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
849 | pdata->prv_reg_ctx[i], offset); | |
850 | } | |
851 | } | |
852 | ||
853 | /** | |
854 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
855 | * @dev: LPSS device | |
cb39dcdd | 856 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
857 | * |
858 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
859 | */ | |
cb39dcdd AS |
860 | static void acpi_lpss_restore_ctx(struct device *dev, |
861 | struct lpss_private_data *pdata) | |
c78b0830 | 862 | { |
c78b0830 HK |
863 | unsigned int i; |
864 | ||
02b98540 AS |
865 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
866 | unsigned long offset = i * sizeof(u32); | |
867 | ||
868 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
869 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
870 | pdata->prv_reg_ctx[i], offset); | |
871 | } | |
872 | } | |
873 | ||
874 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
875 | { | |
c78b0830 HK |
876 | /* |
877 | * The following delay is needed or the subsequent write operations may | |
878 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
879 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 880 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 881 | */ |
b00855ae SK |
882 | unsigned int delay = 10; /* default 10ms delay */ |
883 | ||
884 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
885 | delay = 0; | |
886 | ||
887 | msleep(delay); | |
c78b0830 HK |
888 | } |
889 | ||
c3a49cf3 AS |
890 | static int acpi_lpss_activate(struct device *dev) |
891 | { | |
892 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
893 | int ret; | |
894 | ||
63705c40 | 895 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
896 | if (ret) |
897 | return ret; | |
898 | ||
899 | acpi_lpss_d3_to_d0_delay(pdata); | |
900 | ||
901 | /* | |
902 | * This is called only on ->probe() stage where a device is either in | |
903 | * known state defined by BIOS or most likely powered off. Due to this | |
904 | * we have to deassert reset line to be sure that ->probe() will | |
905 | * recognize the device. | |
906 | */ | |
15aa5e4c | 907 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
c3a49cf3 AS |
908 | lpss_deassert_reset(pdata); |
909 | ||
15aa5e4c HG |
910 | #ifdef CONFIG_PM |
911 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) | |
912 | acpi_lpss_save_ctx(dev, pdata); | |
913 | #endif | |
914 | ||
c3a49cf3 AS |
915 | return 0; |
916 | } | |
917 | ||
918 | static void acpi_lpss_dismiss(struct device *dev) | |
919 | { | |
cbe25ce3 | 920 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
921 | } |
922 | ||
eebb3e8d AS |
923 | /* IOSF SB for LPSS island */ |
924 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
925 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
926 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
927 | ||
928 | #define LPSS_IOSF_PMCSR 0x84 | |
929 | #define LPSS_PMCSR_D0 0 | |
930 | #define LPSS_PMCSR_D3hot 3 | |
931 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
932 | ||
933 | #define LPSS_IOSF_GPIODEF0 0x154 | |
934 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
935 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
936 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 937 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
938 | |
939 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 940 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
941 | |
942 | static void lpss_iosf_enter_d3_state(void) | |
943 | { | |
944 | u32 value1 = 0; | |
d132d6d5 | 945 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
946 | u32 value2 = LPSS_PMCSR_D3hot; |
947 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
948 | /* | |
949 | * PMC provides an information about actual status of the LPSS devices. | |
950 | * Here we read the values related to LPSS power island, i.e. LPSS | |
951 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
952 | */ | |
86b62e5c | 953 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
954 | int ret; |
955 | ||
956 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
957 | if (ret) | |
958 | return; | |
959 | ||
960 | mutex_lock(&lpss_iosf_mutex); | |
961 | ||
962 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
963 | if (ret) | |
964 | goto exit; | |
965 | ||
966 | /* | |
967 | * Get the status of entire LPSS power island per device basis. | |
968 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
969 | * are already in D3hot. | |
970 | */ | |
86b62e5c | 971 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
972 | if (pmc_status) |
973 | goto exit; | |
974 | ||
975 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
976 | LPSS_IOSF_PMCSR, value2, mask2); | |
977 | ||
978 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
979 | LPSS_IOSF_PMCSR, value2, mask2); | |
980 | ||
981 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
982 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
983 | |
984 | lpss_iosf_d3_entered = true; | |
985 | ||
eebb3e8d AS |
986 | exit: |
987 | mutex_unlock(&lpss_iosf_mutex); | |
988 | } | |
989 | ||
990 | static void lpss_iosf_exit_d3_state(void) | |
991 | { | |
d132d6d5 AS |
992 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
993 | LPSS_GPIODEF0_DMA_LLP; | |
994 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
995 | u32 value2 = LPSS_PMCSR_D0; |
996 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
997 | ||
998 | mutex_lock(&lpss_iosf_mutex); | |
999 | ||
12864ff8 RW |
1000 | if (!lpss_iosf_d3_entered) |
1001 | goto exit; | |
1002 | ||
1003 | lpss_iosf_d3_entered = false; | |
1004 | ||
eebb3e8d AS |
1005 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
1006 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
1007 | ||
1008 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
1009 | LPSS_IOSF_PMCSR, value2, mask2); | |
1010 | ||
1011 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
1012 | LPSS_IOSF_PMCSR, value2, mask2); | |
1013 | ||
12864ff8 | 1014 | exit: |
eebb3e8d AS |
1015 | mutex_unlock(&lpss_iosf_mutex); |
1016 | } | |
1017 | ||
12864ff8 | 1018 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 1019 | { |
cb39dcdd AS |
1020 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1021 | int ret; | |
c78b0830 | 1022 | |
cb39dcdd AS |
1023 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1024 | acpi_lpss_save_ctx(dev, pdata); | |
1025 | ||
a192aa92 | 1026 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1027 | |
1028 | /* | |
1029 | * This call must be last in the sequence, otherwise PMC will return | |
1030 | * wrong status for devices being about to be powered off. See | |
1031 | * lpss_iosf_enter_d3_state() for further information. | |
1032 | */ | |
12864ff8 | 1033 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1034 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1035 | lpss_iosf_enter_d3_state(); |
1036 | ||
1037 | return ret; | |
c78b0830 HK |
1038 | } |
1039 | ||
12864ff8 | 1040 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1041 | { |
cb39dcdd AS |
1042 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1043 | int ret; | |
c78b0830 | 1044 | |
eebb3e8d AS |
1045 | /* |
1046 | * This call is kept first to be in symmetry with | |
1047 | * acpi_lpss_runtime_suspend() one. | |
1048 | */ | |
12864ff8 | 1049 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1050 | lpss_iosf_exit_d3_state(); |
1051 | ||
63705c40 | 1052 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1053 | if (ret) |
1054 | return ret; | |
1055 | ||
02b98540 AS |
1056 | acpi_lpss_d3_to_d0_delay(pdata); |
1057 | ||
15aa5e4c | 1058 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
cb39dcdd AS |
1059 | acpi_lpss_restore_ctx(dev, pdata); |
1060 | ||
a192aa92 RW |
1061 | return 0; |
1062 | } | |
1063 | ||
1064 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1065 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1066 | { |
05087360 RW |
1067 | int ret; |
1068 | ||
fa2bfead | 1069 | if (dev_pm_skip_suspend(dev)) |
05087360 | 1070 | return 0; |
a192aa92 | 1071 | |
05087360 | 1072 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1073 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1074 | } |
1075 | ||
48402cee HG |
1076 | static int acpi_lpss_suspend_late(struct device *dev) |
1077 | { | |
1078 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1079 | ||
1080 | if (pdata->dev_desc->resume_from_noirq) | |
1081 | return 0; | |
1082 | ||
1083 | return acpi_lpss_do_suspend_late(dev); | |
1084 | } | |
1085 | ||
1086 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1087 | { | |
1088 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1089 | int ret; | |
1090 | ||
1091 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1092 | /* |
1093 | * The driver's ->suspend_late callback will be invoked by | |
1094 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1095 | * driver really wanted to run that code in ->suspend_noirq, but | |
1096 | * it could not run after acpi_dev_suspend() and the driver | |
1097 | * expected the latter to be called in the "late" phase. | |
1098 | */ | |
48402cee HG |
1099 | ret = acpi_lpss_do_suspend_late(dev); |
1100 | if (ret) | |
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | return acpi_subsys_suspend_noirq(dev); | |
1105 | } | |
1106 | ||
1107 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1108 | { |
12864ff8 | 1109 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1110 | |
1111 | return ret ? ret : pm_generic_resume_early(dev); | |
1112 | } | |
48402cee HG |
1113 | |
1114 | static int acpi_lpss_resume_early(struct device *dev) | |
1115 | { | |
1116 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1117 | ||
1118 | if (pdata->dev_desc->resume_from_noirq) | |
1119 | return 0; | |
1120 | ||
76c70cb5 | 1121 | if (dev_pm_skip_resume(dev)) |
6e176bf8 RW |
1122 | return 0; |
1123 | ||
48402cee HG |
1124 | return acpi_lpss_do_resume_early(dev); |
1125 | } | |
1126 | ||
1127 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1128 | { | |
1129 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1130 | int ret; | |
1131 | ||
3cd7957e | 1132 | /* Follow acpi_subsys_resume_noirq(). */ |
76c70cb5 | 1133 | if (dev_pm_skip_resume(dev)) |
3cd7957e RW |
1134 | return 0; |
1135 | ||
3cd7957e | 1136 | ret = pm_generic_resume_noirq(dev); |
48402cee HG |
1137 | if (ret) |
1138 | return ret; | |
1139 | ||
3cd7957e RW |
1140 | if (!pdata->dev_desc->resume_from_noirq) |
1141 | return 0; | |
48402cee | 1142 | |
3cd7957e RW |
1143 | /* |
1144 | * The driver's ->resume_early callback will be invoked by | |
1145 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1146 | * really wanted to run that code in ->resume_noirq, but it could not | |
1147 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1148 | * called in the "early" phase. | |
1149 | */ | |
1150 | return acpi_lpss_do_resume_early(dev); | |
1151 | } | |
1152 | ||
1153 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1154 | { | |
1155 | int ret = acpi_lpss_resume(dev); | |
1156 | ||
1157 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1158 | } |
1159 | ||
3cd7957e RW |
1160 | static int acpi_lpss_restore_early(struct device *dev) |
1161 | { | |
1162 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1163 | ||
1164 | if (pdata->dev_desc->resume_from_noirq) | |
1165 | return 0; | |
1166 | ||
1167 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1168 | } |
1169 | ||
3cd7957e RW |
1170 | static int acpi_lpss_restore_noirq(struct device *dev) |
1171 | { | |
1172 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1173 | int ret; | |
1174 | ||
1175 | ret = pm_generic_restore_noirq(dev); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | ||
1179 | if (!pdata->dev_desc->resume_from_noirq) | |
1180 | return 0; | |
1181 | ||
1182 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1183 | return acpi_lpss_do_restore_early(dev); | |
1184 | } | |
c95b7595 RW |
1185 | |
1186 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1187 | { | |
1188 | int ret = pm_generic_poweroff_late(dev); | |
1189 | ||
1190 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1191 | } | |
1192 | ||
1193 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1194 | { | |
1195 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1196 | ||
fa2bfead | 1197 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1198 | return 0; |
1199 | ||
1200 | if (pdata->dev_desc->resume_from_noirq) | |
1201 | return 0; | |
1202 | ||
1203 | return acpi_lpss_do_poweroff_late(dev); | |
1204 | } | |
1205 | ||
1206 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1207 | { | |
1208 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1209 | ||
fa2bfead | 1210 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1211 | return 0; |
1212 | ||
1213 | if (pdata->dev_desc->resume_from_noirq) { | |
1214 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1215 | int ret = acpi_lpss_do_poweroff_late(dev); | |
bb415ed5 | 1216 | |
c95b7595 RW |
1217 | if (ret) |
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | return pm_generic_poweroff_noirq(dev); | |
1222 | } | |
a192aa92 RW |
1223 | #endif /* CONFIG_PM_SLEEP */ |
1224 | ||
1225 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1226 | { | |
1227 | int ret = pm_generic_runtime_suspend(dev); | |
1228 | ||
1229 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1230 | } | |
1231 | ||
1232 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1233 | { | |
12864ff8 | 1234 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1235 | |
1236 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1237 | } |
c78b0830 HK |
1238 | #endif /* CONFIG_PM */ |
1239 | ||
1240 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1241 | #ifdef CONFIG_PM |
1242 | .activate = acpi_lpss_activate, | |
1243 | .dismiss = acpi_lpss_dismiss, | |
1244 | #endif | |
c78b0830 | 1245 | .ops = { |
5de21bb9 | 1246 | #ifdef CONFIG_PM |
c78b0830 | 1247 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1248 | .prepare = acpi_subsys_prepare, |
e4da817d | 1249 | .complete = acpi_subsys_complete, |
c78b0830 | 1250 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1251 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1252 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1253 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1254 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1255 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1256 | .poweroff = acpi_subsys_poweroff, |
1257 | .poweroff_late = acpi_lpss_poweroff_late, | |
1258 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1259 | .restore_noirq = acpi_lpss_restore_noirq, |
1260 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1261 | #endif |
c78b0830 HK |
1262 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1263 | .runtime_resume = acpi_lpss_runtime_resume, | |
1264 | #endif | |
1265 | }, | |
1266 | }; | |
1267 | ||
2e0f8822 RW |
1268 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1269 | unsigned long action, void *data) | |
1270 | { | |
1271 | struct platform_device *pdev = to_platform_device(data); | |
1272 | struct lpss_private_data *pdata; | |
1273 | struct acpi_device *adev; | |
1274 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1275 | |
1276 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1277 | if (!id || !id->driver_data) | |
1278 | return 0; | |
1279 | ||
50861d43 RW |
1280 | adev = ACPI_COMPANION(&pdev->dev); |
1281 | if (!adev) | |
2e0f8822 RW |
1282 | return 0; |
1283 | ||
1284 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1285 | if (!pdata) |
2e0f8822 RW |
1286 | return 0; |
1287 | ||
cb39dcdd AS |
1288 | if (pdata->mmio_base && |
1289 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1290 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1291 | return 0; | |
1292 | } | |
1293 | ||
c78b0830 | 1294 | switch (action) { |
de16d552 | 1295 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1296 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1297 | break; |
de16d552 | 1298 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1299 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1300 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1301 | break; |
1302 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1303 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1304 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1305 | return sysfs_create_group(&pdev->dev.kobj, |
1306 | &lpss_attr_group); | |
01ac170b | 1307 | break; |
c78b0830 | 1308 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1309 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1310 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1311 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1312 | break; |
c78b0830 HK |
1313 | default: |
1314 | break; | |
1315 | } | |
2e0f8822 | 1316 | |
c78b0830 | 1317 | return 0; |
2e0f8822 RW |
1318 | } |
1319 | ||
1320 | static struct notifier_block acpi_lpss_nb = { | |
1321 | .notifier_call = acpi_lpss_platform_notify, | |
1322 | }; | |
1323 | ||
1a8f8351 RW |
1324 | static void acpi_lpss_bind(struct device *dev) |
1325 | { | |
1326 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1327 | ||
ff8c1af5 | 1328 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1329 | return; |
1330 | ||
1331 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1332 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1333 | else | |
1334 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1335 | } | |
1336 | ||
1337 | static void acpi_lpss_unbind(struct device *dev) | |
1338 | { | |
1339 | dev->power.set_latency_tolerance = NULL; | |
1340 | } | |
1341 | ||
f58b082a RW |
1342 | static struct acpi_scan_handler lpss_handler = { |
1343 | .ids = acpi_lpss_device_ids, | |
1344 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1345 | .bind = acpi_lpss_bind, |
1346 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1347 | }; |
1348 | ||
1349 | void __init acpi_lpss_init(void) | |
1350 | { | |
eebb3e8d AS |
1351 | const struct x86_cpu_id *id; |
1352 | int ret; | |
1353 | ||
cf0a9565 | 1354 | ret = lpss_atom_clk_init(); |
eebb3e8d AS |
1355 | if (ret) |
1356 | return; | |
1357 | ||
1358 | id = x86_match_cpu(lpss_cpu_ids); | |
1359 | if (id) | |
1360 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1361 | ||
1362 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1363 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1364 | } |
d6ddaaac RW |
1365 | |
1366 | #else | |
1367 | ||
1368 | static struct acpi_scan_handler lpss_handler = { | |
1369 | .ids = acpi_lpss_device_ids, | |
1370 | }; | |
1371 | ||
1372 | void __init acpi_lpss_init(void) | |
1373 | { | |
1374 | acpi_scan_add_handler(&lpss_handler); | |
1375 | } | |
1376 | ||
1377 | #endif /* CONFIG_X86_INTEL_LPSS */ |