Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
eebb3e8d | 15 | #include <linux/mutex.h> |
1e30124a | 16 | #include <linux/pci.h> |
f58b082a | 17 | #include <linux/platform_device.h> |
a9443a63 | 18 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 19 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 20 | #include <linux/pm_domain.h> |
2e0f8822 | 21 | #include <linux/pm_runtime.h> |
bf7696a1 | 22 | #include <linux/pwm.h> |
a09c5913 | 23 | #include <linux/suspend.h> |
c78b0830 | 24 | #include <linux/delay.h> |
f58b082a RW |
25 | |
26 | #include "internal.h" | |
27 | ||
28 | ACPI_MODULE_NAME("acpi_lpss"); | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 69 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 70 | |
c975e472 HG |
71 | /* Crystal Cove PMIC shares same ACPI ID between different platforms */ |
72 | #define BYT_CRC_HRV 2 | |
73 | #define CHT_CRC_HRV 3 | |
74 | ||
06d86415 | 75 | struct lpss_private_data; |
f58b082a RW |
76 | |
77 | struct lpss_device_desc { | |
ff8c1af5 | 78 | unsigned int flags; |
fcf0789a | 79 | const char *clk_con_id; |
2e0f8822 | 80 | unsigned int prv_offset; |
958c4eb2 | 81 | size_t prv_size_override; |
a5565cf2 | 82 | struct property_entry *properties; |
06d86415 | 83 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 84 | bool resume_from_noirq; |
f58b082a RW |
85 | }; |
86 | ||
eebb3e8d | 87 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 88 | .flags = LPSS_CLK, |
b59cc200 RW |
89 | }; |
90 | ||
f58b082a | 91 | struct lpss_private_data { |
dd242a08 | 92 | struct acpi_device *adev; |
f58b082a RW |
93 | void __iomem *mmio_base; |
94 | resource_size_t mmio_size; | |
03f09f73 | 95 | unsigned int fixed_clk_rate; |
f58b082a RW |
96 | struct clk *clk; |
97 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 98 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
99 | }; |
100 | ||
86b62e5c HG |
101 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
102 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
103 | ||
eebb3e8d AS |
104 | /* LPSS run time quirks */ |
105 | static unsigned int lpss_quirks; | |
106 | ||
107 | /* | |
108 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
109 | * | |
fa9e93b1 | 110 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
111 | * it can be powered off automatically whenever the last LPSS device goes down. |
112 | * In case of no power any access to the DMA controller will hang the system. | |
113 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
114 | * well as on ASuS T100TA transformer. | |
115 | * | |
116 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
117 | * on whenever we have at least one other device in use. | |
118 | */ | |
119 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
120 | ||
1f47a77c HK |
121 | /* UART Component Parameter Register */ |
122 | #define LPSS_UART_CPR 0xF4 | |
123 | #define LPSS_UART_CPR_AFCE BIT(4) | |
124 | ||
06d86415 HK |
125 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
126 | { | |
088f1fd2 | 127 | unsigned int offset; |
1f47a77c | 128 | u32 val; |
06d86415 | 129 | |
088f1fd2 | 130 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
131 | val = readl(pdata->mmio_base + offset); |
132 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
133 | ||
134 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
135 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
136 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
137 | val = readl(pdata->mmio_base + offset); | |
138 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
139 | writel(val, pdata->mmio_base + offset); | |
140 | } | |
06d86415 HK |
141 | } |
142 | ||
3095794a | 143 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
144 | { |
145 | unsigned int offset; | |
146 | u32 val; | |
147 | ||
148 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
149 | val = readl(pdata->mmio_base + offset); | |
150 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
151 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
152 | } |
153 | ||
04434ab5 HG |
154 | /* |
155 | * BYT PWM used for backlight control by the i915 driver on systems without | |
156 | * the Crystal Cove PMIC. | |
157 | */ | |
158 | static struct pwm_lookup byt_pwm_lookup[] = { | |
159 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
160 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
161 | "pwm-lpss-platform"), | |
162 | }; | |
163 | ||
164 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
165 | { | |
dd242a08 HG |
166 | struct acpi_device *adev = pdata->adev; |
167 | ||
168 | /* Only call pwm_add_table for the first PWM controller */ | |
169 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
170 | return; | |
171 | ||
c975e472 | 172 | if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV)) |
04434ab5 HG |
173 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
174 | } | |
175 | ||
3095794a MW |
176 | #define LPSS_I2C_ENABLE 0x6c |
177 | ||
178 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
179 | { | |
86b62e5c HG |
180 | const char *uid_str = acpi_device_uid(pdata->adev); |
181 | acpi_handle handle = pdata->adev->handle; | |
182 | unsigned long long shared_host = 0; | |
183 | acpi_status status; | |
184 | long uid = 0; | |
185 | ||
186 | /* Expected to always be true, but better safe then sorry */ | |
187 | if (uid_str) | |
188 | uid = simple_strtol(uid_str, NULL, 10); | |
189 | ||
190 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ | |
191 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
192 | if (ACPI_SUCCESS(status) && shared_host && uid) | |
193 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
194 | ||
3095794a | 195 | lpss_deassert_reset(pdata); |
765bdd4e | 196 | |
03f09f73 HK |
197 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
198 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
199 | |
200 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 201 | } |
43218a1b | 202 | |
bf7696a1 HG |
203 | /* BSW PWM used for backlight control by the i915 driver */ |
204 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
205 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
206 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
207 | "pwm-lpss-platform"), | |
208 | }; | |
209 | ||
210 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
211 | { | |
dd242a08 HG |
212 | struct acpi_device *adev = pdata->adev; |
213 | ||
214 | /* Only call pwm_add_table for the first PWM controller */ | |
215 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
216 | return; | |
217 | ||
bf7696a1 HG |
218 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
219 | } | |
220 | ||
b2687cd7 | 221 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 222 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 223 | .prv_offset = 0x800, |
ed3a872e HK |
224 | }; |
225 | ||
b2687cd7 | 226 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 227 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 228 | .prv_offset = 0x800, |
2e0f8822 RW |
229 | }; |
230 | ||
a5565cf2 HK |
231 | static struct property_entry uart_properties[] = { |
232 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
233 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
234 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
235 | { }, | |
236 | }; | |
237 | ||
b2687cd7 | 238 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 239 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 240 | .clk_con_id = "baudclk", |
06d86415 | 241 | .prv_offset = 0x800, |
06d86415 | 242 | .setup = lpss_uart_setup, |
a5565cf2 | 243 | .properties = uart_properties, |
2e0f8822 RW |
244 | }; |
245 | ||
b2687cd7 | 246 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 247 | .flags = LPSS_LTR, |
2e0f8822 | 248 | .prv_offset = 0x1000, |
958c4eb2 | 249 | .prv_size_override = 0x1018, |
e1c74817 CCE |
250 | }; |
251 | ||
b2687cd7 | 252 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 253 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 254 | .prv_offset = 0x800, |
04434ab5 | 255 | .setup = byt_pwm_setup, |
e1c74817 CCE |
256 | }; |
257 | ||
b00855ae SK |
258 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
259 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
fdcb613d | 260 | .prv_offset = 0x800, |
bf7696a1 | 261 | .setup = bsw_pwm_setup, |
b00855ae SK |
262 | }; |
263 | ||
b2687cd7 | 264 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 265 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 266 | .clk_con_id = "baudclk", |
f6272170 | 267 | .prv_offset = 0x800, |
06d86415 | 268 | .setup = lpss_uart_setup, |
a5565cf2 | 269 | .properties = uart_properties, |
f6272170 MW |
270 | }; |
271 | ||
b00855ae SK |
272 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
273 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
274 | | LPSS_NO_D3_DELAY, | |
275 | .clk_con_id = "baudclk", | |
276 | .prv_offset = 0x800, | |
277 | .setup = lpss_uart_setup, | |
a5565cf2 | 278 | .properties = uart_properties, |
b00855ae SK |
279 | }; |
280 | ||
b2687cd7 | 281 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 282 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 283 | .prv_offset = 0x400, |
f6272170 MW |
284 | }; |
285 | ||
b2687cd7 | 286 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 287 | .flags = LPSS_CLK, |
f6272170 MW |
288 | }; |
289 | ||
b2687cd7 | 290 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 291 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 292 | .prv_offset = 0x800, |
03f09f73 | 293 | .setup = byt_i2c_setup, |
48402cee | 294 | .resume_from_noirq = true, |
1bfbd8eb AC |
295 | }; |
296 | ||
b00855ae SK |
297 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
298 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
299 | .prv_offset = 0x800, | |
300 | .setup = byt_i2c_setup, | |
48402cee | 301 | .resume_from_noirq = true, |
b00855ae SK |
302 | }; |
303 | ||
eebb3e8d | 304 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
305 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
306 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
307 | .prv_offset = 0x400, |
308 | .setup = lpss_deassert_reset, | |
309 | }; | |
310 | ||
eebb3e8d AS |
311 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
312 | ||
313 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
f2c4db1b | 314 | ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ |
4626d840 | 315 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ |
eebb3e8d AS |
316 | {} |
317 | }; | |
318 | ||
d6ddaaac RW |
319 | #else |
320 | ||
321 | #define LPSS_ADDR(desc) (0UL) | |
322 | ||
323 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
324 | ||
f58b082a | 325 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 326 | /* Generic LPSS devices */ |
d6ddaaac | 327 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 328 | |
f58b082a | 329 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
330 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
331 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
332 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
333 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
334 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
335 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
336 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
337 | { "INT33C7", }, |
338 | ||
f6272170 | 339 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
340 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
341 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
342 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
343 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
344 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 345 | { "INT33B2", }, |
20482d32 | 346 | { "INT33FC", }, |
f6272170 | 347 | |
1bfbd8eb | 348 | /* Braswell LPSS devices */ |
24071406 | 349 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae SK |
350 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
351 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 352 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 353 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 354 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 355 | |
b00855ae | 356 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
357 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
358 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
359 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
360 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
361 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
362 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
363 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
364 | { "INT3437", }, |
365 | ||
ff8c1af5 HK |
366 | /* Wildcat Point LPSS devices */ |
367 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 368 | |
f58b082a RW |
369 | { } |
370 | }; | |
371 | ||
d6ddaaac RW |
372 | #ifdef CONFIG_X86_INTEL_LPSS |
373 | ||
f58b082a RW |
374 | static int is_memory(struct acpi_resource *res, void *not_used) |
375 | { | |
376 | struct resource r; | |
377 | return !acpi_dev_resource_memory(res, &r); | |
378 | } | |
379 | ||
380 | /* LPSS main clock device. */ | |
381 | static struct platform_device *lpss_clk_dev; | |
382 | ||
383 | static inline void lpt_register_clock_device(void) | |
384 | { | |
385 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
386 | } | |
387 | ||
388 | static int register_device_clock(struct acpi_device *adev, | |
389 | struct lpss_private_data *pdata) | |
390 | { | |
391 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 392 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 393 | struct clk *clk; |
b59cc200 | 394 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
395 | const char *parent, *clk_name; |
396 | void __iomem *prv_base; | |
f58b082a RW |
397 | |
398 | if (!lpss_clk_dev) | |
399 | lpt_register_clock_device(); | |
400 | ||
b59cc200 RW |
401 | clk_data = platform_get_drvdata(lpss_clk_dev); |
402 | if (!clk_data) | |
403 | return -ENODEV; | |
b0d00f8b | 404 | clk = clk_data->clk; |
b59cc200 RW |
405 | |
406 | if (!pdata->mmio_base | |
2e0f8822 | 407 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
408 | return -ENODATA; |
409 | ||
f6272170 | 410 | parent = clk_data->name; |
ed3a872e | 411 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 412 | |
03f09f73 HK |
413 | if (pdata->fixed_clk_rate) { |
414 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
415 | pdata->fixed_clk_rate); | |
416 | goto out; | |
f6272170 MW |
417 | } |
418 | ||
ff8c1af5 | 419 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
420 | clk = clk_register_gate(NULL, devname, parent, 0, |
421 | prv_base, 0, 0, NULL); | |
422 | parent = devname; | |
423 | } | |
424 | ||
ff8c1af5 | 425 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
426 | /* Prevent division by zero */ |
427 | if (!readl(prv_base)) | |
428 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
429 | ||
430 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
431 | if (!clk_name) | |
432 | return -ENOMEM; | |
433 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
434 | 0, prv_base, | |
435 | 1, 15, 16, 15, 0, NULL); | |
436 | parent = clk_name; | |
437 | ||
438 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
439 | if (!clk_name) { | |
440 | kfree(parent); | |
441 | return -ENOMEM; | |
442 | } | |
443 | clk = clk_register_gate(NULL, clk_name, parent, | |
444 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
445 | prv_base, 31, 0, NULL); | |
446 | kfree(parent); | |
447 | kfree(clk_name); | |
f6272170 | 448 | } |
03f09f73 | 449 | out: |
f6272170 MW |
450 | if (IS_ERR(clk)) |
451 | return PTR_ERR(clk); | |
f58b082a | 452 | |
ed3a872e | 453 | pdata->clk = clk; |
fcf0789a | 454 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
455 | return 0; |
456 | } | |
457 | ||
e6ce0ce3 AH |
458 | struct lpss_device_links { |
459 | const char *supplier_hid; | |
460 | const char *supplier_uid; | |
461 | const char *consumer_hid; | |
462 | const char *consumer_uid; | |
463 | u32 flags; | |
464 | }; | |
465 | ||
466 | /* | |
467 | * The _DEP method is used to identify dependencies but instead of creating | |
468 | * device links for every handle in _DEP, only links in the following list are | |
469 | * created. That is necessary because, in the general case, _DEP can refer to | |
470 | * devices that might not have drivers, or that are on different buses, or where | |
471 | * the supplier is not enumerated until after the consumer is probed. | |
472 | */ | |
473 | static const struct lpss_device_links lpss_device_links[] = { | |
474 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, | |
bd0f4e34 | 475 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
2d71ee0c | 476 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
e6ce0ce3 AH |
477 | }; |
478 | ||
ea625ce1 | 479 | static bool hid_uid_match(struct acpi_device *adev, |
e6ce0ce3 AH |
480 | const char *hid2, const char *uid2) |
481 | { | |
ea625ce1 HG |
482 | const char *hid1 = acpi_device_hid(adev); |
483 | const char *uid1 = acpi_device_uid(adev); | |
484 | ||
a92a5563 HG |
485 | if (strcmp(hid1, hid2)) |
486 | return false; | |
487 | ||
488 | if (!uid2) | |
489 | return true; | |
490 | ||
491 | return uid1 && !strcmp(uid1, uid2); | |
e6ce0ce3 AH |
492 | } |
493 | ||
494 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, | |
495 | const struct lpss_device_links *link) | |
496 | { | |
ea625ce1 | 497 | return hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
498 | } |
499 | ||
500 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
501 | const struct lpss_device_links *link) | |
502 | { | |
ea625ce1 | 503 | return hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
504 | } |
505 | ||
506 | struct hid_uid { | |
507 | const char *hid; | |
508 | const char *uid; | |
509 | }; | |
510 | ||
418e3ea1 | 511 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
512 | { |
513 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 514 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
515 | |
516 | if (!adev) | |
517 | return 0; | |
518 | ||
ea625ce1 | 519 | return hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
520 | } |
521 | ||
522 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
523 | { | |
1e30124a HG |
524 | struct device *dev; |
525 | ||
e6ce0ce3 AH |
526 | struct hid_uid data = { |
527 | .hid = hid, | |
528 | .uid = uid, | |
529 | }; | |
530 | ||
1e30124a HG |
531 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
532 | if (dev) | |
533 | return dev; | |
534 | ||
535 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
536 | } |
537 | ||
538 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
539 | { | |
540 | struct acpi_handle_list dep_devices; | |
541 | acpi_status status; | |
542 | int i; | |
543 | ||
544 | if (!acpi_has_method(adev->handle, "_DEP")) | |
545 | return false; | |
546 | ||
547 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
548 | &dep_devices); | |
549 | if (ACPI_FAILURE(status)) { | |
550 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
551 | return false; | |
552 | } | |
553 | ||
554 | for (i = 0; i < dep_devices.count; i++) { | |
555 | if (dep_devices.handles[i] == handle) | |
556 | return true; | |
557 | } | |
558 | ||
559 | return false; | |
560 | } | |
561 | ||
562 | static void acpi_lpss_link_consumer(struct device *dev1, | |
563 | const struct lpss_device_links *link) | |
564 | { | |
565 | struct device *dev2; | |
566 | ||
567 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
568 | if (!dev2) | |
569 | return; | |
570 | ||
571 | if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
572 | device_link_add(dev2, dev1, link->flags); | |
573 | ||
574 | put_device(dev2); | |
575 | } | |
576 | ||
577 | static void acpi_lpss_link_supplier(struct device *dev1, | |
578 | const struct lpss_device_links *link) | |
579 | { | |
580 | struct device *dev2; | |
581 | ||
582 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
583 | if (!dev2) | |
584 | return; | |
585 | ||
586 | if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
587 | device_link_add(dev1, dev2, link->flags); | |
588 | ||
589 | put_device(dev2); | |
590 | } | |
591 | ||
592 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
593 | struct platform_device *pdev) | |
594 | { | |
595 | int i; | |
596 | ||
597 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
598 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
599 | ||
600 | if (acpi_lpss_is_supplier(adev, link)) | |
601 | acpi_lpss_link_consumer(&pdev->dev, link); | |
602 | ||
603 | if (acpi_lpss_is_consumer(adev, link)) | |
604 | acpi_lpss_link_supplier(&pdev->dev, link); | |
605 | } | |
606 | } | |
607 | ||
f58b082a RW |
608 | static int acpi_lpss_create_device(struct acpi_device *adev, |
609 | const struct acpi_device_id *id) | |
610 | { | |
b2687cd7 | 611 | const struct lpss_device_desc *dev_desc; |
f58b082a | 612 | struct lpss_private_data *pdata; |
90e97820 | 613 | struct resource_entry *rentry; |
f58b082a | 614 | struct list_head resource_list; |
8ce62f85 | 615 | struct platform_device *pdev; |
f58b082a RW |
616 | int ret; |
617 | ||
b2687cd7 | 618 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 619 | if (!dev_desc) { |
1571875b | 620 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
621 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
622 | } | |
f58b082a RW |
623 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
624 | if (!pdata) | |
625 | return -ENOMEM; | |
626 | ||
627 | INIT_LIST_HEAD(&resource_list); | |
628 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
629 | if (ret < 0) | |
630 | goto err_out; | |
631 | ||
632 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 633 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
634 | if (dev_desc->prv_size_override) |
635 | pdata->mmio_size = dev_desc->prv_size_override; | |
636 | else | |
90e97820 JL |
637 | pdata->mmio_size = resource_size(rentry->res); |
638 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 639 | pdata->mmio_size); |
f58b082a RW |
640 | break; |
641 | } | |
642 | ||
643 | acpi_dev_free_resource_list(&resource_list); | |
644 | ||
d3e13ff3 | 645 | if (!pdata->mmio_base) { |
e1681599 HG |
646 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
647 | adev->pnp.type.platform_id = 0; | |
a4bb2b49 RT |
648 | /* Skip the device, but continue the namespace scan. */ |
649 | ret = 0; | |
d3e13ff3 RW |
650 | goto err_out; |
651 | } | |
652 | ||
dd242a08 | 653 | pdata->adev = adev; |
af65cfe9 MW |
654 | pdata->dev_desc = dev_desc; |
655 | ||
03f09f73 HK |
656 | if (dev_desc->setup) |
657 | dev_desc->setup(pdata); | |
658 | ||
ff8c1af5 | 659 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
660 | ret = register_device_clock(adev, pdata); |
661 | if (ret) { | |
b9e95fc6 RW |
662 | /* Skip the device, but continue the namespace scan. */ |
663 | ret = 0; | |
664 | goto err_out; | |
f58b082a RW |
665 | } |
666 | } | |
667 | ||
b9e95fc6 RW |
668 | /* |
669 | * This works around a known issue in ACPI tables where LPSS devices | |
670 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
671 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
672 | */ | |
1a2fa02f | 673 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 674 | |
f58b082a | 675 | adev->driver_data = pdata; |
1571875b | 676 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 677 | if (!IS_ERR_OR_NULL(pdev)) { |
e6ce0ce3 | 678 | acpi_lpss_create_device_links(adev, pdev); |
8ce62f85 RW |
679 | return 1; |
680 | } | |
f58b082a | 681 | |
8ce62f85 | 682 | ret = PTR_ERR(pdev); |
f58b082a RW |
683 | adev->driver_data = NULL; |
684 | ||
685 | err_out: | |
686 | kfree(pdata); | |
687 | return ret; | |
688 | } | |
689 | ||
1a8f8351 RW |
690 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
691 | { | |
692 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
693 | } | |
694 | ||
695 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
696 | unsigned int reg) | |
697 | { | |
698 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
699 | } | |
700 | ||
2e0f8822 RW |
701 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
702 | { | |
703 | struct acpi_device *adev; | |
704 | struct lpss_private_data *pdata; | |
705 | unsigned long flags; | |
706 | int ret; | |
707 | ||
708 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
709 | if (WARN_ON(ret)) | |
710 | return ret; | |
711 | ||
712 | spin_lock_irqsave(&dev->power.lock, flags); | |
713 | if (pm_runtime_suspended(dev)) { | |
714 | ret = -EAGAIN; | |
715 | goto out; | |
716 | } | |
717 | pdata = acpi_driver_data(adev); | |
718 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
719 | ret = -ENODEV; | |
720 | goto out; | |
721 | } | |
1a8f8351 | 722 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
723 | |
724 | out: | |
725 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
726 | return ret; | |
727 | } | |
728 | ||
729 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
730 | char *buf) | |
731 | { | |
732 | u32 ltr_value = 0; | |
733 | unsigned int reg; | |
734 | int ret; | |
735 | ||
736 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
737 | ret = lpss_reg_read(dev, reg, <r_value); | |
738 | if (ret) | |
739 | return ret; | |
740 | ||
741 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
742 | } | |
743 | ||
744 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
745 | struct device_attribute *attr, char *buf) | |
746 | { | |
747 | u32 ltr_mode = 0; | |
748 | char *outstr; | |
749 | int ret; | |
750 | ||
751 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
752 | if (ret) | |
753 | return ret; | |
754 | ||
755 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
756 | return sprintf(buf, "%s\n", outstr); | |
757 | } | |
758 | ||
759 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
760 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
761 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
762 | ||
763 | static struct attribute *lpss_attrs[] = { | |
764 | &dev_attr_auto_ltr.attr, | |
765 | &dev_attr_sw_ltr.attr, | |
766 | &dev_attr_ltr_mode.attr, | |
767 | NULL, | |
768 | }; | |
769 | ||
31945d0e | 770 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
771 | .attrs = lpss_attrs, |
772 | .name = "lpss_ltr", | |
773 | }; | |
774 | ||
1a8f8351 RW |
775 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
776 | { | |
777 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
778 | u32 ltr_mode, ltr_val; | |
779 | ||
780 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
781 | if (val < 0) { | |
782 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
783 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
784 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
785 | } | |
786 | return; | |
787 | } | |
788 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
789 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
790 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
791 | val = LPSS_LTR_MAX_VAL; | |
792 | } else if (val > LPSS_LTR_MAX_VAL) { | |
793 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
794 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
795 | } else { | |
796 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
797 | } | |
798 | ltr_val |= val; | |
799 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
800 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
801 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
802 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
803 | } | |
804 | } | |
805 | ||
c78b0830 HK |
806 | #ifdef CONFIG_PM |
807 | /** | |
808 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
809 | * @dev: LPSS device | |
cb39dcdd | 810 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
811 | * |
812 | * Most LPSS devices have private registers which may loose their context when | |
813 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
814 | * prv_reg_ctx array. | |
815 | */ | |
cb39dcdd AS |
816 | static void acpi_lpss_save_ctx(struct device *dev, |
817 | struct lpss_private_data *pdata) | |
c78b0830 | 818 | { |
c78b0830 HK |
819 | unsigned int i; |
820 | ||
821 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
822 | unsigned long offset = i * sizeof(u32); | |
823 | ||
824 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
825 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
826 | pdata->prv_reg_ctx[i], offset); | |
827 | } | |
828 | } | |
829 | ||
830 | /** | |
831 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
832 | * @dev: LPSS device | |
cb39dcdd | 833 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
834 | * |
835 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
836 | */ | |
cb39dcdd AS |
837 | static void acpi_lpss_restore_ctx(struct device *dev, |
838 | struct lpss_private_data *pdata) | |
c78b0830 | 839 | { |
c78b0830 HK |
840 | unsigned int i; |
841 | ||
02b98540 AS |
842 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
843 | unsigned long offset = i * sizeof(u32); | |
844 | ||
845 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
846 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
847 | pdata->prv_reg_ctx[i], offset); | |
848 | } | |
849 | } | |
850 | ||
851 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
852 | { | |
c78b0830 HK |
853 | /* |
854 | * The following delay is needed or the subsequent write operations may | |
855 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
856 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 857 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 858 | */ |
b00855ae SK |
859 | unsigned int delay = 10; /* default 10ms delay */ |
860 | ||
861 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
862 | delay = 0; | |
863 | ||
864 | msleep(delay); | |
c78b0830 HK |
865 | } |
866 | ||
c3a49cf3 AS |
867 | static int acpi_lpss_activate(struct device *dev) |
868 | { | |
869 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
870 | int ret; | |
871 | ||
63705c40 | 872 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
873 | if (ret) |
874 | return ret; | |
875 | ||
876 | acpi_lpss_d3_to_d0_delay(pdata); | |
877 | ||
878 | /* | |
879 | * This is called only on ->probe() stage where a device is either in | |
880 | * known state defined by BIOS or most likely powered off. Due to this | |
881 | * we have to deassert reset line to be sure that ->probe() will | |
882 | * recognize the device. | |
883 | */ | |
884 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
885 | lpss_deassert_reset(pdata); | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | static void acpi_lpss_dismiss(struct device *dev) | |
891 | { | |
cbe25ce3 | 892 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
893 | } |
894 | ||
eebb3e8d AS |
895 | /* IOSF SB for LPSS island */ |
896 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
897 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
898 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
899 | ||
900 | #define LPSS_IOSF_PMCSR 0x84 | |
901 | #define LPSS_PMCSR_D0 0 | |
902 | #define LPSS_PMCSR_D3hot 3 | |
903 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
904 | ||
905 | #define LPSS_IOSF_GPIODEF0 0x154 | |
906 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
907 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
908 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 909 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
910 | |
911 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 912 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
913 | |
914 | static void lpss_iosf_enter_d3_state(void) | |
915 | { | |
916 | u32 value1 = 0; | |
d132d6d5 | 917 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
918 | u32 value2 = LPSS_PMCSR_D3hot; |
919 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
920 | /* | |
921 | * PMC provides an information about actual status of the LPSS devices. | |
922 | * Here we read the values related to LPSS power island, i.e. LPSS | |
923 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
924 | */ | |
86b62e5c | 925 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
926 | int ret; |
927 | ||
928 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
929 | if (ret) | |
930 | return; | |
931 | ||
932 | mutex_lock(&lpss_iosf_mutex); | |
933 | ||
934 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
935 | if (ret) | |
936 | goto exit; | |
937 | ||
938 | /* | |
939 | * Get the status of entire LPSS power island per device basis. | |
940 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
941 | * are already in D3hot. | |
942 | */ | |
86b62e5c | 943 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
944 | if (pmc_status) |
945 | goto exit; | |
946 | ||
947 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
948 | LPSS_IOSF_PMCSR, value2, mask2); | |
949 | ||
950 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
951 | LPSS_IOSF_PMCSR, value2, mask2); | |
952 | ||
953 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
954 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
955 | |
956 | lpss_iosf_d3_entered = true; | |
957 | ||
eebb3e8d AS |
958 | exit: |
959 | mutex_unlock(&lpss_iosf_mutex); | |
960 | } | |
961 | ||
962 | static void lpss_iosf_exit_d3_state(void) | |
963 | { | |
d132d6d5 AS |
964 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
965 | LPSS_GPIODEF0_DMA_LLP; | |
966 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
967 | u32 value2 = LPSS_PMCSR_D0; |
968 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
969 | ||
970 | mutex_lock(&lpss_iosf_mutex); | |
971 | ||
12864ff8 RW |
972 | if (!lpss_iosf_d3_entered) |
973 | goto exit; | |
974 | ||
975 | lpss_iosf_d3_entered = false; | |
976 | ||
eebb3e8d AS |
977 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
978 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
979 | ||
980 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
981 | LPSS_IOSF_PMCSR, value2, mask2); | |
982 | ||
983 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
984 | LPSS_IOSF_PMCSR, value2, mask2); | |
985 | ||
12864ff8 | 986 | exit: |
eebb3e8d AS |
987 | mutex_unlock(&lpss_iosf_mutex); |
988 | } | |
989 | ||
12864ff8 | 990 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 991 | { |
cb39dcdd AS |
992 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
993 | int ret; | |
c78b0830 | 994 | |
cb39dcdd AS |
995 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
996 | acpi_lpss_save_ctx(dev, pdata); | |
997 | ||
a192aa92 | 998 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
999 | |
1000 | /* | |
1001 | * This call must be last in the sequence, otherwise PMC will return | |
1002 | * wrong status for devices being about to be powered off. See | |
1003 | * lpss_iosf_enter_d3_state() for further information. | |
1004 | */ | |
12864ff8 | 1005 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1006 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1007 | lpss_iosf_enter_d3_state(); |
1008 | ||
1009 | return ret; | |
c78b0830 HK |
1010 | } |
1011 | ||
12864ff8 | 1012 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1013 | { |
cb39dcdd AS |
1014 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1015 | int ret; | |
c78b0830 | 1016 | |
eebb3e8d AS |
1017 | /* |
1018 | * This call is kept first to be in symmetry with | |
1019 | * acpi_lpss_runtime_suspend() one. | |
1020 | */ | |
12864ff8 | 1021 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1022 | lpss_iosf_exit_d3_state(); |
1023 | ||
63705c40 | 1024 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1025 | if (ret) |
1026 | return ret; | |
1027 | ||
02b98540 AS |
1028 | acpi_lpss_d3_to_d0_delay(pdata); |
1029 | ||
cb39dcdd AS |
1030 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1031 | acpi_lpss_restore_ctx(dev, pdata); | |
1032 | ||
a192aa92 RW |
1033 | return 0; |
1034 | } | |
1035 | ||
1036 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1037 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1038 | { |
05087360 RW |
1039 | int ret; |
1040 | ||
1041 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
1042 | return 0; | |
a192aa92 | 1043 | |
05087360 | 1044 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1045 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1046 | } |
1047 | ||
48402cee HG |
1048 | static int acpi_lpss_suspend_late(struct device *dev) |
1049 | { | |
1050 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1051 | ||
1052 | if (pdata->dev_desc->resume_from_noirq) | |
1053 | return 0; | |
1054 | ||
1055 | return acpi_lpss_do_suspend_late(dev); | |
1056 | } | |
1057 | ||
1058 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1059 | { | |
1060 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1061 | int ret; | |
1062 | ||
1063 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1064 | /* |
1065 | * The driver's ->suspend_late callback will be invoked by | |
1066 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1067 | * driver really wanted to run that code in ->suspend_noirq, but | |
1068 | * it could not run after acpi_dev_suspend() and the driver | |
1069 | * expected the latter to be called in the "late" phase. | |
1070 | */ | |
48402cee HG |
1071 | ret = acpi_lpss_do_suspend_late(dev); |
1072 | if (ret) | |
1073 | return ret; | |
1074 | } | |
1075 | ||
1076 | return acpi_subsys_suspend_noirq(dev); | |
1077 | } | |
1078 | ||
1079 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1080 | { |
12864ff8 | 1081 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1082 | |
1083 | return ret ? ret : pm_generic_resume_early(dev); | |
1084 | } | |
48402cee HG |
1085 | |
1086 | static int acpi_lpss_resume_early(struct device *dev) | |
1087 | { | |
1088 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1089 | ||
1090 | if (pdata->dev_desc->resume_from_noirq) | |
1091 | return 0; | |
1092 | ||
1093 | return acpi_lpss_do_resume_early(dev); | |
1094 | } | |
1095 | ||
1096 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1097 | { | |
1098 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1099 | int ret; | |
1100 | ||
3cd7957e RW |
1101 | /* Follow acpi_subsys_resume_noirq(). */ |
1102 | if (dev_pm_may_skip_resume(dev)) | |
1103 | return 0; | |
1104 | ||
1105 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
1106 | pm_runtime_set_active(dev); | |
1107 | ||
1108 | ret = pm_generic_resume_noirq(dev); | |
48402cee HG |
1109 | if (ret) |
1110 | return ret; | |
1111 | ||
3cd7957e RW |
1112 | if (!pdata->dev_desc->resume_from_noirq) |
1113 | return 0; | |
48402cee | 1114 | |
3cd7957e RW |
1115 | /* |
1116 | * The driver's ->resume_early callback will be invoked by | |
1117 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1118 | * really wanted to run that code in ->resume_noirq, but it could not | |
1119 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1120 | * called in the "early" phase. | |
1121 | */ | |
1122 | return acpi_lpss_do_resume_early(dev); | |
1123 | } | |
1124 | ||
1125 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1126 | { | |
1127 | int ret = acpi_lpss_resume(dev); | |
1128 | ||
1129 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1130 | } |
1131 | ||
3cd7957e RW |
1132 | static int acpi_lpss_restore_early(struct device *dev) |
1133 | { | |
1134 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1135 | ||
1136 | if (pdata->dev_desc->resume_from_noirq) | |
1137 | return 0; | |
1138 | ||
1139 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1140 | } |
1141 | ||
3cd7957e RW |
1142 | static int acpi_lpss_restore_noirq(struct device *dev) |
1143 | { | |
1144 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1145 | int ret; | |
1146 | ||
1147 | ret = pm_generic_restore_noirq(dev); | |
1148 | if (ret) | |
1149 | return ret; | |
1150 | ||
1151 | if (!pdata->dev_desc->resume_from_noirq) | |
1152 | return 0; | |
1153 | ||
1154 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1155 | return acpi_lpss_do_restore_early(dev); | |
1156 | } | |
c95b7595 RW |
1157 | |
1158 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1159 | { | |
1160 | int ret = pm_generic_poweroff_late(dev); | |
1161 | ||
1162 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1163 | } | |
1164 | ||
1165 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1166 | { | |
1167 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1168 | ||
1169 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
1170 | return 0; | |
1171 | ||
1172 | if (pdata->dev_desc->resume_from_noirq) | |
1173 | return 0; | |
1174 | ||
1175 | return acpi_lpss_do_poweroff_late(dev); | |
1176 | } | |
1177 | ||
1178 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1179 | { | |
1180 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1181 | ||
1182 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
1183 | return 0; | |
1184 | ||
1185 | if (pdata->dev_desc->resume_from_noirq) { | |
1186 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1187 | int ret = acpi_lpss_do_poweroff_late(dev); | |
1188 | if (ret) | |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | return pm_generic_poweroff_noirq(dev); | |
1193 | } | |
a192aa92 RW |
1194 | #endif /* CONFIG_PM_SLEEP */ |
1195 | ||
1196 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1197 | { | |
1198 | int ret = pm_generic_runtime_suspend(dev); | |
1199 | ||
1200 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1201 | } | |
1202 | ||
1203 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1204 | { | |
12864ff8 | 1205 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1206 | |
1207 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1208 | } |
c78b0830 HK |
1209 | #endif /* CONFIG_PM */ |
1210 | ||
1211 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1212 | #ifdef CONFIG_PM |
1213 | .activate = acpi_lpss_activate, | |
1214 | .dismiss = acpi_lpss_dismiss, | |
1215 | #endif | |
c78b0830 | 1216 | .ops = { |
5de21bb9 | 1217 | #ifdef CONFIG_PM |
c78b0830 | 1218 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1219 | .prepare = acpi_subsys_prepare, |
e4da817d | 1220 | .complete = acpi_subsys_complete, |
c78b0830 | 1221 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1222 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1223 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1224 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1225 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1226 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1227 | .poweroff = acpi_subsys_poweroff, |
1228 | .poweroff_late = acpi_lpss_poweroff_late, | |
1229 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1230 | .restore_noirq = acpi_lpss_restore_noirq, |
1231 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1232 | #endif |
c78b0830 HK |
1233 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1234 | .runtime_resume = acpi_lpss_runtime_resume, | |
1235 | #endif | |
1236 | }, | |
1237 | }; | |
1238 | ||
2e0f8822 RW |
1239 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1240 | unsigned long action, void *data) | |
1241 | { | |
1242 | struct platform_device *pdev = to_platform_device(data); | |
1243 | struct lpss_private_data *pdata; | |
1244 | struct acpi_device *adev; | |
1245 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1246 | |
1247 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1248 | if (!id || !id->driver_data) | |
1249 | return 0; | |
1250 | ||
1251 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1252 | return 0; | |
1253 | ||
1254 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1255 | if (!pdata) |
2e0f8822 RW |
1256 | return 0; |
1257 | ||
cb39dcdd AS |
1258 | if (pdata->mmio_base && |
1259 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1260 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1261 | return 0; | |
1262 | } | |
1263 | ||
c78b0830 | 1264 | switch (action) { |
de16d552 | 1265 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1266 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1267 | break; |
de16d552 | 1268 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1269 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1270 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1271 | break; |
1272 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1273 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1274 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1275 | return sysfs_create_group(&pdev->dev.kobj, |
1276 | &lpss_attr_group); | |
01ac170b | 1277 | break; |
c78b0830 | 1278 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1279 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1280 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1281 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1282 | break; |
c78b0830 HK |
1283 | default: |
1284 | break; | |
1285 | } | |
2e0f8822 | 1286 | |
c78b0830 | 1287 | return 0; |
2e0f8822 RW |
1288 | } |
1289 | ||
1290 | static struct notifier_block acpi_lpss_nb = { | |
1291 | .notifier_call = acpi_lpss_platform_notify, | |
1292 | }; | |
1293 | ||
1a8f8351 RW |
1294 | static void acpi_lpss_bind(struct device *dev) |
1295 | { | |
1296 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1297 | ||
ff8c1af5 | 1298 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1299 | return; |
1300 | ||
1301 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1302 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1303 | else | |
1304 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1305 | } | |
1306 | ||
1307 | static void acpi_lpss_unbind(struct device *dev) | |
1308 | { | |
1309 | dev->power.set_latency_tolerance = NULL; | |
1310 | } | |
1311 | ||
f58b082a RW |
1312 | static struct acpi_scan_handler lpss_handler = { |
1313 | .ids = acpi_lpss_device_ids, | |
1314 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1315 | .bind = acpi_lpss_bind, |
1316 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1317 | }; |
1318 | ||
1319 | void __init acpi_lpss_init(void) | |
1320 | { | |
eebb3e8d AS |
1321 | const struct x86_cpu_id *id; |
1322 | int ret; | |
1323 | ||
1324 | ret = lpt_clk_init(); | |
1325 | if (ret) | |
1326 | return; | |
1327 | ||
1328 | id = x86_match_cpu(lpss_cpu_ids); | |
1329 | if (id) | |
1330 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1331 | ||
1332 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1333 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1334 | } |
d6ddaaac RW |
1335 | |
1336 | #else | |
1337 | ||
1338 | static struct acpi_scan_handler lpss_handler = { | |
1339 | .ids = acpi_lpss_device_ids, | |
1340 | }; | |
1341 | ||
1342 | void __init acpi_lpss_init(void) | |
1343 | { | |
1344 | acpi_scan_add_handler(&lpss_handler); | |
1345 | } | |
1346 | ||
1347 | #endif /* CONFIG_X86_INTEL_LPSS */ |