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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
6025e2fa | 13 | #include <linux/dmi.h> |
f58b082a RW |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
eebb3e8d | 16 | #include <linux/mutex.h> |
1e30124a | 17 | #include <linux/pci.h> |
f58b082a | 18 | #include <linux/platform_device.h> |
a9443a63 | 19 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 20 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
bf7696a1 | 23 | #include <linux/pwm.h> |
620c803f | 24 | #include <linux/pxa2xx_ssp.h> |
a09c5913 | 25 | #include <linux/suspend.h> |
c78b0830 | 26 | #include <linux/delay.h> |
f58b082a RW |
27 | |
28 | #include "internal.h" | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
15aa5e4c HG |
69 | /* |
70 | * For some devices the DSDT AML code for another device turns off the device | |
71 | * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) | |
72 | * as ctx register values. | |
73 | * Luckily these devices always use the same ctx register values, so we can | |
74 | * work around this by saving the ctx registers once on activation. | |
75 | */ | |
76 | #define LPSS_SAVE_CTX_ONCE BIT(5) | |
77 | #define LPSS_NO_D3_DELAY BIT(6) | |
f6272170 | 78 | |
06d86415 | 79 | struct lpss_private_data; |
f58b082a RW |
80 | |
81 | struct lpss_device_desc { | |
ff8c1af5 | 82 | unsigned int flags; |
fcf0789a | 83 | const char *clk_con_id; |
2e0f8822 | 84 | unsigned int prv_offset; |
958c4eb2 | 85 | size_t prv_size_override; |
f167c1a1 | 86 | const struct property_entry *properties; |
06d86415 | 87 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 88 | bool resume_from_noirq; |
f58b082a RW |
89 | }; |
90 | ||
eebb3e8d | 91 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 92 | .flags = LPSS_CLK, |
b59cc200 RW |
93 | }; |
94 | ||
f58b082a | 95 | struct lpss_private_data { |
dd242a08 | 96 | struct acpi_device *adev; |
f58b082a RW |
97 | void __iomem *mmio_base; |
98 | resource_size_t mmio_size; | |
03f09f73 | 99 | unsigned int fixed_clk_rate; |
f58b082a RW |
100 | struct clk *clk; |
101 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 102 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
103 | }; |
104 | ||
86b62e5c HG |
105 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
106 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
107 | ||
eebb3e8d AS |
108 | /* LPSS run time quirks */ |
109 | static unsigned int lpss_quirks; | |
110 | ||
111 | /* | |
112 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
113 | * | |
fa9e93b1 | 114 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
115 | * it can be powered off automatically whenever the last LPSS device goes down. |
116 | * In case of no power any access to the DMA controller will hang the system. | |
117 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
118 | * well as on ASuS T100TA transformer. | |
119 | * | |
120 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
121 | * on whenever we have at least one other device in use. | |
122 | */ | |
123 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
124 | ||
1f47a77c HK |
125 | /* UART Component Parameter Register */ |
126 | #define LPSS_UART_CPR 0xF4 | |
127 | #define LPSS_UART_CPR_AFCE BIT(4) | |
128 | ||
06d86415 HK |
129 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
130 | { | |
088f1fd2 | 131 | unsigned int offset; |
1f47a77c | 132 | u32 val; |
06d86415 | 133 | |
088f1fd2 | 134 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
135 | val = readl(pdata->mmio_base + offset); |
136 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
137 | ||
138 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
139 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
140 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
141 | val = readl(pdata->mmio_base + offset); | |
142 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
143 | writel(val, pdata->mmio_base + offset); | |
144 | } | |
06d86415 HK |
145 | } |
146 | ||
3095794a | 147 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
148 | { |
149 | unsigned int offset; | |
150 | u32 val; | |
151 | ||
152 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
153 | val = readl(pdata->mmio_base + offset); | |
154 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
155 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
156 | } |
157 | ||
04434ab5 HG |
158 | /* |
159 | * BYT PWM used for backlight control by the i915 driver on systems without | |
160 | * the Crystal Cove PMIC. | |
161 | */ | |
162 | static struct pwm_lookup byt_pwm_lookup[] = { | |
163 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
b2147a3a | 164 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
04434ab5 HG |
165 | "pwm-lpss-platform"), |
166 | }; | |
167 | ||
168 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
169 | { | |
2a036e48 | 170 | u64 uid; |
dd242a08 HG |
171 | |
172 | /* Only call pwm_add_table for the first PWM controller */ | |
2a036e48 | 173 | if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) |
dd242a08 HG |
174 | return; |
175 | ||
b2147a3a | 176 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
04434ab5 HG |
177 | } |
178 | ||
3095794a MW |
179 | #define LPSS_I2C_ENABLE 0x6c |
180 | ||
181 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
182 | { | |
86b62e5c HG |
183 | acpi_handle handle = pdata->adev->handle; |
184 | unsigned long long shared_host = 0; | |
185 | acpi_status status; | |
2a036e48 | 186 | u64 uid; |
86b62e5c | 187 | |
2a036e48 AS |
188 | /* Expected to always be successfull, but better safe then sorry */ |
189 | if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) { | |
8e3ecc68 LS |
190 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ |
191 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
192 | if (ACPI_SUCCESS(status) && shared_host) | |
193 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
194 | } | |
86b62e5c | 195 | |
3095794a | 196 | lpss_deassert_reset(pdata); |
765bdd4e | 197 | |
03f09f73 HK |
198 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
199 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
200 | |
201 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 202 | } |
43218a1b | 203 | |
fa578bf5 HG |
204 | /* |
205 | * BSW PWM1 is used for backlight control by the i915 driver | |
206 | * BSW PWM2 is used for backlight control for fixed (etched into the glass) | |
207 | * touch controls on some models. These touch-controls have specialized | |
208 | * drivers which know they need the "pwm_soc_lpss_2" con-id. | |
209 | */ | |
bf7696a1 HG |
210 | static struct pwm_lookup bsw_pwm_lookup[] = { |
211 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
b2147a3a | 212 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
bf7696a1 | 213 | "pwm-lpss-platform"), |
fa578bf5 HG |
214 | PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL, |
215 | "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL, | |
216 | "pwm-lpss-platform"), | |
bf7696a1 HG |
217 | }; |
218 | ||
219 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
220 | { | |
2a036e48 | 221 | u64 uid; |
dd242a08 HG |
222 | |
223 | /* Only call pwm_add_table for the first PWM controller */ | |
2a036e48 | 224 | if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) |
dd242a08 HG |
225 | return; |
226 | ||
bf7696a1 HG |
227 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
228 | } | |
229 | ||
620c803f AS |
230 | static const struct property_entry lpt_spi_properties[] = { |
231 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), | |
232 | { } | |
233 | }; | |
234 | ||
235 | static const struct lpss_device_desc lpt_spi_dev_desc = { | |
57b30064 JN |
236 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
237 | | LPSS_SAVE_CTX, | |
ed3a872e | 238 | .prv_offset = 0x800, |
620c803f | 239 | .properties = lpt_spi_properties, |
ed3a872e HK |
240 | }; |
241 | ||
b2687cd7 | 242 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
57b30064 | 243 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, |
2e0f8822 | 244 | .prv_offset = 0x800, |
2e0f8822 RW |
245 | }; |
246 | ||
a5565cf2 HK |
247 | static struct property_entry uart_properties[] = { |
248 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
249 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
250 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
251 | { }, | |
252 | }; | |
253 | ||
b2687cd7 | 254 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
57b30064 JN |
255 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
256 | | LPSS_SAVE_CTX, | |
fcf0789a | 257 | .clk_con_id = "baudclk", |
06d86415 | 258 | .prv_offset = 0x800, |
06d86415 | 259 | .setup = lpss_uart_setup, |
a5565cf2 | 260 | .properties = uart_properties, |
2e0f8822 RW |
261 | }; |
262 | ||
b2687cd7 | 263 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 264 | .flags = LPSS_LTR, |
2e0f8822 | 265 | .prv_offset = 0x1000, |
958c4eb2 | 266 | .prv_size_override = 0x1018, |
e1c74817 CCE |
267 | }; |
268 | ||
b2687cd7 | 269 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 270 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 271 | .prv_offset = 0x800, |
04434ab5 | 272 | .setup = byt_pwm_setup, |
e1c74817 CCE |
273 | }; |
274 | ||
b00855ae | 275 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
15aa5e4c | 276 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, |
fdcb613d | 277 | .prv_offset = 0x800, |
bf7696a1 | 278 | .setup = bsw_pwm_setup, |
5e31ee84 | 279 | .resume_from_noirq = true, |
b00855ae SK |
280 | }; |
281 | ||
03c57b01 HG |
282 | static const struct lpss_device_desc bsw_pwm2_dev_desc = { |
283 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, | |
284 | .prv_offset = 0x800, | |
285 | .resume_from_noirq = true, | |
286 | }; | |
287 | ||
b2687cd7 | 288 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 289 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 290 | .clk_con_id = "baudclk", |
f6272170 | 291 | .prv_offset = 0x800, |
06d86415 | 292 | .setup = lpss_uart_setup, |
a5565cf2 | 293 | .properties = uart_properties, |
f6272170 MW |
294 | }; |
295 | ||
b00855ae SK |
296 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
297 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
298 | | LPSS_NO_D3_DELAY, | |
299 | .clk_con_id = "baudclk", | |
300 | .prv_offset = 0x800, | |
301 | .setup = lpss_uart_setup, | |
a5565cf2 | 302 | .properties = uart_properties, |
b00855ae SK |
303 | }; |
304 | ||
620c803f AS |
305 | static const struct property_entry byt_spi_properties[] = { |
306 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), | |
307 | { } | |
308 | }; | |
309 | ||
b2687cd7 | 310 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 311 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 312 | .prv_offset = 0x400, |
620c803f | 313 | .properties = byt_spi_properties, |
f6272170 MW |
314 | }; |
315 | ||
b2687cd7 | 316 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 317 | .flags = LPSS_CLK, |
f6272170 MW |
318 | }; |
319 | ||
b2687cd7 | 320 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 321 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 322 | .prv_offset = 0x800, |
03f09f73 | 323 | .setup = byt_i2c_setup, |
48402cee | 324 | .resume_from_noirq = true, |
1bfbd8eb AC |
325 | }; |
326 | ||
b00855ae SK |
327 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
328 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
329 | .prv_offset = 0x800, | |
330 | .setup = byt_i2c_setup, | |
48402cee | 331 | .resume_from_noirq = true, |
b00855ae SK |
332 | }; |
333 | ||
620c803f AS |
334 | static const struct property_entry bsw_spi_properties[] = { |
335 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), | |
336 | { } | |
337 | }; | |
338 | ||
eebb3e8d | 339 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
340 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
341 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
342 | .prv_offset = 0x400, |
343 | .setup = lpss_deassert_reset, | |
620c803f | 344 | .properties = bsw_spi_properties, |
3095794a MW |
345 | }; |
346 | ||
eebb3e8d | 347 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
e36cf2f7 TG |
348 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), |
349 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), | |
eebb3e8d AS |
350 | {} |
351 | }; | |
352 | ||
d6ddaaac RW |
353 | #else |
354 | ||
355 | #define LPSS_ADDR(desc) (0UL) | |
356 | ||
357 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
358 | ||
f58b082a | 359 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 360 | /* Generic LPSS devices */ |
d6ddaaac | 361 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 362 | |
f58b082a | 363 | /* Lynxpoint LPSS devices */ |
620c803f AS |
364 | { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, |
365 | { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
366 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, |
367 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
368 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
369 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
370 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a | 371 | |
f6272170 | 372 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
373 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
374 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
375 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
376 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
377 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 378 | |
1bfbd8eb | 379 | /* Braswell LPSS devices */ |
24071406 | 380 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 381 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
03c57b01 | 382 | { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) }, |
b00855ae | 383 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, |
3095794a | 384 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 385 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 386 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 387 | |
b00855ae | 388 | /* Broadwell LPSS devices */ |
620c803f AS |
389 | { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, |
390 | { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
391 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, |
392 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
393 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
394 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
395 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 | 396 | |
ff8c1af5 | 397 | /* Wildcat Point LPSS devices */ |
620c803f | 398 | { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, |
43218a1b | 399 | |
f58b082a RW |
400 | { } |
401 | }; | |
402 | ||
d6ddaaac RW |
403 | #ifdef CONFIG_X86_INTEL_LPSS |
404 | ||
f58b082a RW |
405 | /* LPSS main clock device. */ |
406 | static struct platform_device *lpss_clk_dev; | |
407 | ||
408 | static inline void lpt_register_clock_device(void) | |
409 | { | |
cf0a9565 AS |
410 | lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", |
411 | PLATFORM_DEVID_NONE, | |
412 | NULL, 0); | |
f58b082a RW |
413 | } |
414 | ||
415 | static int register_device_clock(struct acpi_device *adev, | |
416 | struct lpss_private_data *pdata) | |
417 | { | |
418 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 419 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 420 | struct clk *clk; |
b59cc200 | 421 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
422 | const char *parent, *clk_name; |
423 | void __iomem *prv_base; | |
f58b082a RW |
424 | |
425 | if (!lpss_clk_dev) | |
426 | lpt_register_clock_device(); | |
427 | ||
b4f1f61e | 428 | if (IS_ERR(lpss_clk_dev)) |
429 | return PTR_ERR(lpss_clk_dev); | |
430 | ||
b59cc200 RW |
431 | clk_data = platform_get_drvdata(lpss_clk_dev); |
432 | if (!clk_data) | |
433 | return -ENODEV; | |
b0d00f8b | 434 | clk = clk_data->clk; |
b59cc200 RW |
435 | |
436 | if (!pdata->mmio_base | |
2e0f8822 | 437 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
438 | return -ENODATA; |
439 | ||
f6272170 | 440 | parent = clk_data->name; |
ed3a872e | 441 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 442 | |
03f09f73 HK |
443 | if (pdata->fixed_clk_rate) { |
444 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
445 | pdata->fixed_clk_rate); | |
446 | goto out; | |
f6272170 MW |
447 | } |
448 | ||
ff8c1af5 | 449 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
450 | clk = clk_register_gate(NULL, devname, parent, 0, |
451 | prv_base, 0, 0, NULL); | |
452 | parent = devname; | |
453 | } | |
454 | ||
ff8c1af5 | 455 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
456 | /* Prevent division by zero */ |
457 | if (!readl(prv_base)) | |
458 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
459 | ||
460 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
461 | if (!clk_name) | |
462 | return -ENOMEM; | |
463 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
82f53f9e AS |
464 | CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, |
465 | prv_base, 1, 15, 16, 15, 0, NULL); | |
ed3a872e HK |
466 | parent = clk_name; |
467 | ||
468 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
469 | if (!clk_name) { | |
470 | kfree(parent); | |
471 | return -ENOMEM; | |
472 | } | |
473 | clk = clk_register_gate(NULL, clk_name, parent, | |
474 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
475 | prv_base, 31, 0, NULL); | |
476 | kfree(parent); | |
477 | kfree(clk_name); | |
f6272170 | 478 | } |
03f09f73 | 479 | out: |
f6272170 MW |
480 | if (IS_ERR(clk)) |
481 | return PTR_ERR(clk); | |
f58b082a | 482 | |
ed3a872e | 483 | pdata->clk = clk; |
fcf0789a | 484 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
485 | return 0; |
486 | } | |
487 | ||
e6ce0ce3 AH |
488 | struct lpss_device_links { |
489 | const char *supplier_hid; | |
490 | const char *supplier_uid; | |
491 | const char *consumer_hid; | |
492 | const char *consumer_uid; | |
493 | u32 flags; | |
6025e2fa HG |
494 | const struct dmi_system_id *dep_missing_ids; |
495 | }; | |
496 | ||
497 | /* Please keep this list sorted alphabetically by vendor and model */ | |
498 | static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { | |
499 | { | |
500 | .matches = { | |
501 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), | |
502 | DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), | |
503 | }, | |
504 | }, | |
505 | {} | |
e6ce0ce3 AH |
506 | }; |
507 | ||
508 | /* | |
509 | * The _DEP method is used to identify dependencies but instead of creating | |
510 | * device links for every handle in _DEP, only links in the following list are | |
511 | * created. That is necessary because, in the general case, _DEP can refer to | |
512 | * devices that might not have drivers, or that are on different buses, or where | |
513 | * the supplier is not enumerated until after the consumer is probed. | |
514 | */ | |
515 | static const struct lpss_device_links lpss_device_links[] = { | |
cc18735f | 516 | /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ |
e6ce0ce3 | 517 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, |
cc18735f | 518 | /* CHT iGPU depends on PMIC I2C controller */ |
bd0f4e34 | 519 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
b3b3519c | 520 | /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ |
6025e2fa HG |
521 | {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, |
522 | i2c1_dep_missing_dmi_ids}, | |
cc18735f | 523 | /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ |
2d71ee0c | 524 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
cc18735f HG |
525 | /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ |
526 | {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, | |
e6ce0ce3 AH |
527 | }; |
528 | ||
e6ce0ce3 AH |
529 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, |
530 | const struct lpss_device_links *link) | |
531 | { | |
7e70c8ac | 532 | return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
533 | } |
534 | ||
535 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
536 | const struct lpss_device_links *link) | |
537 | { | |
7e70c8ac | 538 | return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
539 | } |
540 | ||
541 | struct hid_uid { | |
542 | const char *hid; | |
543 | const char *uid; | |
544 | }; | |
545 | ||
418e3ea1 | 546 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
547 | { |
548 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 549 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
550 | |
551 | if (!adev) | |
552 | return 0; | |
553 | ||
7e70c8ac | 554 | return acpi_dev_hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
555 | } |
556 | ||
557 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
558 | { | |
1e30124a HG |
559 | struct device *dev; |
560 | ||
e6ce0ce3 AH |
561 | struct hid_uid data = { |
562 | .hid = hid, | |
563 | .uid = uid, | |
564 | }; | |
565 | ||
1e30124a HG |
566 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
567 | if (dev) | |
568 | return dev; | |
569 | ||
570 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
571 | } |
572 | ||
573 | static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) | |
574 | { | |
575 | struct acpi_handle_list dep_devices; | |
576 | acpi_status status; | |
2e57d10a | 577 | bool ret = false; |
e6ce0ce3 AH |
578 | int i; |
579 | ||
580 | if (!acpi_has_method(adev->handle, "_DEP")) | |
581 | return false; | |
582 | ||
583 | status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, | |
584 | &dep_devices); | |
585 | if (ACPI_FAILURE(status)) { | |
586 | dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); | |
587 | return false; | |
588 | } | |
589 | ||
590 | for (i = 0; i < dep_devices.count; i++) { | |
2e57d10a RW |
591 | if (dep_devices.handles[i] == handle) { |
592 | ret = true; | |
593 | break; | |
594 | } | |
e6ce0ce3 AH |
595 | } |
596 | ||
2e57d10a RW |
597 | acpi_handle_list_free(&dep_devices); |
598 | return ret; | |
e6ce0ce3 AH |
599 | } |
600 | ||
601 | static void acpi_lpss_link_consumer(struct device *dev1, | |
602 | const struct lpss_device_links *link) | |
603 | { | |
604 | struct device *dev2; | |
605 | ||
606 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
607 | if (!dev2) | |
608 | return; | |
609 | ||
6025e2fa HG |
610 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
611 | || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) | |
e6ce0ce3 AH |
612 | device_link_add(dev2, dev1, link->flags); |
613 | ||
614 | put_device(dev2); | |
615 | } | |
616 | ||
617 | static void acpi_lpss_link_supplier(struct device *dev1, | |
618 | const struct lpss_device_links *link) | |
619 | { | |
620 | struct device *dev2; | |
621 | ||
622 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
623 | if (!dev2) | |
624 | return; | |
625 | ||
6025e2fa HG |
626 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
627 | || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) | |
e6ce0ce3 AH |
628 | device_link_add(dev1, dev2, link->flags); |
629 | ||
630 | put_device(dev2); | |
631 | } | |
632 | ||
633 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
634 | struct platform_device *pdev) | |
635 | { | |
636 | int i; | |
637 | ||
638 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
639 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
640 | ||
641 | if (acpi_lpss_is_supplier(adev, link)) | |
642 | acpi_lpss_link_consumer(&pdev->dev, link); | |
643 | ||
644 | if (acpi_lpss_is_consumer(adev, link)) | |
645 | acpi_lpss_link_supplier(&pdev->dev, link); | |
646 | } | |
647 | } | |
648 | ||
f58b082a RW |
649 | static int acpi_lpss_create_device(struct acpi_device *adev, |
650 | const struct acpi_device_id *id) | |
651 | { | |
b2687cd7 | 652 | const struct lpss_device_desc *dev_desc; |
f58b082a | 653 | struct lpss_private_data *pdata; |
90e97820 | 654 | struct resource_entry *rentry; |
f58b082a | 655 | struct list_head resource_list; |
8ce62f85 | 656 | struct platform_device *pdev; |
f58b082a RW |
657 | int ret; |
658 | ||
b2687cd7 | 659 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
bda3df10 RJ |
660 | if (!dev_desc) |
661 | return -EINVAL; | |
662 | ||
f58b082a RW |
663 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
664 | if (!pdata) | |
665 | return -ENOMEM; | |
666 | ||
667 | INIT_LIST_HEAD(&resource_list); | |
840baca4 | 668 | ret = acpi_dev_get_memory_resources(adev, &resource_list); |
f58b082a RW |
669 | if (ret < 0) |
670 | goto err_out; | |
671 | ||
da13b336 AS |
672 | rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node); |
673 | if (rentry) { | |
674 | if (dev_desc->prv_size_override) | |
675 | pdata->mmio_size = dev_desc->prv_size_override; | |
676 | else | |
677 | pdata->mmio_size = resource_size(rentry->res); | |
678 | pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size); | |
679 | } | |
f58b082a RW |
680 | |
681 | acpi_dev_free_resource_list(&resource_list); | |
682 | ||
d3e13ff3 | 683 | if (!pdata->mmio_base) { |
e1681599 HG |
684 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
685 | adev->pnp.type.platform_id = 0; | |
6cc401be | 686 | goto out_free; |
d3e13ff3 RW |
687 | } |
688 | ||
dd242a08 | 689 | pdata->adev = adev; |
af65cfe9 MW |
690 | pdata->dev_desc = dev_desc; |
691 | ||
03f09f73 HK |
692 | if (dev_desc->setup) |
693 | dev_desc->setup(pdata); | |
694 | ||
ff8c1af5 | 695 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a | 696 | ret = register_device_clock(adev, pdata); |
6cc401be AS |
697 | if (ret) |
698 | goto out_free; | |
f58b082a RW |
699 | } |
700 | ||
b9e95fc6 RW |
701 | /* |
702 | * This works around a known issue in ACPI tables where LPSS devices | |
703 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
704 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
705 | */ | |
1a2fa02f | 706 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 707 | |
f58b082a | 708 | adev->driver_data = pdata; |
1571875b | 709 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
6cc401be AS |
710 | if (IS_ERR_OR_NULL(pdev)) { |
711 | adev->driver_data = NULL; | |
712 | ret = PTR_ERR(pdev); | |
713 | goto err_out; | |
8ce62f85 | 714 | } |
f58b082a | 715 | |
6cc401be AS |
716 | acpi_lpss_create_device_links(adev, pdev); |
717 | return 1; | |
f58b082a | 718 | |
6cc401be AS |
719 | out_free: |
720 | /* Skip the device, but continue the namespace scan */ | |
721 | ret = 0; | |
722 | err_out: | |
f58b082a RW |
723 | kfree(pdata); |
724 | return ret; | |
725 | } | |
726 | ||
1a8f8351 RW |
727 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
728 | { | |
729 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
730 | } | |
731 | ||
732 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
733 | unsigned int reg) | |
734 | { | |
735 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
736 | } | |
737 | ||
2e0f8822 RW |
738 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
739 | { | |
50861d43 | 740 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2e0f8822 RW |
741 | struct lpss_private_data *pdata; |
742 | unsigned long flags; | |
743 | int ret; | |
744 | ||
50861d43 RW |
745 | if (WARN_ON(!adev)) |
746 | return -ENODEV; | |
2e0f8822 RW |
747 | |
748 | spin_lock_irqsave(&dev->power.lock, flags); | |
749 | if (pm_runtime_suspended(dev)) { | |
750 | ret = -EAGAIN; | |
751 | goto out; | |
752 | } | |
753 | pdata = acpi_driver_data(adev); | |
754 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
755 | ret = -ENODEV; | |
756 | goto out; | |
757 | } | |
1a8f8351 | 758 | *val = __lpss_reg_read(pdata, reg); |
50861d43 | 759 | ret = 0; |
2e0f8822 RW |
760 | |
761 | out: | |
762 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
763 | return ret; | |
764 | } | |
765 | ||
766 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
767 | char *buf) | |
768 | { | |
769 | u32 ltr_value = 0; | |
770 | unsigned int reg; | |
771 | int ret; | |
772 | ||
773 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
774 | ret = lpss_reg_read(dev, reg, <r_value); | |
775 | if (ret) | |
776 | return ret; | |
777 | ||
d47e983e | 778 | return sysfs_emit(buf, "%08x\n", ltr_value); |
2e0f8822 RW |
779 | } |
780 | ||
781 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
782 | struct device_attribute *attr, char *buf) | |
783 | { | |
784 | u32 ltr_mode = 0; | |
785 | char *outstr; | |
786 | int ret; | |
787 | ||
788 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
792 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
793 | return sprintf(buf, "%s\n", outstr); | |
794 | } | |
795 | ||
796 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
797 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
798 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
799 | ||
800 | static struct attribute *lpss_attrs[] = { | |
801 | &dev_attr_auto_ltr.attr, | |
802 | &dev_attr_sw_ltr.attr, | |
803 | &dev_attr_ltr_mode.attr, | |
804 | NULL, | |
805 | }; | |
806 | ||
31945d0e | 807 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
808 | .attrs = lpss_attrs, |
809 | .name = "lpss_ltr", | |
810 | }; | |
811 | ||
1a8f8351 RW |
812 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
813 | { | |
814 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
815 | u32 ltr_mode, ltr_val; | |
816 | ||
817 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
818 | if (val < 0) { | |
819 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
820 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
821 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
822 | } | |
823 | return; | |
824 | } | |
825 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
826 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
827 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
828 | val = LPSS_LTR_MAX_VAL; | |
829 | } else if (val > LPSS_LTR_MAX_VAL) { | |
830 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
831 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
832 | } else { | |
833 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
834 | } | |
835 | ltr_val |= val; | |
836 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
837 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
838 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
839 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
840 | } | |
841 | } | |
842 | ||
c78b0830 HK |
843 | #ifdef CONFIG_PM |
844 | /** | |
845 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
846 | * @dev: LPSS device | |
cb39dcdd | 847 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
848 | * |
849 | * Most LPSS devices have private registers which may loose their context when | |
850 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
851 | * prv_reg_ctx array. | |
852 | */ | |
cb39dcdd AS |
853 | static void acpi_lpss_save_ctx(struct device *dev, |
854 | struct lpss_private_data *pdata) | |
c78b0830 | 855 | { |
c78b0830 HK |
856 | unsigned int i; |
857 | ||
858 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
859 | unsigned long offset = i * sizeof(u32); | |
860 | ||
861 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
862 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
863 | pdata->prv_reg_ctx[i], offset); | |
864 | } | |
865 | } | |
866 | ||
867 | /** | |
868 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
869 | * @dev: LPSS device | |
cb39dcdd | 870 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
871 | * |
872 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
873 | */ | |
cb39dcdd AS |
874 | static void acpi_lpss_restore_ctx(struct device *dev, |
875 | struct lpss_private_data *pdata) | |
c78b0830 | 876 | { |
c78b0830 HK |
877 | unsigned int i; |
878 | ||
02b98540 AS |
879 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
880 | unsigned long offset = i * sizeof(u32); | |
881 | ||
882 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
883 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
884 | pdata->prv_reg_ctx[i], offset); | |
885 | } | |
886 | } | |
887 | ||
888 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
889 | { | |
c78b0830 HK |
890 | /* |
891 | * The following delay is needed or the subsequent write operations may | |
892 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
893 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 894 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 895 | */ |
b00855ae SK |
896 | unsigned int delay = 10; /* default 10ms delay */ |
897 | ||
898 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
899 | delay = 0; | |
900 | ||
901 | msleep(delay); | |
c78b0830 HK |
902 | } |
903 | ||
c3a49cf3 AS |
904 | static int acpi_lpss_activate(struct device *dev) |
905 | { | |
906 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
907 | int ret; | |
908 | ||
63705c40 | 909 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
910 | if (ret) |
911 | return ret; | |
912 | ||
913 | acpi_lpss_d3_to_d0_delay(pdata); | |
914 | ||
915 | /* | |
916 | * This is called only on ->probe() stage where a device is either in | |
917 | * known state defined by BIOS or most likely powered off. Due to this | |
918 | * we have to deassert reset line to be sure that ->probe() will | |
919 | * recognize the device. | |
920 | */ | |
15aa5e4c | 921 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
c3a49cf3 AS |
922 | lpss_deassert_reset(pdata); |
923 | ||
15aa5e4c HG |
924 | #ifdef CONFIG_PM |
925 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) | |
926 | acpi_lpss_save_ctx(dev, pdata); | |
927 | #endif | |
928 | ||
c3a49cf3 AS |
929 | return 0; |
930 | } | |
931 | ||
932 | static void acpi_lpss_dismiss(struct device *dev) | |
933 | { | |
cbe25ce3 | 934 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
935 | } |
936 | ||
eebb3e8d AS |
937 | /* IOSF SB for LPSS island */ |
938 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
939 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
940 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
941 | ||
942 | #define LPSS_IOSF_PMCSR 0x84 | |
943 | #define LPSS_PMCSR_D0 0 | |
944 | #define LPSS_PMCSR_D3hot 3 | |
945 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
946 | ||
947 | #define LPSS_IOSF_GPIODEF0 0x154 | |
948 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
949 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
950 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 951 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
952 | |
953 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 954 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
955 | |
956 | static void lpss_iosf_enter_d3_state(void) | |
957 | { | |
958 | u32 value1 = 0; | |
d132d6d5 | 959 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
960 | u32 value2 = LPSS_PMCSR_D3hot; |
961 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
962 | /* | |
963 | * PMC provides an information about actual status of the LPSS devices. | |
964 | * Here we read the values related to LPSS power island, i.e. LPSS | |
965 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
966 | */ | |
86b62e5c | 967 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
968 | int ret; |
969 | ||
970 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
971 | if (ret) | |
972 | return; | |
973 | ||
974 | mutex_lock(&lpss_iosf_mutex); | |
975 | ||
976 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
977 | if (ret) | |
978 | goto exit; | |
979 | ||
980 | /* | |
981 | * Get the status of entire LPSS power island per device basis. | |
982 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
983 | * are already in D3hot. | |
984 | */ | |
86b62e5c | 985 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
986 | if (pmc_status) |
987 | goto exit; | |
988 | ||
989 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
990 | LPSS_IOSF_PMCSR, value2, mask2); | |
991 | ||
992 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
993 | LPSS_IOSF_PMCSR, value2, mask2); | |
994 | ||
995 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
996 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
997 | |
998 | lpss_iosf_d3_entered = true; | |
999 | ||
eebb3e8d AS |
1000 | exit: |
1001 | mutex_unlock(&lpss_iosf_mutex); | |
1002 | } | |
1003 | ||
1004 | static void lpss_iosf_exit_d3_state(void) | |
1005 | { | |
d132d6d5 AS |
1006 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
1007 | LPSS_GPIODEF0_DMA_LLP; | |
1008 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
1009 | u32 value2 = LPSS_PMCSR_D0; |
1010 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
1011 | ||
1012 | mutex_lock(&lpss_iosf_mutex); | |
1013 | ||
12864ff8 RW |
1014 | if (!lpss_iosf_d3_entered) |
1015 | goto exit; | |
1016 | ||
1017 | lpss_iosf_d3_entered = false; | |
1018 | ||
eebb3e8d AS |
1019 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
1020 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
1021 | ||
1022 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
1023 | LPSS_IOSF_PMCSR, value2, mask2); | |
1024 | ||
1025 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
1026 | LPSS_IOSF_PMCSR, value2, mask2); | |
1027 | ||
12864ff8 | 1028 | exit: |
eebb3e8d AS |
1029 | mutex_unlock(&lpss_iosf_mutex); |
1030 | } | |
1031 | ||
12864ff8 | 1032 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 1033 | { |
cb39dcdd AS |
1034 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1035 | int ret; | |
c78b0830 | 1036 | |
cb39dcdd AS |
1037 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1038 | acpi_lpss_save_ctx(dev, pdata); | |
1039 | ||
a192aa92 | 1040 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1041 | |
1042 | /* | |
1043 | * This call must be last in the sequence, otherwise PMC will return | |
1044 | * wrong status for devices being about to be powered off. See | |
1045 | * lpss_iosf_enter_d3_state() for further information. | |
1046 | */ | |
12864ff8 | 1047 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1048 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1049 | lpss_iosf_enter_d3_state(); |
1050 | ||
1051 | return ret; | |
c78b0830 HK |
1052 | } |
1053 | ||
12864ff8 | 1054 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1055 | { |
cb39dcdd AS |
1056 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1057 | int ret; | |
c78b0830 | 1058 | |
eebb3e8d AS |
1059 | /* |
1060 | * This call is kept first to be in symmetry with | |
1061 | * acpi_lpss_runtime_suspend() one. | |
1062 | */ | |
12864ff8 | 1063 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1064 | lpss_iosf_exit_d3_state(); |
1065 | ||
63705c40 | 1066 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1067 | if (ret) |
1068 | return ret; | |
1069 | ||
02b98540 AS |
1070 | acpi_lpss_d3_to_d0_delay(pdata); |
1071 | ||
15aa5e4c | 1072 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
cb39dcdd AS |
1073 | acpi_lpss_restore_ctx(dev, pdata); |
1074 | ||
a192aa92 RW |
1075 | return 0; |
1076 | } | |
1077 | ||
1078 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1079 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1080 | { |
05087360 RW |
1081 | int ret; |
1082 | ||
fa2bfead | 1083 | if (dev_pm_skip_suspend(dev)) |
05087360 | 1084 | return 0; |
a192aa92 | 1085 | |
05087360 | 1086 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1087 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1088 | } |
1089 | ||
48402cee HG |
1090 | static int acpi_lpss_suspend_late(struct device *dev) |
1091 | { | |
1092 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1093 | ||
1094 | if (pdata->dev_desc->resume_from_noirq) | |
1095 | return 0; | |
1096 | ||
1097 | return acpi_lpss_do_suspend_late(dev); | |
1098 | } | |
1099 | ||
1100 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1101 | { | |
1102 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1103 | int ret; | |
1104 | ||
1105 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1106 | /* |
1107 | * The driver's ->suspend_late callback will be invoked by | |
1108 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1109 | * driver really wanted to run that code in ->suspend_noirq, but | |
1110 | * it could not run after acpi_dev_suspend() and the driver | |
1111 | * expected the latter to be called in the "late" phase. | |
1112 | */ | |
48402cee HG |
1113 | ret = acpi_lpss_do_suspend_late(dev); |
1114 | if (ret) | |
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | return acpi_subsys_suspend_noirq(dev); | |
1119 | } | |
1120 | ||
1121 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1122 | { |
12864ff8 | 1123 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1124 | |
1125 | return ret ? ret : pm_generic_resume_early(dev); | |
1126 | } | |
48402cee HG |
1127 | |
1128 | static int acpi_lpss_resume_early(struct device *dev) | |
1129 | { | |
1130 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1131 | ||
1132 | if (pdata->dev_desc->resume_from_noirq) | |
1133 | return 0; | |
1134 | ||
76c70cb5 | 1135 | if (dev_pm_skip_resume(dev)) |
6e176bf8 RW |
1136 | return 0; |
1137 | ||
48402cee HG |
1138 | return acpi_lpss_do_resume_early(dev); |
1139 | } | |
1140 | ||
1141 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1142 | { | |
1143 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1144 | int ret; | |
1145 | ||
3cd7957e | 1146 | /* Follow acpi_subsys_resume_noirq(). */ |
76c70cb5 | 1147 | if (dev_pm_skip_resume(dev)) |
3cd7957e RW |
1148 | return 0; |
1149 | ||
3cd7957e | 1150 | ret = pm_generic_resume_noirq(dev); |
48402cee HG |
1151 | if (ret) |
1152 | return ret; | |
1153 | ||
3cd7957e RW |
1154 | if (!pdata->dev_desc->resume_from_noirq) |
1155 | return 0; | |
48402cee | 1156 | |
3cd7957e RW |
1157 | /* |
1158 | * The driver's ->resume_early callback will be invoked by | |
1159 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1160 | * really wanted to run that code in ->resume_noirq, but it could not | |
1161 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1162 | * called in the "early" phase. | |
1163 | */ | |
1164 | return acpi_lpss_do_resume_early(dev); | |
1165 | } | |
1166 | ||
1167 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1168 | { | |
1169 | int ret = acpi_lpss_resume(dev); | |
1170 | ||
1171 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1172 | } |
1173 | ||
3cd7957e RW |
1174 | static int acpi_lpss_restore_early(struct device *dev) |
1175 | { | |
1176 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1177 | ||
1178 | if (pdata->dev_desc->resume_from_noirq) | |
1179 | return 0; | |
1180 | ||
1181 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1182 | } |
1183 | ||
3cd7957e RW |
1184 | static int acpi_lpss_restore_noirq(struct device *dev) |
1185 | { | |
1186 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1187 | int ret; | |
1188 | ||
1189 | ret = pm_generic_restore_noirq(dev); | |
1190 | if (ret) | |
1191 | return ret; | |
1192 | ||
1193 | if (!pdata->dev_desc->resume_from_noirq) | |
1194 | return 0; | |
1195 | ||
1196 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1197 | return acpi_lpss_do_restore_early(dev); | |
1198 | } | |
c95b7595 RW |
1199 | |
1200 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1201 | { | |
1202 | int ret = pm_generic_poweroff_late(dev); | |
1203 | ||
1204 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1205 | } | |
1206 | ||
1207 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1208 | { | |
1209 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1210 | ||
fa2bfead | 1211 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1212 | return 0; |
1213 | ||
1214 | if (pdata->dev_desc->resume_from_noirq) | |
1215 | return 0; | |
1216 | ||
1217 | return acpi_lpss_do_poweroff_late(dev); | |
1218 | } | |
1219 | ||
1220 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1221 | { | |
1222 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1223 | ||
fa2bfead | 1224 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1225 | return 0; |
1226 | ||
1227 | if (pdata->dev_desc->resume_from_noirq) { | |
1228 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1229 | int ret = acpi_lpss_do_poweroff_late(dev); | |
bb415ed5 | 1230 | |
c95b7595 RW |
1231 | if (ret) |
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | return pm_generic_poweroff_noirq(dev); | |
1236 | } | |
a192aa92 RW |
1237 | #endif /* CONFIG_PM_SLEEP */ |
1238 | ||
1239 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1240 | { | |
1241 | int ret = pm_generic_runtime_suspend(dev); | |
1242 | ||
1243 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1244 | } | |
1245 | ||
1246 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1247 | { | |
12864ff8 | 1248 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1249 | |
1250 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1251 | } |
c78b0830 HK |
1252 | #endif /* CONFIG_PM */ |
1253 | ||
1254 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1255 | #ifdef CONFIG_PM |
1256 | .activate = acpi_lpss_activate, | |
1257 | .dismiss = acpi_lpss_dismiss, | |
1258 | #endif | |
c78b0830 | 1259 | .ops = { |
5de21bb9 | 1260 | #ifdef CONFIG_PM |
c78b0830 | 1261 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1262 | .prepare = acpi_subsys_prepare, |
e4da817d | 1263 | .complete = acpi_subsys_complete, |
c78b0830 | 1264 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1265 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1266 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1267 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1268 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1269 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1270 | .poweroff = acpi_subsys_poweroff, |
1271 | .poweroff_late = acpi_lpss_poweroff_late, | |
1272 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1273 | .restore_noirq = acpi_lpss_restore_noirq, |
1274 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1275 | #endif |
c78b0830 HK |
1276 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1277 | .runtime_resume = acpi_lpss_runtime_resume, | |
1278 | #endif | |
1279 | }, | |
1280 | }; | |
1281 | ||
2e0f8822 RW |
1282 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1283 | unsigned long action, void *data) | |
1284 | { | |
1285 | struct platform_device *pdev = to_platform_device(data); | |
1286 | struct lpss_private_data *pdata; | |
1287 | struct acpi_device *adev; | |
1288 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1289 | |
1290 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1291 | if (!id || !id->driver_data) | |
1292 | return 0; | |
1293 | ||
50861d43 RW |
1294 | adev = ACPI_COMPANION(&pdev->dev); |
1295 | if (!adev) | |
2e0f8822 RW |
1296 | return 0; |
1297 | ||
1298 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1299 | if (!pdata) |
2e0f8822 RW |
1300 | return 0; |
1301 | ||
cb39dcdd AS |
1302 | if (pdata->mmio_base && |
1303 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1304 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1305 | return 0; | |
1306 | } | |
1307 | ||
c78b0830 | 1308 | switch (action) { |
de16d552 | 1309 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1310 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1311 | break; |
de16d552 | 1312 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1313 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1314 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1315 | break; |
1316 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1317 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1318 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1319 | return sysfs_create_group(&pdev->dev.kobj, |
1320 | &lpss_attr_group); | |
01ac170b | 1321 | break; |
c78b0830 | 1322 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1323 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1324 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1325 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1326 | break; |
c78b0830 HK |
1327 | default: |
1328 | break; | |
1329 | } | |
2e0f8822 | 1330 | |
c78b0830 | 1331 | return 0; |
2e0f8822 RW |
1332 | } |
1333 | ||
1334 | static struct notifier_block acpi_lpss_nb = { | |
1335 | .notifier_call = acpi_lpss_platform_notify, | |
1336 | }; | |
1337 | ||
1a8f8351 RW |
1338 | static void acpi_lpss_bind(struct device *dev) |
1339 | { | |
1340 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1341 | ||
ff8c1af5 | 1342 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1343 | return; |
1344 | ||
1345 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1346 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1347 | else | |
1348 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1349 | } | |
1350 | ||
1351 | static void acpi_lpss_unbind(struct device *dev) | |
1352 | { | |
1353 | dev->power.set_latency_tolerance = NULL; | |
1354 | } | |
1355 | ||
f58b082a RW |
1356 | static struct acpi_scan_handler lpss_handler = { |
1357 | .ids = acpi_lpss_device_ids, | |
1358 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1359 | .bind = acpi_lpss_bind, |
1360 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1361 | }; |
1362 | ||
1363 | void __init acpi_lpss_init(void) | |
1364 | { | |
eebb3e8d AS |
1365 | const struct x86_cpu_id *id; |
1366 | int ret; | |
1367 | ||
cf0a9565 | 1368 | ret = lpss_atom_clk_init(); |
eebb3e8d AS |
1369 | if (ret) |
1370 | return; | |
1371 | ||
1372 | id = x86_match_cpu(lpss_cpu_ids); | |
1373 | if (id) | |
1374 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1375 | ||
1376 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1377 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1378 | } |
d6ddaaac RW |
1379 | |
1380 | #else | |
1381 | ||
1382 | static struct acpi_scan_handler lpss_handler = { | |
1383 | .ids = acpi_lpss_device_ids, | |
1384 | }; | |
1385 | ||
1386 | void __init acpi_lpss_init(void) | |
1387 | { | |
1388 | acpi_scan_add_handler(&lpss_handler); | |
1389 | } | |
1390 | ||
1391 | #endif /* CONFIG_X86_INTEL_LPSS */ |