Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/clkdev.h> | |
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/platform_data/clk-lpss.h> | |
2e0f8822 | 21 | #include <linux/pm_runtime.h> |
c78b0830 | 22 | #include <linux/delay.h> |
f58b082a RW |
23 | |
24 | #include "internal.h" | |
25 | ||
26 | ACPI_MODULE_NAME("acpi_lpss"); | |
27 | ||
d6ddaaac RW |
28 | #ifdef CONFIG_X86_INTEL_LPSS |
29 | ||
30 | #define LPSS_ADDR(desc) ((unsigned long)&desc) | |
31 | ||
f58b082a | 32 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
33 | #define LPSS_LTR_SIZE 0x18 |
34 | ||
35 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 36 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
37 | #define LPSS_RESETS 0x04 |
38 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
39 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
40 | #define LPSS_GENERAL 0x08 |
41 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 42 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
43 | #define LPSS_SW_LTR 0x10 |
44 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
45 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
46 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
47 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
48 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
49 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
50 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
51 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
52 | #define LPSS_TX_INT 0x20 |
53 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 54 | |
c78b0830 HK |
55 | #define LPSS_PRV_REG_COUNT 9 |
56 | ||
ff8c1af5 HK |
57 | /* LPSS Flags */ |
58 | #define LPSS_CLK BIT(0) | |
59 | #define LPSS_CLK_GATE BIT(1) | |
60 | #define LPSS_CLK_DIVIDER BIT(2) | |
61 | #define LPSS_LTR BIT(3) | |
62 | #define LPSS_SAVE_CTX BIT(4) | |
f6272170 | 63 | |
06d86415 | 64 | struct lpss_private_data; |
f58b082a RW |
65 | |
66 | struct lpss_device_desc { | |
ff8c1af5 | 67 | unsigned int flags; |
fcf0789a | 68 | const char *clk_con_id; |
2e0f8822 | 69 | unsigned int prv_offset; |
958c4eb2 | 70 | size_t prv_size_override; |
06d86415 | 71 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
72 | }; |
73 | ||
b59cc200 | 74 | static struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 75 | .flags = LPSS_CLK, |
b59cc200 RW |
76 | }; |
77 | ||
f58b082a RW |
78 | struct lpss_private_data { |
79 | void __iomem *mmio_base; | |
80 | resource_size_t mmio_size; | |
03f09f73 | 81 | unsigned int fixed_clk_rate; |
f58b082a RW |
82 | struct clk *clk; |
83 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 84 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
85 | }; |
86 | ||
1f47a77c HK |
87 | /* UART Component Parameter Register */ |
88 | #define LPSS_UART_CPR 0xF4 | |
89 | #define LPSS_UART_CPR_AFCE BIT(4) | |
90 | ||
06d86415 HK |
91 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
92 | { | |
088f1fd2 | 93 | unsigned int offset; |
1f47a77c | 94 | u32 val; |
06d86415 | 95 | |
088f1fd2 | 96 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
97 | val = readl(pdata->mmio_base + offset); |
98 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
99 | ||
100 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
101 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
102 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
103 | val = readl(pdata->mmio_base + offset); | |
104 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
105 | writel(val, pdata->mmio_base + offset); | |
106 | } | |
06d86415 HK |
107 | } |
108 | ||
3095794a | 109 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
110 | { |
111 | unsigned int offset; | |
112 | u32 val; | |
113 | ||
114 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
115 | val = readl(pdata->mmio_base + offset); | |
116 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
117 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
118 | } |
119 | ||
120 | #define LPSS_I2C_ENABLE 0x6c | |
121 | ||
122 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
123 | { | |
124 | lpss_deassert_reset(pdata); | |
765bdd4e | 125 | |
03f09f73 HK |
126 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
127 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
128 | |
129 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 130 | } |
43218a1b | 131 | |
f58b082a | 132 | static struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 133 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 134 | .prv_offset = 0x800, |
ed3a872e HK |
135 | }; |
136 | ||
137 | static struct lpss_device_desc lpt_i2c_dev_desc = { | |
ff8c1af5 | 138 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 139 | .prv_offset = 0x800, |
2e0f8822 RW |
140 | }; |
141 | ||
06d86415 | 142 | static struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 143 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 144 | .clk_con_id = "baudclk", |
06d86415 | 145 | .prv_offset = 0x800, |
06d86415 | 146 | .setup = lpss_uart_setup, |
2e0f8822 RW |
147 | }; |
148 | ||
149 | static struct lpss_device_desc lpt_sdio_dev_desc = { | |
ff8c1af5 | 150 | .flags = LPSS_LTR, |
2e0f8822 | 151 | .prv_offset = 0x1000, |
958c4eb2 | 152 | .prv_size_override = 0x1018, |
e1c74817 CCE |
153 | }; |
154 | ||
155 | static struct lpss_device_desc byt_pwm_dev_desc = { | |
3f56bf3e | 156 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
157 | }; |
158 | ||
f6272170 | 159 | static struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 160 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 161 | .clk_con_id = "baudclk", |
f6272170 | 162 | .prv_offset = 0x800, |
06d86415 | 163 | .setup = lpss_uart_setup, |
f6272170 MW |
164 | }; |
165 | ||
f6272170 | 166 | static struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 167 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 168 | .prv_offset = 0x400, |
f6272170 MW |
169 | }; |
170 | ||
171 | static struct lpss_device_desc byt_sdio_dev_desc = { | |
3df2da96 | 172 | .flags = LPSS_CLK, |
f6272170 MW |
173 | }; |
174 | ||
175 | static struct lpss_device_desc byt_i2c_dev_desc = { | |
3df2da96 | 176 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 177 | .prv_offset = 0x800, |
03f09f73 | 178 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
179 | }; |
180 | ||
3095794a MW |
181 | static struct lpss_device_desc bsw_spi_dev_desc = { |
182 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, | |
183 | .prv_offset = 0x400, | |
184 | .setup = lpss_deassert_reset, | |
185 | }; | |
186 | ||
d6ddaaac RW |
187 | #else |
188 | ||
189 | #define LPSS_ADDR(desc) (0UL) | |
190 | ||
191 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
192 | ||
f58b082a | 193 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 194 | /* Generic LPSS devices */ |
d6ddaaac | 195 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 196 | |
f58b082a | 197 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
198 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
199 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
200 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
201 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
202 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
203 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
204 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
205 | { "INT33C7", }, |
206 | ||
f6272170 | 207 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
208 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
209 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
210 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
211 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
212 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 213 | { "INT33B2", }, |
20482d32 | 214 | { "INT33FC", }, |
f6272170 | 215 | |
1bfbd8eb | 216 | /* Braswell LPSS devices */ |
3f56bf3e | 217 | { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, |
1bfbd8eb | 218 | { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, |
3095794a | 219 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
1bfbd8eb AC |
220 | { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, |
221 | ||
d6ddaaac RW |
222 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
223 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
224 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
225 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
226 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
227 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
228 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
229 | { "INT3437", }, |
230 | ||
ff8c1af5 HK |
231 | /* Wildcat Point LPSS devices */ |
232 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 233 | |
f58b082a RW |
234 | { } |
235 | }; | |
236 | ||
d6ddaaac RW |
237 | #ifdef CONFIG_X86_INTEL_LPSS |
238 | ||
f58b082a RW |
239 | static int is_memory(struct acpi_resource *res, void *not_used) |
240 | { | |
241 | struct resource r; | |
242 | return !acpi_dev_resource_memory(res, &r); | |
243 | } | |
244 | ||
245 | /* LPSS main clock device. */ | |
246 | static struct platform_device *lpss_clk_dev; | |
247 | ||
248 | static inline void lpt_register_clock_device(void) | |
249 | { | |
250 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
251 | } | |
252 | ||
253 | static int register_device_clock(struct acpi_device *adev, | |
254 | struct lpss_private_data *pdata) | |
255 | { | |
256 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 257 | const char *devname = dev_name(&adev->dev); |
f6272170 | 258 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 259 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
260 | const char *parent, *clk_name; |
261 | void __iomem *prv_base; | |
f58b082a RW |
262 | |
263 | if (!lpss_clk_dev) | |
264 | lpt_register_clock_device(); | |
265 | ||
b59cc200 RW |
266 | clk_data = platform_get_drvdata(lpss_clk_dev); |
267 | if (!clk_data) | |
268 | return -ENODEV; | |
b0d00f8b | 269 | clk = clk_data->clk; |
b59cc200 RW |
270 | |
271 | if (!pdata->mmio_base | |
2e0f8822 | 272 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
273 | return -ENODATA; |
274 | ||
f6272170 | 275 | parent = clk_data->name; |
ed3a872e | 276 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 277 | |
03f09f73 HK |
278 | if (pdata->fixed_clk_rate) { |
279 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
280 | pdata->fixed_clk_rate); | |
281 | goto out; | |
f6272170 MW |
282 | } |
283 | ||
ff8c1af5 | 284 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
285 | clk = clk_register_gate(NULL, devname, parent, 0, |
286 | prv_base, 0, 0, NULL); | |
287 | parent = devname; | |
288 | } | |
289 | ||
ff8c1af5 | 290 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
291 | /* Prevent division by zero */ |
292 | if (!readl(prv_base)) | |
293 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
294 | ||
295 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
296 | if (!clk_name) | |
297 | return -ENOMEM; | |
298 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
299 | 0, prv_base, | |
300 | 1, 15, 16, 15, 0, NULL); | |
301 | parent = clk_name; | |
302 | ||
303 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
304 | if (!clk_name) { | |
305 | kfree(parent); | |
306 | return -ENOMEM; | |
307 | } | |
308 | clk = clk_register_gate(NULL, clk_name, parent, | |
309 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
310 | prv_base, 31, 0, NULL); | |
311 | kfree(parent); | |
312 | kfree(clk_name); | |
f6272170 | 313 | } |
03f09f73 | 314 | out: |
f6272170 MW |
315 | if (IS_ERR(clk)) |
316 | return PTR_ERR(clk); | |
f58b082a | 317 | |
ed3a872e | 318 | pdata->clk = clk; |
fcf0789a | 319 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
320 | return 0; |
321 | } | |
322 | ||
323 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
324 | const struct acpi_device_id *id) | |
325 | { | |
326 | struct lpss_device_desc *dev_desc; | |
327 | struct lpss_private_data *pdata; | |
90e97820 | 328 | struct resource_entry *rentry; |
f58b082a | 329 | struct list_head resource_list; |
8ce62f85 | 330 | struct platform_device *pdev; |
f58b082a RW |
331 | int ret; |
332 | ||
333 | dev_desc = (struct lpss_device_desc *)id->driver_data; | |
8ce62f85 RW |
334 | if (!dev_desc) { |
335 | pdev = acpi_create_platform_device(adev); | |
336 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
337 | } | |
f58b082a RW |
338 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
339 | if (!pdata) | |
340 | return -ENOMEM; | |
341 | ||
342 | INIT_LIST_HEAD(&resource_list); | |
343 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
344 | if (ret < 0) | |
345 | goto err_out; | |
346 | ||
347 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 348 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
349 | if (dev_desc->prv_size_override) |
350 | pdata->mmio_size = dev_desc->prv_size_override; | |
351 | else | |
90e97820 JL |
352 | pdata->mmio_size = resource_size(rentry->res); |
353 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 354 | pdata->mmio_size); |
4483d59e HK |
355 | if (!pdata->mmio_base) |
356 | goto err_out; | |
f58b082a RW |
357 | break; |
358 | } | |
359 | ||
360 | acpi_dev_free_resource_list(&resource_list); | |
361 | ||
af65cfe9 MW |
362 | pdata->dev_desc = dev_desc; |
363 | ||
03f09f73 HK |
364 | if (dev_desc->setup) |
365 | dev_desc->setup(pdata); | |
366 | ||
ff8c1af5 | 367 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
368 | ret = register_device_clock(adev, pdata); |
369 | if (ret) { | |
b9e95fc6 RW |
370 | /* Skip the device, but continue the namespace scan. */ |
371 | ret = 0; | |
372 | goto err_out; | |
f58b082a RW |
373 | } |
374 | } | |
375 | ||
b9e95fc6 RW |
376 | /* |
377 | * This works around a known issue in ACPI tables where LPSS devices | |
378 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
379 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
380 | */ | |
381 | ret = acpi_device_fix_up_power(adev); | |
382 | if (ret) { | |
383 | /* Skip the device, but continue the namespace scan. */ | |
384 | ret = 0; | |
385 | goto err_out; | |
386 | } | |
387 | ||
f58b082a | 388 | adev->driver_data = pdata; |
8ce62f85 RW |
389 | pdev = acpi_create_platform_device(adev); |
390 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
391 | return 1; |
392 | } | |
f58b082a | 393 | |
8ce62f85 | 394 | ret = PTR_ERR(pdev); |
f58b082a RW |
395 | adev->driver_data = NULL; |
396 | ||
397 | err_out: | |
398 | kfree(pdata); | |
399 | return ret; | |
400 | } | |
401 | ||
1a8f8351 RW |
402 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
403 | { | |
404 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
405 | } | |
406 | ||
407 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
408 | unsigned int reg) | |
409 | { | |
410 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
411 | } | |
412 | ||
2e0f8822 RW |
413 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
414 | { | |
415 | struct acpi_device *adev; | |
416 | struct lpss_private_data *pdata; | |
417 | unsigned long flags; | |
418 | int ret; | |
419 | ||
420 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
421 | if (WARN_ON(ret)) | |
422 | return ret; | |
423 | ||
424 | spin_lock_irqsave(&dev->power.lock, flags); | |
425 | if (pm_runtime_suspended(dev)) { | |
426 | ret = -EAGAIN; | |
427 | goto out; | |
428 | } | |
429 | pdata = acpi_driver_data(adev); | |
430 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
431 | ret = -ENODEV; | |
432 | goto out; | |
433 | } | |
1a8f8351 | 434 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
435 | |
436 | out: | |
437 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
438 | return ret; | |
439 | } | |
440 | ||
441 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
442 | char *buf) | |
443 | { | |
444 | u32 ltr_value = 0; | |
445 | unsigned int reg; | |
446 | int ret; | |
447 | ||
448 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
449 | ret = lpss_reg_read(dev, reg, <r_value); | |
450 | if (ret) | |
451 | return ret; | |
452 | ||
453 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
454 | } | |
455 | ||
456 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
457 | struct device_attribute *attr, char *buf) | |
458 | { | |
459 | u32 ltr_mode = 0; | |
460 | char *outstr; | |
461 | int ret; | |
462 | ||
463 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
464 | if (ret) | |
465 | return ret; | |
466 | ||
467 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
468 | return sprintf(buf, "%s\n", outstr); | |
469 | } | |
470 | ||
471 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
472 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
473 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
474 | ||
475 | static struct attribute *lpss_attrs[] = { | |
476 | &dev_attr_auto_ltr.attr, | |
477 | &dev_attr_sw_ltr.attr, | |
478 | &dev_attr_ltr_mode.attr, | |
479 | NULL, | |
480 | }; | |
481 | ||
482 | static struct attribute_group lpss_attr_group = { | |
483 | .attrs = lpss_attrs, | |
484 | .name = "lpss_ltr", | |
485 | }; | |
486 | ||
1a8f8351 RW |
487 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
488 | { | |
489 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
490 | u32 ltr_mode, ltr_val; | |
491 | ||
492 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
493 | if (val < 0) { | |
494 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
495 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
496 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
497 | } | |
498 | return; | |
499 | } | |
500 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
501 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
502 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
503 | val = LPSS_LTR_MAX_VAL; | |
504 | } else if (val > LPSS_LTR_MAX_VAL) { | |
505 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
506 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
507 | } else { | |
508 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
509 | } | |
510 | ltr_val |= val; | |
511 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
512 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
513 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
514 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
515 | } | |
516 | } | |
517 | ||
c78b0830 HK |
518 | #ifdef CONFIG_PM |
519 | /** | |
520 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
521 | * @dev: LPSS device | |
cb39dcdd | 522 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
523 | * |
524 | * Most LPSS devices have private registers which may loose their context when | |
525 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
526 | * prv_reg_ctx array. | |
527 | */ | |
cb39dcdd AS |
528 | static void acpi_lpss_save_ctx(struct device *dev, |
529 | struct lpss_private_data *pdata) | |
c78b0830 | 530 | { |
c78b0830 HK |
531 | unsigned int i; |
532 | ||
533 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
534 | unsigned long offset = i * sizeof(u32); | |
535 | ||
536 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
537 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
538 | pdata->prv_reg_ctx[i], offset); | |
539 | } | |
540 | } | |
541 | ||
542 | /** | |
543 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
544 | * @dev: LPSS device | |
cb39dcdd | 545 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
546 | * |
547 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
548 | */ | |
cb39dcdd AS |
549 | static void acpi_lpss_restore_ctx(struct device *dev, |
550 | struct lpss_private_data *pdata) | |
c78b0830 | 551 | { |
c78b0830 HK |
552 | unsigned int i; |
553 | ||
554 | /* | |
555 | * The following delay is needed or the subsequent write operations may | |
556 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
557 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
558 | * transition. | |
559 | */ | |
560 | msleep(10); | |
561 | ||
562 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
563 | unsigned long offset = i * sizeof(u32); | |
564 | ||
565 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
566 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
567 | pdata->prv_reg_ctx[i], offset); | |
568 | } | |
569 | } | |
570 | ||
571 | #ifdef CONFIG_PM_SLEEP | |
572 | static int acpi_lpss_suspend_late(struct device *dev) | |
573 | { | |
cb39dcdd AS |
574 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
575 | int ret; | |
c78b0830 | 576 | |
cb39dcdd | 577 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
578 | if (ret) |
579 | return ret; | |
580 | ||
cb39dcdd AS |
581 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
582 | acpi_lpss_save_ctx(dev, pdata); | |
583 | ||
c78b0830 HK |
584 | return acpi_dev_suspend_late(dev); |
585 | } | |
586 | ||
f4168b61 | 587 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 588 | { |
cb39dcdd AS |
589 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
590 | int ret; | |
c78b0830 | 591 | |
cb39dcdd | 592 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
593 | if (ret) |
594 | return ret; | |
595 | ||
cb39dcdd AS |
596 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
597 | acpi_lpss_restore_ctx(dev, pdata); | |
598 | ||
c78b0830 HK |
599 | return pm_generic_resume_early(dev); |
600 | } | |
601 | #endif /* CONFIG_PM_SLEEP */ | |
602 | ||
c78b0830 HK |
603 | static int acpi_lpss_runtime_suspend(struct device *dev) |
604 | { | |
cb39dcdd AS |
605 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
606 | int ret; | |
c78b0830 | 607 | |
cb39dcdd | 608 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
609 | if (ret) |
610 | return ret; | |
611 | ||
cb39dcdd AS |
612 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
613 | acpi_lpss_save_ctx(dev, pdata); | |
614 | ||
3df2da96 | 615 | return acpi_dev_runtime_suspend(dev); |
c78b0830 HK |
616 | } |
617 | ||
618 | static int acpi_lpss_runtime_resume(struct device *dev) | |
619 | { | |
cb39dcdd AS |
620 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
621 | int ret; | |
c78b0830 | 622 | |
cb39dcdd | 623 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
624 | if (ret) |
625 | return ret; | |
626 | ||
cb39dcdd AS |
627 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
628 | acpi_lpss_restore_ctx(dev, pdata); | |
629 | ||
c78b0830 HK |
630 | return pm_generic_runtime_resume(dev); |
631 | } | |
c78b0830 HK |
632 | #endif /* CONFIG_PM */ |
633 | ||
634 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
635 | .ops = { | |
5de21bb9 | 636 | #ifdef CONFIG_PM |
c78b0830 | 637 | #ifdef CONFIG_PM_SLEEP |
c78b0830 HK |
638 | .prepare = acpi_subsys_prepare, |
639 | .complete = acpi_subsys_complete, | |
640 | .suspend = acpi_subsys_suspend, | |
f4168b61 FZ |
641 | .suspend_late = acpi_lpss_suspend_late, |
642 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
643 | .freeze = acpi_subsys_freeze, |
644 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
645 | .poweroff_late = acpi_lpss_suspend_late, |
646 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 647 | #endif |
c78b0830 HK |
648 | .runtime_suspend = acpi_lpss_runtime_suspend, |
649 | .runtime_resume = acpi_lpss_runtime_resume, | |
650 | #endif | |
651 | }, | |
652 | }; | |
653 | ||
2e0f8822 RW |
654 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
655 | unsigned long action, void *data) | |
656 | { | |
657 | struct platform_device *pdev = to_platform_device(data); | |
658 | struct lpss_private_data *pdata; | |
659 | struct acpi_device *adev; | |
660 | const struct acpi_device_id *id; | |
2e0f8822 RW |
661 | |
662 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
663 | if (!id || !id->driver_data) | |
664 | return 0; | |
665 | ||
666 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
667 | return 0; | |
668 | ||
669 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 670 | if (!pdata) |
2e0f8822 RW |
671 | return 0; |
672 | ||
cb39dcdd AS |
673 | if (pdata->mmio_base && |
674 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
675 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
676 | return 0; | |
677 | } | |
678 | ||
c78b0830 | 679 | switch (action) { |
c78b0830 | 680 | case BUS_NOTIFY_ADD_DEVICE: |
01ac170b | 681 | pdev->dev.pm_domain = &acpi_lpss_pm_domain; |
ff8c1af5 | 682 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
683 | return sysfs_create_group(&pdev->dev.kobj, |
684 | &lpss_attr_group); | |
01ac170b | 685 | break; |
c78b0830 | 686 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 687 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 688 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
01ac170b AS |
689 | pdev->dev.pm_domain = NULL; |
690 | break; | |
c78b0830 HK |
691 | default: |
692 | break; | |
693 | } | |
2e0f8822 | 694 | |
c78b0830 | 695 | return 0; |
2e0f8822 RW |
696 | } |
697 | ||
698 | static struct notifier_block acpi_lpss_nb = { | |
699 | .notifier_call = acpi_lpss_platform_notify, | |
700 | }; | |
701 | ||
1a8f8351 RW |
702 | static void acpi_lpss_bind(struct device *dev) |
703 | { | |
704 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
705 | ||
ff8c1af5 | 706 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
707 | return; |
708 | ||
709 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
710 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
711 | else | |
712 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
713 | } | |
714 | ||
715 | static void acpi_lpss_unbind(struct device *dev) | |
716 | { | |
717 | dev->power.set_latency_tolerance = NULL; | |
718 | } | |
719 | ||
f58b082a RW |
720 | static struct acpi_scan_handler lpss_handler = { |
721 | .ids = acpi_lpss_device_ids, | |
722 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
723 | .bind = acpi_lpss_bind, |
724 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
725 | }; |
726 | ||
727 | void __init acpi_lpss_init(void) | |
728 | { | |
2e0f8822 RW |
729 | if (!lpt_clk_init()) { |
730 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
f58b082a | 731 | acpi_scan_add_handler(&lpss_handler); |
2e0f8822 | 732 | } |
f58b082a | 733 | } |
d6ddaaac RW |
734 | |
735 | #else | |
736 | ||
737 | static struct acpi_scan_handler lpss_handler = { | |
738 | .ids = acpi_lpss_device_ids, | |
739 | }; | |
740 | ||
741 | void __init acpi_lpss_init(void) | |
742 | { | |
743 | acpi_scan_add_handler(&lpss_handler); | |
744 | } | |
745 | ||
746 | #endif /* CONFIG_X86_INTEL_LPSS */ |