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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f58b082a RW |
2 | /* |
3 | * ACPI support for Intel Lynxpoint LPSS. | |
4 | * | |
3df2da96 | 5 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
6 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
f58b082a RW |
8 | */ |
9 | ||
10 | #include <linux/acpi.h> | |
f58b082a RW |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> | |
6025e2fa | 13 | #include <linux/dmi.h> |
f58b082a RW |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
eebb3e8d | 16 | #include <linux/mutex.h> |
1e30124a | 17 | #include <linux/pci.h> |
f58b082a | 18 | #include <linux/platform_device.h> |
a9443a63 | 19 | #include <linux/platform_data/x86/clk-lpss.h> |
80a7581f | 20 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
bf7696a1 | 23 | #include <linux/pwm.h> |
620c803f | 24 | #include <linux/pxa2xx_ssp.h> |
a09c5913 | 25 | #include <linux/suspend.h> |
c78b0830 | 26 | #include <linux/delay.h> |
f58b082a RW |
27 | |
28 | #include "internal.h" | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
15aa5e4c HG |
69 | /* |
70 | * For some devices the DSDT AML code for another device turns off the device | |
71 | * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) | |
72 | * as ctx register values. | |
73 | * Luckily these devices always use the same ctx register values, so we can | |
74 | * work around this by saving the ctx registers once on activation. | |
75 | */ | |
76 | #define LPSS_SAVE_CTX_ONCE BIT(5) | |
77 | #define LPSS_NO_D3_DELAY BIT(6) | |
f6272170 | 78 | |
06d86415 | 79 | struct lpss_private_data; |
f58b082a RW |
80 | |
81 | struct lpss_device_desc { | |
ff8c1af5 | 82 | unsigned int flags; |
fcf0789a | 83 | const char *clk_con_id; |
2e0f8822 | 84 | unsigned int prv_offset; |
958c4eb2 | 85 | size_t prv_size_override; |
f167c1a1 | 86 | const struct property_entry *properties; |
06d86415 | 87 | void (*setup)(struct lpss_private_data *pdata); |
48402cee | 88 | bool resume_from_noirq; |
f58b082a RW |
89 | }; |
90 | ||
eebb3e8d | 91 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 92 | .flags = LPSS_CLK, |
b59cc200 RW |
93 | }; |
94 | ||
f58b082a | 95 | struct lpss_private_data { |
dd242a08 | 96 | struct acpi_device *adev; |
f58b082a RW |
97 | void __iomem *mmio_base; |
98 | resource_size_t mmio_size; | |
03f09f73 | 99 | unsigned int fixed_clk_rate; |
f58b082a RW |
100 | struct clk *clk; |
101 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 102 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
103 | }; |
104 | ||
86b62e5c HG |
105 | /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ |
106 | static u32 pmc_atom_d3_mask = 0xfe000ffe; | |
107 | ||
eebb3e8d AS |
108 | /* LPSS run time quirks */ |
109 | static unsigned int lpss_quirks; | |
110 | ||
111 | /* | |
112 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
113 | * | |
fa9e93b1 | 114 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
115 | * it can be powered off automatically whenever the last LPSS device goes down. |
116 | * In case of no power any access to the DMA controller will hang the system. | |
117 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
118 | * well as on ASuS T100TA transformer. | |
119 | * | |
120 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
121 | * on whenever we have at least one other device in use. | |
122 | */ | |
123 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
124 | ||
1f47a77c HK |
125 | /* UART Component Parameter Register */ |
126 | #define LPSS_UART_CPR 0xF4 | |
127 | #define LPSS_UART_CPR_AFCE BIT(4) | |
128 | ||
06d86415 HK |
129 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
130 | { | |
088f1fd2 | 131 | unsigned int offset; |
1f47a77c | 132 | u32 val; |
06d86415 | 133 | |
088f1fd2 | 134 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
135 | val = readl(pdata->mmio_base + offset); |
136 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
137 | ||
138 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
139 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
140 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
141 | val = readl(pdata->mmio_base + offset); | |
142 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
143 | writel(val, pdata->mmio_base + offset); | |
144 | } | |
06d86415 HK |
145 | } |
146 | ||
3095794a | 147 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
148 | { |
149 | unsigned int offset; | |
150 | u32 val; | |
151 | ||
152 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
153 | val = readl(pdata->mmio_base + offset); | |
154 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
155 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
156 | } |
157 | ||
04434ab5 HG |
158 | /* |
159 | * BYT PWM used for backlight control by the i915 driver on systems without | |
160 | * the Crystal Cove PMIC. | |
161 | */ | |
162 | static struct pwm_lookup byt_pwm_lookup[] = { | |
163 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
b2147a3a | 164 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
04434ab5 HG |
165 | "pwm-lpss-platform"), |
166 | }; | |
167 | ||
168 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
169 | { | |
dd242a08 | 170 | /* Only call pwm_add_table for the first PWM controller */ |
5ecdb287 RJ |
171 | if (acpi_dev_uid_match(pdata->adev, 1)) |
172 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); | |
04434ab5 HG |
173 | } |
174 | ||
3095794a MW |
175 | #define LPSS_I2C_ENABLE 0x6c |
176 | ||
177 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
178 | { | |
86b62e5c HG |
179 | acpi_handle handle = pdata->adev->handle; |
180 | unsigned long long shared_host = 0; | |
181 | acpi_status status; | |
2a036e48 | 182 | u64 uid; |
86b62e5c | 183 | |
2a036e48 AS |
184 | /* Expected to always be successfull, but better safe then sorry */ |
185 | if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) { | |
8e3ecc68 LS |
186 | /* Detect I2C bus shared with PUNIT and ignore its d3 status */ |
187 | status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); | |
188 | if (ACPI_SUCCESS(status) && shared_host) | |
189 | pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); | |
190 | } | |
86b62e5c | 191 | |
3095794a | 192 | lpss_deassert_reset(pdata); |
765bdd4e | 193 | |
03f09f73 HK |
194 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
195 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
196 | |
197 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 198 | } |
43218a1b | 199 | |
fa578bf5 HG |
200 | /* |
201 | * BSW PWM1 is used for backlight control by the i915 driver | |
202 | * BSW PWM2 is used for backlight control for fixed (etched into the glass) | |
203 | * touch controls on some models. These touch-controls have specialized | |
204 | * drivers which know they need the "pwm_soc_lpss_2" con-id. | |
205 | */ | |
bf7696a1 HG |
206 | static struct pwm_lookup bsw_pwm_lookup[] = { |
207 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
b2147a3a | 208 | "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, |
bf7696a1 | 209 | "pwm-lpss-platform"), |
fa578bf5 HG |
210 | PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL, |
211 | "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL, | |
212 | "pwm-lpss-platform"), | |
bf7696a1 HG |
213 | }; |
214 | ||
215 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
216 | { | |
dd242a08 | 217 | /* Only call pwm_add_table for the first PWM controller */ |
5ecdb287 RJ |
218 | if (acpi_dev_uid_match(pdata->adev, 1)) |
219 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); | |
bf7696a1 HG |
220 | } |
221 | ||
620c803f AS |
222 | static const struct property_entry lpt_spi_properties[] = { |
223 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), | |
224 | { } | |
225 | }; | |
226 | ||
227 | static const struct lpss_device_desc lpt_spi_dev_desc = { | |
57b30064 JN |
228 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
229 | | LPSS_SAVE_CTX, | |
ed3a872e | 230 | .prv_offset = 0x800, |
620c803f | 231 | .properties = lpt_spi_properties, |
ed3a872e HK |
232 | }; |
233 | ||
b2687cd7 | 234 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
57b30064 | 235 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, |
2e0f8822 | 236 | .prv_offset = 0x800, |
2e0f8822 RW |
237 | }; |
238 | ||
a5565cf2 HK |
239 | static struct property_entry uart_properties[] = { |
240 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
241 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
242 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
243 | { }, | |
244 | }; | |
245 | ||
b2687cd7 | 246 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
57b30064 JN |
247 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR |
248 | | LPSS_SAVE_CTX, | |
fcf0789a | 249 | .clk_con_id = "baudclk", |
06d86415 | 250 | .prv_offset = 0x800, |
06d86415 | 251 | .setup = lpss_uart_setup, |
a5565cf2 | 252 | .properties = uart_properties, |
2e0f8822 RW |
253 | }; |
254 | ||
b2687cd7 | 255 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 256 | .flags = LPSS_LTR, |
2e0f8822 | 257 | .prv_offset = 0x1000, |
958c4eb2 | 258 | .prv_size_override = 0x1018, |
e1c74817 CCE |
259 | }; |
260 | ||
b2687cd7 | 261 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 262 | .flags = LPSS_SAVE_CTX, |
fdcb613d | 263 | .prv_offset = 0x800, |
04434ab5 | 264 | .setup = byt_pwm_setup, |
e1c74817 CCE |
265 | }; |
266 | ||
b00855ae | 267 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
15aa5e4c | 268 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, |
fdcb613d | 269 | .prv_offset = 0x800, |
bf7696a1 | 270 | .setup = bsw_pwm_setup, |
5e31ee84 | 271 | .resume_from_noirq = true, |
b00855ae SK |
272 | }; |
273 | ||
03c57b01 HG |
274 | static const struct lpss_device_desc bsw_pwm2_dev_desc = { |
275 | .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, | |
276 | .prv_offset = 0x800, | |
277 | .resume_from_noirq = true, | |
278 | }; | |
279 | ||
b2687cd7 | 280 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 281 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 282 | .clk_con_id = "baudclk", |
f6272170 | 283 | .prv_offset = 0x800, |
06d86415 | 284 | .setup = lpss_uart_setup, |
a5565cf2 | 285 | .properties = uart_properties, |
f6272170 MW |
286 | }; |
287 | ||
b00855ae SK |
288 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
289 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
290 | | LPSS_NO_D3_DELAY, | |
291 | .clk_con_id = "baudclk", | |
292 | .prv_offset = 0x800, | |
293 | .setup = lpss_uart_setup, | |
a5565cf2 | 294 | .properties = uart_properties, |
b00855ae SK |
295 | }; |
296 | ||
620c803f AS |
297 | static const struct property_entry byt_spi_properties[] = { |
298 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), | |
299 | { } | |
300 | }; | |
301 | ||
b2687cd7 | 302 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 303 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 304 | .prv_offset = 0x400, |
620c803f | 305 | .properties = byt_spi_properties, |
f6272170 MW |
306 | }; |
307 | ||
b2687cd7 | 308 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 309 | .flags = LPSS_CLK, |
f6272170 MW |
310 | }; |
311 | ||
b2687cd7 | 312 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 313 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 314 | .prv_offset = 0x800, |
03f09f73 | 315 | .setup = byt_i2c_setup, |
48402cee | 316 | .resume_from_noirq = true, |
1bfbd8eb AC |
317 | }; |
318 | ||
b00855ae SK |
319 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
320 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
321 | .prv_offset = 0x800, | |
322 | .setup = byt_i2c_setup, | |
48402cee | 323 | .resume_from_noirq = true, |
b00855ae SK |
324 | }; |
325 | ||
620c803f AS |
326 | static const struct property_entry bsw_spi_properties[] = { |
327 | PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), | |
328 | { } | |
329 | }; | |
330 | ||
eebb3e8d | 331 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
332 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
333 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
334 | .prv_offset = 0x400, |
335 | .setup = lpss_deassert_reset, | |
620c803f | 336 | .properties = bsw_spi_properties, |
3095794a MW |
337 | }; |
338 | ||
eebb3e8d | 339 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
e36cf2f7 TG |
340 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), |
341 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), | |
eebb3e8d AS |
342 | {} |
343 | }; | |
344 | ||
d6ddaaac RW |
345 | #else |
346 | ||
347 | #define LPSS_ADDR(desc) (0UL) | |
348 | ||
349 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
350 | ||
f58b082a | 351 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 352 | /* Generic LPSS devices */ |
d6ddaaac | 353 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 354 | |
f58b082a | 355 | /* Lynxpoint LPSS devices */ |
620c803f AS |
356 | { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, |
357 | { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
358 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, |
359 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
360 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
361 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
362 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a | 363 | |
f6272170 | 364 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
365 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
366 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
367 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
368 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
369 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 370 | |
1bfbd8eb | 371 | /* Braswell LPSS devices */ |
24071406 | 372 | { "80862286", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 373 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
03c57b01 | 374 | { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) }, |
b00855ae | 375 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, |
3095794a | 376 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
24071406 | 377 | { "808622C0", LPSS_ADDR(lpss_dma_desc) }, |
b00855ae | 378 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 379 | |
b00855ae | 380 | /* Broadwell LPSS devices */ |
620c803f AS |
381 | { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, |
382 | { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, | |
d6ddaaac RW |
383 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, |
384 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
385 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
386 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
387 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 | 388 | |
ff8c1af5 | 389 | /* Wildcat Point LPSS devices */ |
620c803f | 390 | { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, |
43218a1b | 391 | |
f58b082a RW |
392 | { } |
393 | }; | |
394 | ||
d6ddaaac RW |
395 | #ifdef CONFIG_X86_INTEL_LPSS |
396 | ||
f58b082a RW |
397 | /* LPSS main clock device. */ |
398 | static struct platform_device *lpss_clk_dev; | |
399 | ||
400 | static inline void lpt_register_clock_device(void) | |
401 | { | |
cf0a9565 AS |
402 | lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", |
403 | PLATFORM_DEVID_NONE, | |
404 | NULL, 0); | |
f58b082a RW |
405 | } |
406 | ||
407 | static int register_device_clock(struct acpi_device *adev, | |
408 | struct lpss_private_data *pdata) | |
409 | { | |
410 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 411 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 412 | struct clk *clk; |
b59cc200 | 413 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
414 | const char *parent, *clk_name; |
415 | void __iomem *prv_base; | |
f58b082a RW |
416 | |
417 | if (!lpss_clk_dev) | |
418 | lpt_register_clock_device(); | |
419 | ||
b4f1f61e | 420 | if (IS_ERR(lpss_clk_dev)) |
421 | return PTR_ERR(lpss_clk_dev); | |
422 | ||
b59cc200 RW |
423 | clk_data = platform_get_drvdata(lpss_clk_dev); |
424 | if (!clk_data) | |
425 | return -ENODEV; | |
b0d00f8b | 426 | clk = clk_data->clk; |
b59cc200 RW |
427 | |
428 | if (!pdata->mmio_base | |
2e0f8822 | 429 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
430 | return -ENODATA; |
431 | ||
f6272170 | 432 | parent = clk_data->name; |
ed3a872e | 433 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 434 | |
03f09f73 HK |
435 | if (pdata->fixed_clk_rate) { |
436 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
437 | pdata->fixed_clk_rate); | |
438 | goto out; | |
f6272170 MW |
439 | } |
440 | ||
ff8c1af5 | 441 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
442 | clk = clk_register_gate(NULL, devname, parent, 0, |
443 | prv_base, 0, 0, NULL); | |
444 | parent = devname; | |
445 | } | |
446 | ||
ff8c1af5 | 447 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
448 | /* Prevent division by zero */ |
449 | if (!readl(prv_base)) | |
450 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
451 | ||
452 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
453 | if (!clk_name) | |
454 | return -ENOMEM; | |
455 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
3ebccf1d | 456 | 0, prv_base, 1, 15, 16, 15, |
82f53f9e | 457 | CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, |
3ebccf1d | 458 | NULL); |
ed3a872e HK |
459 | parent = clk_name; |
460 | ||
461 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
462 | if (!clk_name) { | |
463 | kfree(parent); | |
464 | return -ENOMEM; | |
465 | } | |
466 | clk = clk_register_gate(NULL, clk_name, parent, | |
467 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
468 | prv_base, 31, 0, NULL); | |
469 | kfree(parent); | |
470 | kfree(clk_name); | |
f6272170 | 471 | } |
03f09f73 | 472 | out: |
f6272170 MW |
473 | if (IS_ERR(clk)) |
474 | return PTR_ERR(clk); | |
f58b082a | 475 | |
ed3a872e | 476 | pdata->clk = clk; |
fcf0789a | 477 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
478 | return 0; |
479 | } | |
480 | ||
e6ce0ce3 AH |
481 | struct lpss_device_links { |
482 | const char *supplier_hid; | |
483 | const char *supplier_uid; | |
484 | const char *consumer_hid; | |
485 | const char *consumer_uid; | |
486 | u32 flags; | |
6025e2fa HG |
487 | const struct dmi_system_id *dep_missing_ids; |
488 | }; | |
489 | ||
490 | /* Please keep this list sorted alphabetically by vendor and model */ | |
491 | static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { | |
492 | { | |
493 | .matches = { | |
494 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), | |
495 | DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), | |
496 | }, | |
497 | }, | |
498 | {} | |
e6ce0ce3 AH |
499 | }; |
500 | ||
501 | /* | |
502 | * The _DEP method is used to identify dependencies but instead of creating | |
503 | * device links for every handle in _DEP, only links in the following list are | |
504 | * created. That is necessary because, in the general case, _DEP can refer to | |
505 | * devices that might not have drivers, or that are on different buses, or where | |
506 | * the supplier is not enumerated until after the consumer is probed. | |
507 | */ | |
508 | static const struct lpss_device_links lpss_device_links[] = { | |
cc18735f | 509 | /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ |
e6ce0ce3 | 510 | {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, |
cc18735f | 511 | /* CHT iGPU depends on PMIC I2C controller */ |
bd0f4e34 | 512 | {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
b3b3519c | 513 | /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ |
6025e2fa HG |
514 | {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, |
515 | i2c1_dep_missing_dmi_ids}, | |
cc18735f | 516 | /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ |
2d71ee0c | 517 | {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, |
cc18735f HG |
518 | /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ |
519 | {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, | |
e6ce0ce3 AH |
520 | }; |
521 | ||
e6ce0ce3 AH |
522 | static bool acpi_lpss_is_supplier(struct acpi_device *adev, |
523 | const struct lpss_device_links *link) | |
524 | { | |
7e70c8ac | 525 | return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); |
e6ce0ce3 AH |
526 | } |
527 | ||
528 | static bool acpi_lpss_is_consumer(struct acpi_device *adev, | |
529 | const struct lpss_device_links *link) | |
530 | { | |
7e70c8ac | 531 | return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); |
e6ce0ce3 AH |
532 | } |
533 | ||
534 | struct hid_uid { | |
535 | const char *hid; | |
536 | const char *uid; | |
537 | }; | |
538 | ||
418e3ea1 | 539 | static int match_hid_uid(struct device *dev, const void *data) |
e6ce0ce3 AH |
540 | { |
541 | struct acpi_device *adev = ACPI_COMPANION(dev); | |
418e3ea1 | 542 | const struct hid_uid *id = data; |
e6ce0ce3 AH |
543 | |
544 | if (!adev) | |
545 | return 0; | |
546 | ||
7e70c8ac | 547 | return acpi_dev_hid_uid_match(adev, id->hid, id->uid); |
e6ce0ce3 AH |
548 | } |
549 | ||
550 | static struct device *acpi_lpss_find_device(const char *hid, const char *uid) | |
551 | { | |
1e30124a HG |
552 | struct device *dev; |
553 | ||
e6ce0ce3 AH |
554 | struct hid_uid data = { |
555 | .hid = hid, | |
556 | .uid = uid, | |
557 | }; | |
558 | ||
1e30124a HG |
559 | dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); |
560 | if (dev) | |
561 | return dev; | |
562 | ||
563 | return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); | |
e6ce0ce3 AH |
564 | } |
565 | ||
e6ce0ce3 AH |
566 | static void acpi_lpss_link_consumer(struct device *dev1, |
567 | const struct lpss_device_links *link) | |
568 | { | |
569 | struct device *dev2; | |
570 | ||
571 | dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); | |
572 | if (!dev2) | |
573 | return; | |
574 | ||
6025e2fa | 575 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
d70d141b | 576 | || acpi_device_dep(ACPI_HANDLE(dev2), ACPI_HANDLE(dev1))) |
e6ce0ce3 AH |
577 | device_link_add(dev2, dev1, link->flags); |
578 | ||
579 | put_device(dev2); | |
580 | } | |
581 | ||
582 | static void acpi_lpss_link_supplier(struct device *dev1, | |
583 | const struct lpss_device_links *link) | |
584 | { | |
585 | struct device *dev2; | |
586 | ||
587 | dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); | |
588 | if (!dev2) | |
589 | return; | |
590 | ||
6025e2fa | 591 | if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) |
d70d141b | 592 | || acpi_device_dep(ACPI_HANDLE(dev1), ACPI_HANDLE(dev2))) |
e6ce0ce3 AH |
593 | device_link_add(dev1, dev2, link->flags); |
594 | ||
595 | put_device(dev2); | |
596 | } | |
597 | ||
598 | static void acpi_lpss_create_device_links(struct acpi_device *adev, | |
599 | struct platform_device *pdev) | |
600 | { | |
601 | int i; | |
602 | ||
603 | for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { | |
604 | const struct lpss_device_links *link = &lpss_device_links[i]; | |
605 | ||
606 | if (acpi_lpss_is_supplier(adev, link)) | |
607 | acpi_lpss_link_consumer(&pdev->dev, link); | |
608 | ||
609 | if (acpi_lpss_is_consumer(adev, link)) | |
610 | acpi_lpss_link_supplier(&pdev->dev, link); | |
611 | } | |
612 | } | |
613 | ||
f58b082a RW |
614 | static int acpi_lpss_create_device(struct acpi_device *adev, |
615 | const struct acpi_device_id *id) | |
616 | { | |
b2687cd7 | 617 | const struct lpss_device_desc *dev_desc; |
f58b082a | 618 | struct lpss_private_data *pdata; |
90e97820 | 619 | struct resource_entry *rentry; |
f58b082a | 620 | struct list_head resource_list; |
8ce62f85 | 621 | struct platform_device *pdev; |
f58b082a RW |
622 | int ret; |
623 | ||
b2687cd7 | 624 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
bda3df10 RJ |
625 | if (!dev_desc) |
626 | return -EINVAL; | |
627 | ||
f58b082a RW |
628 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
629 | if (!pdata) | |
630 | return -ENOMEM; | |
631 | ||
632 | INIT_LIST_HEAD(&resource_list); | |
840baca4 | 633 | ret = acpi_dev_get_memory_resources(adev, &resource_list); |
f58b082a RW |
634 | if (ret < 0) |
635 | goto err_out; | |
636 | ||
da13b336 AS |
637 | rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node); |
638 | if (rentry) { | |
639 | if (dev_desc->prv_size_override) | |
640 | pdata->mmio_size = dev_desc->prv_size_override; | |
641 | else | |
642 | pdata->mmio_size = resource_size(rentry->res); | |
643 | pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size); | |
644 | } | |
f58b082a RW |
645 | |
646 | acpi_dev_free_resource_list(&resource_list); | |
647 | ||
d3e13ff3 | 648 | if (!pdata->mmio_base) { |
e1681599 HG |
649 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
650 | adev->pnp.type.platform_id = 0; | |
6cc401be | 651 | goto out_free; |
d3e13ff3 RW |
652 | } |
653 | ||
dd242a08 | 654 | pdata->adev = adev; |
af65cfe9 MW |
655 | pdata->dev_desc = dev_desc; |
656 | ||
03f09f73 HK |
657 | if (dev_desc->setup) |
658 | dev_desc->setup(pdata); | |
659 | ||
ff8c1af5 | 660 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a | 661 | ret = register_device_clock(adev, pdata); |
6cc401be AS |
662 | if (ret) |
663 | goto out_free; | |
f58b082a RW |
664 | } |
665 | ||
b9e95fc6 RW |
666 | /* |
667 | * This works around a known issue in ACPI tables where LPSS devices | |
668 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
669 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
670 | */ | |
1a2fa02f | 671 | acpi_device_fix_up_power(adev); |
b9e95fc6 | 672 | |
f58b082a | 673 | adev->driver_data = pdata; |
1571875b | 674 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
6cc401be AS |
675 | if (IS_ERR_OR_NULL(pdev)) { |
676 | adev->driver_data = NULL; | |
677 | ret = PTR_ERR(pdev); | |
678 | goto err_out; | |
8ce62f85 | 679 | } |
f58b082a | 680 | |
6cc401be AS |
681 | acpi_lpss_create_device_links(adev, pdev); |
682 | return 1; | |
f58b082a | 683 | |
6cc401be AS |
684 | out_free: |
685 | /* Skip the device, but continue the namespace scan */ | |
686 | ret = 0; | |
687 | err_out: | |
f58b082a RW |
688 | kfree(pdata); |
689 | return ret; | |
690 | } | |
691 | ||
1a8f8351 RW |
692 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
693 | { | |
694 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
695 | } | |
696 | ||
697 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
698 | unsigned int reg) | |
699 | { | |
700 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
701 | } | |
702 | ||
2e0f8822 RW |
703 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
704 | { | |
50861d43 | 705 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2e0f8822 RW |
706 | struct lpss_private_data *pdata; |
707 | unsigned long flags; | |
708 | int ret; | |
709 | ||
50861d43 RW |
710 | if (WARN_ON(!adev)) |
711 | return -ENODEV; | |
2e0f8822 RW |
712 | |
713 | spin_lock_irqsave(&dev->power.lock, flags); | |
714 | if (pm_runtime_suspended(dev)) { | |
715 | ret = -EAGAIN; | |
716 | goto out; | |
717 | } | |
718 | pdata = acpi_driver_data(adev); | |
719 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
720 | ret = -ENODEV; | |
721 | goto out; | |
722 | } | |
1a8f8351 | 723 | *val = __lpss_reg_read(pdata, reg); |
50861d43 | 724 | ret = 0; |
2e0f8822 RW |
725 | |
726 | out: | |
727 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
728 | return ret; | |
729 | } | |
730 | ||
731 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
732 | char *buf) | |
733 | { | |
734 | u32 ltr_value = 0; | |
735 | unsigned int reg; | |
736 | int ret; | |
737 | ||
738 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
739 | ret = lpss_reg_read(dev, reg, <r_value); | |
740 | if (ret) | |
741 | return ret; | |
742 | ||
d47e983e | 743 | return sysfs_emit(buf, "%08x\n", ltr_value); |
2e0f8822 RW |
744 | } |
745 | ||
746 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
747 | struct device_attribute *attr, char *buf) | |
748 | { | |
749 | u32 ltr_mode = 0; | |
750 | char *outstr; | |
751 | int ret; | |
752 | ||
753 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
754 | if (ret) | |
755 | return ret; | |
756 | ||
757 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
758 | return sprintf(buf, "%s\n", outstr); | |
759 | } | |
760 | ||
761 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
762 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
763 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
764 | ||
765 | static struct attribute *lpss_attrs[] = { | |
766 | &dev_attr_auto_ltr.attr, | |
767 | &dev_attr_sw_ltr.attr, | |
768 | &dev_attr_ltr_mode.attr, | |
769 | NULL, | |
770 | }; | |
771 | ||
31945d0e | 772 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
773 | .attrs = lpss_attrs, |
774 | .name = "lpss_ltr", | |
775 | }; | |
776 | ||
1a8f8351 RW |
777 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
778 | { | |
779 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
780 | u32 ltr_mode, ltr_val; | |
781 | ||
782 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
783 | if (val < 0) { | |
784 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
785 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
786 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
787 | } | |
788 | return; | |
789 | } | |
790 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
791 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
792 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
793 | val = LPSS_LTR_MAX_VAL; | |
794 | } else if (val > LPSS_LTR_MAX_VAL) { | |
795 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
796 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
797 | } else { | |
798 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
799 | } | |
800 | ltr_val |= val; | |
801 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
802 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
803 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
804 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
805 | } | |
806 | } | |
807 | ||
c78b0830 HK |
808 | #ifdef CONFIG_PM |
809 | /** | |
810 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
811 | * @dev: LPSS device | |
cb39dcdd | 812 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
813 | * |
814 | * Most LPSS devices have private registers which may loose their context when | |
815 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
816 | * prv_reg_ctx array. | |
817 | */ | |
cb39dcdd AS |
818 | static void acpi_lpss_save_ctx(struct device *dev, |
819 | struct lpss_private_data *pdata) | |
c78b0830 | 820 | { |
c78b0830 HK |
821 | unsigned int i; |
822 | ||
823 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
824 | unsigned long offset = i * sizeof(u32); | |
825 | ||
826 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
827 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
828 | pdata->prv_reg_ctx[i], offset); | |
829 | } | |
830 | } | |
831 | ||
832 | /** | |
833 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
834 | * @dev: LPSS device | |
cb39dcdd | 835 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
836 | * |
837 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
838 | */ | |
cb39dcdd AS |
839 | static void acpi_lpss_restore_ctx(struct device *dev, |
840 | struct lpss_private_data *pdata) | |
c78b0830 | 841 | { |
c78b0830 HK |
842 | unsigned int i; |
843 | ||
02b98540 AS |
844 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
845 | unsigned long offset = i * sizeof(u32); | |
846 | ||
847 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
848 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
849 | pdata->prv_reg_ctx[i], offset); | |
850 | } | |
851 | } | |
852 | ||
853 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
854 | { | |
c78b0830 HK |
855 | /* |
856 | * The following delay is needed or the subsequent write operations may | |
857 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
858 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 859 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 860 | */ |
b00855ae SK |
861 | unsigned int delay = 10; /* default 10ms delay */ |
862 | ||
863 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
864 | delay = 0; | |
865 | ||
866 | msleep(delay); | |
c78b0830 HK |
867 | } |
868 | ||
c3a49cf3 AS |
869 | static int acpi_lpss_activate(struct device *dev) |
870 | { | |
871 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
872 | int ret; | |
873 | ||
63705c40 | 874 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
875 | if (ret) |
876 | return ret; | |
877 | ||
878 | acpi_lpss_d3_to_d0_delay(pdata); | |
879 | ||
880 | /* | |
881 | * This is called only on ->probe() stage where a device is either in | |
882 | * known state defined by BIOS or most likely powered off. Due to this | |
883 | * we have to deassert reset line to be sure that ->probe() will | |
884 | * recognize the device. | |
885 | */ | |
15aa5e4c | 886 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
c3a49cf3 AS |
887 | lpss_deassert_reset(pdata); |
888 | ||
15aa5e4c HG |
889 | #ifdef CONFIG_PM |
890 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) | |
891 | acpi_lpss_save_ctx(dev, pdata); | |
892 | #endif | |
893 | ||
c3a49cf3 AS |
894 | return 0; |
895 | } | |
896 | ||
897 | static void acpi_lpss_dismiss(struct device *dev) | |
898 | { | |
cbe25ce3 | 899 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
900 | } |
901 | ||
eebb3e8d AS |
902 | /* IOSF SB for LPSS island */ |
903 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
904 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
905 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
906 | ||
907 | #define LPSS_IOSF_PMCSR 0x84 | |
908 | #define LPSS_PMCSR_D0 0 | |
909 | #define LPSS_PMCSR_D3hot 3 | |
910 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
911 | ||
912 | #define LPSS_IOSF_GPIODEF0 0x154 | |
913 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
914 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
915 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 916 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
917 | |
918 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
f11fc4bc | 919 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
920 | |
921 | static void lpss_iosf_enter_d3_state(void) | |
922 | { | |
923 | u32 value1 = 0; | |
d132d6d5 | 924 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
925 | u32 value2 = LPSS_PMCSR_D3hot; |
926 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
927 | /* | |
928 | * PMC provides an information about actual status of the LPSS devices. | |
929 | * Here we read the values related to LPSS power island, i.e. LPSS | |
930 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
931 | */ | |
86b62e5c | 932 | u32 func_dis, d3_sts_0, pmc_status; |
eebb3e8d AS |
933 | int ret; |
934 | ||
935 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
936 | if (ret) | |
937 | return; | |
938 | ||
939 | mutex_lock(&lpss_iosf_mutex); | |
940 | ||
941 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
942 | if (ret) | |
943 | goto exit; | |
944 | ||
945 | /* | |
946 | * Get the status of entire LPSS power island per device basis. | |
947 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
948 | * are already in D3hot. | |
949 | */ | |
86b62e5c | 950 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; |
eebb3e8d AS |
951 | if (pmc_status) |
952 | goto exit; | |
953 | ||
954 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
955 | LPSS_IOSF_PMCSR, value2, mask2); | |
956 | ||
957 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
958 | LPSS_IOSF_PMCSR, value2, mask2); | |
959 | ||
960 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
961 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
12864ff8 RW |
962 | |
963 | lpss_iosf_d3_entered = true; | |
964 | ||
eebb3e8d AS |
965 | exit: |
966 | mutex_unlock(&lpss_iosf_mutex); | |
967 | } | |
968 | ||
969 | static void lpss_iosf_exit_d3_state(void) | |
970 | { | |
d132d6d5 AS |
971 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
972 | LPSS_GPIODEF0_DMA_LLP; | |
973 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
974 | u32 value2 = LPSS_PMCSR_D0; |
975 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
976 | ||
977 | mutex_lock(&lpss_iosf_mutex); | |
978 | ||
12864ff8 RW |
979 | if (!lpss_iosf_d3_entered) |
980 | goto exit; | |
981 | ||
982 | lpss_iosf_d3_entered = false; | |
983 | ||
eebb3e8d AS |
984 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
985 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
986 | ||
987 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
988 | LPSS_IOSF_PMCSR, value2, mask2); | |
989 | ||
990 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
991 | LPSS_IOSF_PMCSR, value2, mask2); | |
992 | ||
12864ff8 | 993 | exit: |
eebb3e8d AS |
994 | mutex_unlock(&lpss_iosf_mutex); |
995 | } | |
996 | ||
12864ff8 | 997 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 998 | { |
cb39dcdd AS |
999 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1000 | int ret; | |
c78b0830 | 1001 | |
cb39dcdd AS |
1002 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
1003 | acpi_lpss_save_ctx(dev, pdata); | |
1004 | ||
a192aa92 | 1005 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
1006 | |
1007 | /* | |
1008 | * This call must be last in the sequence, otherwise PMC will return | |
1009 | * wrong status for devices being about to be powered off. See | |
1010 | * lpss_iosf_enter_d3_state() for further information. | |
1011 | */ | |
12864ff8 | 1012 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
a09c5913 | 1013 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1014 | lpss_iosf_enter_d3_state(); |
1015 | ||
1016 | return ret; | |
c78b0830 HK |
1017 | } |
1018 | ||
12864ff8 | 1019 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 1020 | { |
cb39dcdd AS |
1021 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
1022 | int ret; | |
c78b0830 | 1023 | |
eebb3e8d AS |
1024 | /* |
1025 | * This call is kept first to be in symmetry with | |
1026 | * acpi_lpss_runtime_suspend() one. | |
1027 | */ | |
12864ff8 | 1028 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
1029 | lpss_iosf_exit_d3_state(); |
1030 | ||
63705c40 | 1031 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
1032 | if (ret) |
1033 | return ret; | |
1034 | ||
02b98540 AS |
1035 | acpi_lpss_d3_to_d0_delay(pdata); |
1036 | ||
15aa5e4c | 1037 | if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) |
cb39dcdd AS |
1038 | acpi_lpss_restore_ctx(dev, pdata); |
1039 | ||
a192aa92 RW |
1040 | return 0; |
1041 | } | |
1042 | ||
1043 | #ifdef CONFIG_PM_SLEEP | |
48402cee | 1044 | static int acpi_lpss_do_suspend_late(struct device *dev) |
a192aa92 | 1045 | { |
05087360 RW |
1046 | int ret; |
1047 | ||
fa2bfead | 1048 | if (dev_pm_skip_suspend(dev)) |
05087360 | 1049 | return 0; |
a192aa92 | 1050 | |
05087360 | 1051 | ret = pm_generic_suspend_late(dev); |
12864ff8 | 1052 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
1053 | } |
1054 | ||
48402cee HG |
1055 | static int acpi_lpss_suspend_late(struct device *dev) |
1056 | { | |
1057 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1058 | ||
1059 | if (pdata->dev_desc->resume_from_noirq) | |
1060 | return 0; | |
1061 | ||
1062 | return acpi_lpss_do_suspend_late(dev); | |
1063 | } | |
1064 | ||
1065 | static int acpi_lpss_suspend_noirq(struct device *dev) | |
1066 | { | |
1067 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1068 | int ret; | |
1069 | ||
1070 | if (pdata->dev_desc->resume_from_noirq) { | |
c95b7595 RW |
1071 | /* |
1072 | * The driver's ->suspend_late callback will be invoked by | |
1073 | * acpi_lpss_do_suspend_late(), with the assumption that the | |
1074 | * driver really wanted to run that code in ->suspend_noirq, but | |
1075 | * it could not run after acpi_dev_suspend() and the driver | |
1076 | * expected the latter to be called in the "late" phase. | |
1077 | */ | |
48402cee HG |
1078 | ret = acpi_lpss_do_suspend_late(dev); |
1079 | if (ret) | |
1080 | return ret; | |
1081 | } | |
1082 | ||
1083 | return acpi_subsys_suspend_noirq(dev); | |
1084 | } | |
1085 | ||
1086 | static int acpi_lpss_do_resume_early(struct device *dev) | |
a192aa92 | 1087 | { |
12864ff8 | 1088 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1089 | |
1090 | return ret ? ret : pm_generic_resume_early(dev); | |
1091 | } | |
48402cee HG |
1092 | |
1093 | static int acpi_lpss_resume_early(struct device *dev) | |
1094 | { | |
1095 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1096 | ||
1097 | if (pdata->dev_desc->resume_from_noirq) | |
1098 | return 0; | |
1099 | ||
76c70cb5 | 1100 | if (dev_pm_skip_resume(dev)) |
6e176bf8 RW |
1101 | return 0; |
1102 | ||
48402cee HG |
1103 | return acpi_lpss_do_resume_early(dev); |
1104 | } | |
1105 | ||
1106 | static int acpi_lpss_resume_noirq(struct device *dev) | |
1107 | { | |
1108 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1109 | int ret; | |
1110 | ||
3cd7957e | 1111 | /* Follow acpi_subsys_resume_noirq(). */ |
76c70cb5 | 1112 | if (dev_pm_skip_resume(dev)) |
3cd7957e RW |
1113 | return 0; |
1114 | ||
3cd7957e | 1115 | ret = pm_generic_resume_noirq(dev); |
48402cee HG |
1116 | if (ret) |
1117 | return ret; | |
1118 | ||
3cd7957e RW |
1119 | if (!pdata->dev_desc->resume_from_noirq) |
1120 | return 0; | |
48402cee | 1121 | |
3cd7957e RW |
1122 | /* |
1123 | * The driver's ->resume_early callback will be invoked by | |
1124 | * acpi_lpss_do_resume_early(), with the assumption that the driver | |
1125 | * really wanted to run that code in ->resume_noirq, but it could not | |
1126 | * run before acpi_dev_resume() and the driver expected the latter to be | |
1127 | * called in the "early" phase. | |
1128 | */ | |
1129 | return acpi_lpss_do_resume_early(dev); | |
1130 | } | |
1131 | ||
1132 | static int acpi_lpss_do_restore_early(struct device *dev) | |
1133 | { | |
1134 | int ret = acpi_lpss_resume(dev); | |
1135 | ||
1136 | return ret ? ret : pm_generic_restore_early(dev); | |
48402cee HG |
1137 | } |
1138 | ||
3cd7957e RW |
1139 | static int acpi_lpss_restore_early(struct device *dev) |
1140 | { | |
1141 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1142 | ||
1143 | if (pdata->dev_desc->resume_from_noirq) | |
1144 | return 0; | |
1145 | ||
1146 | return acpi_lpss_do_restore_early(dev); | |
48402cee HG |
1147 | } |
1148 | ||
3cd7957e RW |
1149 | static int acpi_lpss_restore_noirq(struct device *dev) |
1150 | { | |
1151 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1152 | int ret; | |
1153 | ||
1154 | ret = pm_generic_restore_noirq(dev); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
1158 | if (!pdata->dev_desc->resume_from_noirq) | |
1159 | return 0; | |
1160 | ||
1161 | /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ | |
1162 | return acpi_lpss_do_restore_early(dev); | |
1163 | } | |
c95b7595 RW |
1164 | |
1165 | static int acpi_lpss_do_poweroff_late(struct device *dev) | |
1166 | { | |
1167 | int ret = pm_generic_poweroff_late(dev); | |
1168 | ||
1169 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); | |
1170 | } | |
1171 | ||
1172 | static int acpi_lpss_poweroff_late(struct device *dev) | |
1173 | { | |
1174 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1175 | ||
fa2bfead | 1176 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1177 | return 0; |
1178 | ||
1179 | if (pdata->dev_desc->resume_from_noirq) | |
1180 | return 0; | |
1181 | ||
1182 | return acpi_lpss_do_poweroff_late(dev); | |
1183 | } | |
1184 | ||
1185 | static int acpi_lpss_poweroff_noirq(struct device *dev) | |
1186 | { | |
1187 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1188 | ||
fa2bfead | 1189 | if (dev_pm_skip_suspend(dev)) |
c95b7595 RW |
1190 | return 0; |
1191 | ||
1192 | if (pdata->dev_desc->resume_from_noirq) { | |
1193 | /* This is analogous to the acpi_lpss_suspend_noirq() case. */ | |
1194 | int ret = acpi_lpss_do_poweroff_late(dev); | |
bb415ed5 | 1195 | |
c95b7595 RW |
1196 | if (ret) |
1197 | return ret; | |
1198 | } | |
1199 | ||
1200 | return pm_generic_poweroff_noirq(dev); | |
1201 | } | |
a192aa92 RW |
1202 | #endif /* CONFIG_PM_SLEEP */ |
1203 | ||
1204 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
1205 | { | |
1206 | int ret = pm_generic_runtime_suspend(dev); | |
1207 | ||
1208 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
1209 | } | |
1210 | ||
1211 | static int acpi_lpss_runtime_resume(struct device *dev) | |
1212 | { | |
12864ff8 | 1213 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
1214 | |
1215 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 1216 | } |
c78b0830 HK |
1217 | #endif /* CONFIG_PM */ |
1218 | ||
1219 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
1220 | #ifdef CONFIG_PM |
1221 | .activate = acpi_lpss_activate, | |
1222 | .dismiss = acpi_lpss_dismiss, | |
1223 | #endif | |
c78b0830 | 1224 | .ops = { |
5de21bb9 | 1225 | #ifdef CONFIG_PM |
c78b0830 | 1226 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 1227 | .prepare = acpi_subsys_prepare, |
e4da817d | 1228 | .complete = acpi_subsys_complete, |
c78b0830 | 1229 | .suspend = acpi_subsys_suspend, |
f4168b61 | 1230 | .suspend_late = acpi_lpss_suspend_late, |
48402cee HG |
1231 | .suspend_noirq = acpi_lpss_suspend_noirq, |
1232 | .resume_noirq = acpi_lpss_resume_noirq, | |
f4168b61 | 1233 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 1234 | .freeze = acpi_subsys_freeze, |
c95b7595 RW |
1235 | .poweroff = acpi_subsys_poweroff, |
1236 | .poweroff_late = acpi_lpss_poweroff_late, | |
1237 | .poweroff_noirq = acpi_lpss_poweroff_noirq, | |
3cd7957e RW |
1238 | .restore_noirq = acpi_lpss_restore_noirq, |
1239 | .restore_early = acpi_lpss_restore_early, | |
c78b0830 | 1240 | #endif |
c78b0830 HK |
1241 | .runtime_suspend = acpi_lpss_runtime_suspend, |
1242 | .runtime_resume = acpi_lpss_runtime_resume, | |
1243 | #endif | |
1244 | }, | |
1245 | }; | |
1246 | ||
2e0f8822 RW |
1247 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
1248 | unsigned long action, void *data) | |
1249 | { | |
1250 | struct platform_device *pdev = to_platform_device(data); | |
1251 | struct lpss_private_data *pdata; | |
1252 | struct acpi_device *adev; | |
1253 | const struct acpi_device_id *id; | |
2e0f8822 RW |
1254 | |
1255 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
1256 | if (!id || !id->driver_data) | |
1257 | return 0; | |
1258 | ||
50861d43 RW |
1259 | adev = ACPI_COMPANION(&pdev->dev); |
1260 | if (!adev) | |
2e0f8822 RW |
1261 | return 0; |
1262 | ||
1263 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 1264 | if (!pdata) |
2e0f8822 RW |
1265 | return 0; |
1266 | ||
cb39dcdd AS |
1267 | if (pdata->mmio_base && |
1268 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
1269 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
1270 | return 0; | |
1271 | } | |
1272 | ||
c78b0830 | 1273 | switch (action) { |
de16d552 | 1274 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 1275 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 1276 | break; |
de16d552 | 1277 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 1278 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 1279 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
1280 | break; |
1281 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 1282 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 1283 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
1284 | return sysfs_create_group(&pdev->dev.kobj, |
1285 | &lpss_attr_group); | |
01ac170b | 1286 | break; |
c78b0830 | 1287 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 1288 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 1289 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 1290 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 1291 | break; |
c78b0830 HK |
1292 | default: |
1293 | break; | |
1294 | } | |
2e0f8822 | 1295 | |
c78b0830 | 1296 | return 0; |
2e0f8822 RW |
1297 | } |
1298 | ||
1299 | static struct notifier_block acpi_lpss_nb = { | |
1300 | .notifier_call = acpi_lpss_platform_notify, | |
1301 | }; | |
1302 | ||
1a8f8351 RW |
1303 | static void acpi_lpss_bind(struct device *dev) |
1304 | { | |
1305 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
1306 | ||
ff8c1af5 | 1307 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
1308 | return; |
1309 | ||
1310 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
1311 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
1312 | else | |
1313 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1314 | } | |
1315 | ||
1316 | static void acpi_lpss_unbind(struct device *dev) | |
1317 | { | |
1318 | dev->power.set_latency_tolerance = NULL; | |
1319 | } | |
1320 | ||
f58b082a RW |
1321 | static struct acpi_scan_handler lpss_handler = { |
1322 | .ids = acpi_lpss_device_ids, | |
1323 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1324 | .bind = acpi_lpss_bind, |
1325 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1326 | }; |
1327 | ||
1328 | void __init acpi_lpss_init(void) | |
1329 | { | |
eebb3e8d AS |
1330 | const struct x86_cpu_id *id; |
1331 | int ret; | |
1332 | ||
cf0a9565 | 1333 | ret = lpss_atom_clk_init(); |
eebb3e8d AS |
1334 | if (ret) |
1335 | return; | |
1336 | ||
1337 | id = x86_match_cpu(lpss_cpu_ids); | |
1338 | if (id) | |
1339 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1340 | ||
1341 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1342 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1343 | } |
d6ddaaac RW |
1344 | |
1345 | #else | |
1346 | ||
1347 | static struct acpi_scan_handler lpss_handler = { | |
1348 | .ids = acpi_lpss_device_ids, | |
1349 | }; | |
1350 | ||
1351 | void __init acpi_lpss_init(void) | |
1352 | { | |
1353 | acpi_scan_add_handler(&lpss_handler); | |
1354 | } | |
1355 | ||
1356 | #endif /* CONFIG_X86_INTEL_LPSS */ |