[linux-block.git] / drivers / accel / ivpu / vpu_boot_api.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright (c) 2020-2023, Intel Corporation.
 */

#ifndef VPU_BOOT_API_H
#define VPU_BOOT_API_H

/*
 * =========== FW API version information beginning ================
 *  The bellow values will be used to construct the version info this way:
 *  fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
 *  VPU_BOOT_API_VER_MINOR;
 *  VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
 *  This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
 *  If a header is missing this info we ignore the header, if a header is missing or contains
 *  partial info a build error will be generated.
 */

/*
 * Major version changes that break backward compatibility.
 * Major version must start from 1 and can only be incremented.
 */
#define VPU_BOOT_API_VER_MAJOR 3

/*
 * Minor version changes when API backward compatibility is preserved.
 * Resets to 0 if Major version is incremented.
 */
#define VPU_BOOT_API_VER_MINOR 22

/*
 * API header changed (field names, documentation, formatting) but API itself has not been changed
 */
#define VPU_BOOT_API_VER_PATCH 0

/*
 * Index in the API version table
 * Must be unique for each API
 */
#define VPU_BOOT_API_VER_INDEX 0
/* ------------ FW API version information end ---------------------*/

#pragma pack(push, 4)

/*
 * Firmware image header format
 */
#define VPU_FW_HEADER_SIZE    4096
#define VPU_FW_HEADER_VERSION 0x1
#define VPU_FW_VERSION_SIZE   32
#define VPU_FW_API_VER_NUM    16

struct vpu_firmware_header {
	u32 header_version;
	u32 image_format;
	u64 image_load_address;
	u32 image_size;
	u64 entry_point;
	u8 vpu_version[VPU_FW_VERSION_SIZE];
	u32 compression_type;
	u64 firmware_version_load_address;
	u32 firmware_version_size;
	u64 boot_params_load_address;
	u32 api_version[VPU_FW_API_VER_NUM];
	/* Size of memory require for firmware execution */
	u32 runtime_size;
	u32 shave_nn_fw_size;
	/*
	 * Size of primary preemption buffer, assuming a 2-job submission queue.
	 * NOTE: host driver is expected to adapt size accordingly to actual
	 * submission queue size and device capabilities.
	 */
	u32 preemption_buffer_1_size;
	/*
	 * Size of secondary preemption buffer, assuming a 2-job submission queue.
	 * NOTE: host driver is expected to adapt size accordingly to actual
	 * submission queue size and device capabilities.
	 */
	u32 preemption_buffer_2_size;
	/* Space reserved for future preemption-related fields. */
	u32 preemption_reserved[6];
};

/*
 * Firmware boot parameters format
 */

#define VPU_BOOT_PLL_COUNT     3
#define VPU_BOOT_PLL_OUT_COUNT 4

/** Values for boot_type field */
#define VPU_BOOT_TYPE_COLDBOOT 0
#define VPU_BOOT_TYPE_WARMBOOT 1

/** Value for magic filed */
#define VPU_BOOT_PARAMS_MAGIC 0x10000

/** VPU scheduling mode. By default, OS scheduling is used. */
#define VPU_SCHEDULING_MODE_OS 0
#define VPU_SCHEDULING_MODE_HW 1

enum VPU_BOOT_L2_CACHE_CFG_TYPE {
	VPU_BOOT_L2_CACHE_CFG_UPA = 0,
	VPU_BOOT_L2_CACHE_CFG_NN = 1,
	VPU_BOOT_L2_CACHE_CFG_NUM = 2
};

/** VPU MCA ECC signalling mode. By default, no signalling is used */
enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
	VPU_BOOT_MCA_ECC_NONE = 0,
	VPU_BOOT_MCA_ECC_CORR = 1,
	VPU_BOOT_MCA_ECC_FATAL = 2,
	VPU_BOOT_MCA_ECC_BOTH = 3
};

/**
 * Logging destinations.
 *
 * Logging output can be directed to different logging destinations. This enum
 * defines the list of logging destinations supported by the VPU firmware (NOTE:
 * a specific VPU FW binary may support only a subset of such output
 * destinations, depending on the target platform and compile options).
 */
enum vpu_trace_destination {
	VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
	VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
	VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
};

/*
 * Processor bit shifts (for loggable HW components).
 */
#define VPU_TRACE_PROC_BIT_ARM	     0
#define VPU_TRACE_PROC_BIT_LRT	     1
#define VPU_TRACE_PROC_BIT_LNN	     2
#define VPU_TRACE_PROC_BIT_SHV_0     3
#define VPU_TRACE_PROC_BIT_SHV_1     4
#define VPU_TRACE_PROC_BIT_SHV_2     5
#define VPU_TRACE_PROC_BIT_SHV_3     6
#define VPU_TRACE_PROC_BIT_SHV_4     7
#define VPU_TRACE_PROC_BIT_SHV_5     8
#define VPU_TRACE_PROC_BIT_SHV_6     9
#define VPU_TRACE_PROC_BIT_SHV_7     10
#define VPU_TRACE_PROC_BIT_SHV_8     11
#define VPU_TRACE_PROC_BIT_SHV_9     12
#define VPU_TRACE_PROC_BIT_SHV_10    13
#define VPU_TRACE_PROC_BIT_SHV_11    14
#define VPU_TRACE_PROC_BIT_SHV_12    15
#define VPU_TRACE_PROC_BIT_SHV_13    16
#define VPU_TRACE_PROC_BIT_SHV_14    17
#define VPU_TRACE_PROC_BIT_SHV_15    18
#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23

/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
#define VPU_TRACE_PROC_BIT_30XX_LAST  VPU_TRACE_PROC_BIT_SHV_15
#define VPU_TRACE_PROC_BIT_KMB_FIRST  VPU_TRACE_PROC_BIT_30XX_FIRST
#define VPU_TRACE_PROC_BIT_KMB_LAST   VPU_TRACE_PROC_BIT_30XX_LAST

struct vpu_boot_l2_cache_config {
	u8 use;
	u8 cfg;
};

struct vpu_warm_boot_section {
	u32 src;
	u32 dst;
	u32 size;
	u32 core_id;
	u32 is_clear_op;
};

/*
 * When HW scheduling mode is enabled, a present period is defined.
 * It will be used by VPU to swap between normal and focus priorities
 * to prevent starving of normal priority band (when implemented).
 * Host must provide a valid value at boot time in
 * `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
 * defined range a default value will be used. Here we define the min. and max.
 * allowed values and the and default value of the present period. Units are milliseconds.
 */
#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
#define VPU_PRESENT_CALL_PERIOD_MS_MIN	   16
#define VPU_PRESENT_CALL_PERIOD_MS_MAX	   10000

/**
 * Macros to enable various power profiles within the NPU.
 * To be defined as part of 32 bit mask.
 */
#define POWER_PROFILE_SURVIVABILITY 0x1

struct vpu_boot_params {
	u32 magic;
	u32 vpu_id;
	u32 vpu_count;
	u32 pad0[5];
	/* Clock frequencies: 0x20 - 0xFF */
	u32 frequency;
	u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
	u32 perf_clk_frequency;
	u32 pad1[42];
	/* Memory regions: 0x100 - 0x1FF */
	u64 ipc_header_area_start;
	u32 ipc_header_area_size;
	u64 shared_region_base;
	u32 shared_region_size;
	u64 ipc_payload_area_start;
	u32 ipc_payload_area_size;
	u64 global_aliased_pio_base;
	u32 global_aliased_pio_size;
	u32 autoconfig;
	struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
	u64 global_memory_allocator_base;
	u32 global_memory_allocator_size;
	/**
	 * ShaveNN FW section VPU base address
	 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
	 */
	u64 shave_nn_fw_base;
	u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
	u32 pad2[43];
	/* IRQ re-direct numbers: 0x200 - 0x2FF */
	s32 watchdog_irq_mss;
	s32 watchdog_irq_nce;
	/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
	u32 host_to_vpu_irq;
	/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
	u32 job_done_irq;
	/* VPU -> ARM IRQ line to use to request MMU update. */
	u32 mmu_update_request_irq;
	/* ARM -> VPU IRQ line to use to notify of MMU update completion. */
	u32 mmu_update_done_irq;
	/* ARM -> VPU IRQ line to use to request power level change. */
	u32 set_power_level_irq;
	/* VPU -> ARM IRQ line to use to notify of power level change completion. */
	u32 set_power_level_done_irq;
	/* VPU -> ARM IRQ line to use to notify of VPU idle state change */
	u32 set_vpu_idle_update_irq;
	/* VPU -> ARM IRQ line to use to request counter reset. */
	u32 metric_query_event_irq;
	/* ARM -> VPU IRQ line to use to notify of counter reset completion. */
	u32 metric_query_event_done_irq;
	/* VPU -> ARM IRQ line to use to notify of preemption completion. */
	u32 preemption_done_irq;
	/* Padding. */
	u32 pad3[52];
	/* Silicon information: 0x300 - 0x3FF */
	u32 host_version_id;
	u32 si_stepping;
	u64 device_id;
	u64 feature_exclusion;
	u64 sku;
	/** PLL ratio for minimum clock frequency */
	u32 min_freq_pll_ratio;
	/** PLL ratio for maximum clock frequency */
	u32 max_freq_pll_ratio;
	/**
	 * Initial log level threshold (messages with log level severity less than
	 * the threshold will not be logged); applies to every enabled logging
	 * destination and loggable HW component. See 'mvLog_t' enum for acceptable
	 * values.
	 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
	 */
	u32 default_trace_level;
	u32 boot_type;
	u64 punit_telemetry_sram_base;
	u64 punit_telemetry_sram_size;
	u32 vpu_telemetry_enable;
	u64 crit_tracing_buff_addr;
	u32 crit_tracing_buff_size;
	u64 verbose_tracing_buff_addr;
	u32 verbose_tracing_buff_size;
	u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
	/**
	 * Mask of destinations to which logging messages are delivered; bitwise OR
	 * of values defined in vpu_trace_destination enum.
	 */
	u32 trace_destination_mask;
	/**
	 * Mask of hardware components for which logging is enabled; bitwise OR of
	 * bits defined by the VPU_TRACE_PROC_BIT_* macros.
	 */
	u64 trace_hw_component_mask;
	/** Mask of trace message formats supported by the driver */
	u64 tracing_buff_message_format_mask;
	u64 trace_reserved_1[2];
	/**
	 * Period at which the VPU reads the temp sensor values into MMIO, on
	 * platforms where that is necessary (in ms). 0 to disable reads.
	 */
	u32 temp_sensor_period_ms;
	/** PLL ratio for efficient clock frequency */
	u32 pn_freq_pll_ratio;
	/** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */
	u32 dvfs_mode;
	/**
	 * Depending on DVFS Mode:
	 * On-demand: Default if 0.
	 *    Bit 0-7   - uint8_t: Highest residency percent
	 *    Bit 8-15  - uint8_t: High residency percent
	 *    Bit 16-23 - uint8_t: Low residency percent
	 *    Bit 24-31 - uint8_t: Lowest residency percent
	 *    Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
	 *    Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
	 *    Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
	 *    Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
	 *    Bit 48-55 - uint8_t: Period (ms) for residency decisions
	 *    Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
	 * Power Save/Max Performance: Unused
	 */
	u64 dvfs_param;
	/**
	 * D0i3 delayed entry
	 * Bit0: Disable CPU state save on D0i2 entry flow.
	 *       0: Every D0i2 entry saves state. Save state IPC message ignored.
	 *       1: IPC message required to save state on D0i3 entry flow.
	 */
	u32 d0i3_delayed_entry;
	/* Time spent by VPU in D0i3 state */
	u64 d0i3_residency_time_us;
	/* Value of VPU perf counter at the time of entering D0i3 state . */
	u64 d0i3_entry_vpu_ts;
	/*
	 * The system time of the host operating system in microseconds.
	 * E.g the number of microseconds since 1st of January 1970, or whatever date the
	 * host operating system uses to maintain system time.
	 * This value will be used to track system time on the VPU.
	 * The KMD is required to update this value on every VPU reset.
	 */
	u64 system_time_us;
	u32 pad4[18];
	/* Warm boot information: 0x400 - 0x43F */
	u32 warm_boot_sections_count;
	u32 warm_boot_start_address_reference;
	u32 warm_boot_section_info_address_offset;
	u32 pad5[13];
	/* Power States transitions timestamps: 0x440 - 0x46F*/
	struct {
		/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
		u64 vpu_active_state_requested;
		/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
		u64 vpu_active_state_achieved;
		/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
		u64 vpu_idle_state_requested;
		/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
		u64 vpu_idle_state_achieved;
		/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
		u64 vpu_standby_state_requested;
		/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
		u64 vpu_standby_state_achieved;
	} power_states_timestamps;
	/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
	u32 vpu_scheduling_mode;
	/* Present call period in milliseconds. */
	u32 vpu_focus_present_timer_ms;
	/* VPU ECC Signaling */
	u32 vpu_uses_ecc_mca_signal;
	/* Values defined by POWER_PROFILE* macros */
	u32 power_profile;
	/* Microsecond value for DCT active cycle */
	u32 dct_active_us;
	/* Microsecond value for DCT inactive cycle */
	u32 dct_inactive_us;
	/* Unused/reserved: 0x488 - 0xFFF */
	u32 pad6[734];
};

/*
 * Magic numbers set between host and vpu to detect corruptio of tracing init
 */

#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)

/* Tracing buffer message format definitions */
#define VPU_TRACING_FORMAT_STRING 0
#define VPU_TRACING_FORMAT_MIPI	  2
/*
 * Header of the tracing buffer.
 * The below defined header will be stored at the beginning of
 * each allocated tracing buffer, followed by a series of 256b
 * of ASCII trace message entries.
 */
struct vpu_tracing_buffer_header {
	/**
	 * Magic number set by host to detect corruption
	 * @see VPU_TRACING_BUFFER_CANARY
	 */
	u32 host_canary_start;
	/* offset from start of buffer for trace entries */
	u32 read_index;
	u32 pad_to_cache_line_size_0[14];
	/* End of first cache line */

	/**
	 * Magic number set by host to detect corruption
	 * @see VPU_TRACING_BUFFER_CANARY
	 */
	u32 vpu_canary_start;
	/* offset from start of buffer from write start */
	u32 write_index;
	/* counter for buffer wrapping */
	u32 wrap_count;
	/* legacy field - do not use */
	u32 reserved_0;
	/**
	 * Size of the log buffer include this header (@header_size) and space
	 * reserved for all messages. If @alignment` is greater that 0 the @Size
	 * must be multiple of @Alignment.
	 */
	u32 size;
	/* Header version */
	u16 header_version;
	/* Header size */
	u16 header_size;
	/*
	 * Format of the messages in the trace buffer
	 * 0 - null terminated string
	 * 1 - size + null terminated string
	 * 2 - MIPI-SysT encoding
	 */
	u32 format;
	/*
	 * Message alignment
	 * 0 - messages are place 1 after another
	 * n - every message starts and multiple on offset
	 */
	u32 alignment; /* 64, 128, 256 */
	/* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
	char name[16];
	u32 pad_to_cache_line_size_1[4];
	/* End of second cache line */
};

#pragma pack(pop)

#endif
Commit	Line	Data
02d5b0aa JL	1	/* SPDX-License-Identifier: MIT */
02d5b0aa JL	2	/*
3bd0edf8	3	* Copyright (c) 2020-2023, Intel Corporation.
02d5b0aa JL	4	*/
	5
	6	#ifndef VPU_BOOT_API_H
	7	#define VPU_BOOT_API_H
	8
	9	/*
	10	* =========== FW API version information beginning ================
	11	* The bellow values will be used to construct the version info this way:
	12	* fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) \|
	13	* VPU_BOOT_API_VER_MINOR;
8c63b474 KP	14	* VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
	15	* This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
	16	* If a header is missing this info we ignore the header, if a header is missing or contains
	17	* partial info a build error will be generated.
02d5b0aa JL	18	*/
	19
	20	/*
	21	* Major version changes that break backward compatibility.
	22	* Major version must start from 1 and can only be incremented.
	23	*/
	24	#define VPU_BOOT_API_VER_MAJOR 3
	25
	26	/*
	27	* Minor version changes when API backward compatibility is preserved.
	28	* Resets to 0 if Major version is incremented.
	29	*/
3bd0edf8	30	#define VPU_BOOT_API_VER_MINOR 22
02d5b0aa JL	31
	32	/*
	33	* API header changed (field names, documentation, formatting) but API itself has not been changed
	34	*/
3bd0edf8	35	#define VPU_BOOT_API_VER_PATCH 0
02d5b0aa JL	36
	37	/*
	38	* Index in the API version table
	39	* Must be unique for each API
	40	*/
	41	#define VPU_BOOT_API_VER_INDEX 0
	42	/* ------------ FW API version information end ---------------------*/
	43
3bd0edf8	44	#pragma pack(push, 4)
02d5b0aa JL	45
	46	/*
	47	* Firmware image header format
	48	*/
	49	#define VPU_FW_HEADER_SIZE 4096
	50	#define VPU_FW_HEADER_VERSION 0x1
	51	#define VPU_FW_VERSION_SIZE 32
	52	#define VPU_FW_API_VER_NUM 16
	53
	54	struct vpu_firmware_header {
	55	u32 header_version;
	56	u32 image_format;
	57	u64 image_load_address;
	58	u32 image_size;
	59	u64 entry_point;
	60	u8 vpu_version[VPU_FW_VERSION_SIZE];
	61	u32 compression_type;
	62	u64 firmware_version_load_address;
	63	u32 firmware_version_size;
	64	u64 boot_params_load_address;
	65	u32 api_version[VPU_FW_API_VER_NUM];
	66	/* Size of memory require for firmware execution */
	67	u32 runtime_size;
	68	u32 shave_nn_fw_size;
3bd0edf8 JL	69	/*
	70	* Size of primary preemption buffer, assuming a 2-job submission queue.
	71	* NOTE: host driver is expected to adapt size accordingly to actual
	72	* submission queue size and device capabilities.
	73	*/
8c63b474	74	u32 preemption_buffer_1_size;
3bd0edf8 JL	75	/*
	76	* Size of secondary preemption buffer, assuming a 2-job submission queue.
	77	* NOTE: host driver is expected to adapt size accordingly to actual
	78	* submission queue size and device capabilities.
	79	*/
8c63b474 KP	80	u32 preemption_buffer_2_size;
	81	/* Space reserved for future preemption-related fields. */
	82	u32 preemption_reserved[6];
02d5b0aa JL	83	};
	84
	85	/*
	86	* Firmware boot parameters format
	87	*/
	88
	89	#define VPU_BOOT_PLL_COUNT 3
	90	#define VPU_BOOT_PLL_OUT_COUNT 4
	91
	92	/** Values for boot_type field */
	93	#define VPU_BOOT_TYPE_COLDBOOT 0
	94	#define VPU_BOOT_TYPE_WARMBOOT 1
	95
	96	/** Value for magic filed */
	97	#define VPU_BOOT_PARAMS_MAGIC 0x10000
	98
	99	/** VPU scheduling mode. By default, OS scheduling is used. */
	100	#define VPU_SCHEDULING_MODE_OS 0
	101	#define VPU_SCHEDULING_MODE_HW 1
	102
	103	enum VPU_BOOT_L2_CACHE_CFG_TYPE {
	104	VPU_BOOT_L2_CACHE_CFG_UPA = 0,
	105	VPU_BOOT_L2_CACHE_CFG_NN = 1,
	106	VPU_BOOT_L2_CACHE_CFG_NUM = 2
	107	};
	108
8c63b474 KP	109	/** VPU MCA ECC signalling mode. By default, no signalling is used */
	110	enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
	111	VPU_BOOT_MCA_ECC_NONE = 0,
	112	VPU_BOOT_MCA_ECC_CORR = 1,
	113	VPU_BOOT_MCA_ECC_FATAL = 2,
	114	VPU_BOOT_MCA_ECC_BOTH = 3
	115	};
	116
02d5b0aa JL	117	/**
	118	* Logging destinations.
	119	*
	120	* Logging output can be directed to different logging destinations. This enum
	121	* defines the list of logging destinations supported by the VPU firmware (NOTE:
	122	* a specific VPU FW binary may support only a subset of such output
	123	* destinations, depending on the target platform and compile options).
	124	*/
	125	enum vpu_trace_destination {
	126	VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
	127	VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
	128	VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
	129	};
	130
	131	/*
	132	* Processor bit shifts (for loggable HW components).
	133	*/
	134	#define VPU_TRACE_PROC_BIT_ARM 0
	135	#define VPU_TRACE_PROC_BIT_LRT 1
	136	#define VPU_TRACE_PROC_BIT_LNN 2
	137	#define VPU_TRACE_PROC_BIT_SHV_0 3
	138	#define VPU_TRACE_PROC_BIT_SHV_1 4
	139	#define VPU_TRACE_PROC_BIT_SHV_2 5
	140	#define VPU_TRACE_PROC_BIT_SHV_3 6
	141	#define VPU_TRACE_PROC_BIT_SHV_4 7
	142	#define VPU_TRACE_PROC_BIT_SHV_5 8
	143	#define VPU_TRACE_PROC_BIT_SHV_6 9
	144	#define VPU_TRACE_PROC_BIT_SHV_7 10
	145	#define VPU_TRACE_PROC_BIT_SHV_8 11
	146	#define VPU_TRACE_PROC_BIT_SHV_9 12
	147	#define VPU_TRACE_PROC_BIT_SHV_10 13
	148	#define VPU_TRACE_PROC_BIT_SHV_11 14
	149	#define VPU_TRACE_PROC_BIT_SHV_12 15
	150	#define VPU_TRACE_PROC_BIT_SHV_13 16
	151	#define VPU_TRACE_PROC_BIT_SHV_14 17
	152	#define VPU_TRACE_PROC_BIT_SHV_15 18
	153	#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
	154	#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
	155	#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
	156	#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
	157	#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
	158
8c63b474 KP	159	/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
	160	#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
	161	#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15
	162	#define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_30XX_FIRST
	163	#define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_30XX_LAST
02d5b0aa JL	164
	165	struct vpu_boot_l2_cache_config {
	166	u8 use;
	167	u8 cfg;
	168	};
	169
	170	struct vpu_warm_boot_section {
	171	u32 src;
	172	u32 dst;
	173	u32 size;
	174	u32 core_id;
	175	u32 is_clear_op;
	176	};
	177
8c63b474 KP	178	/*
	179	* When HW scheduling mode is enabled, a present period is defined.
	180	* It will be used by VPU to swap between normal and focus priorities
	181	* to prevent starving of normal priority band (when implemented).
	182	* Host must provide a valid value at boot time in
	183	* `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
	184	* defined range a default value will be used. Here we define the min. and max.
	185	* allowed values and the and default value of the present period. Units are milliseconds.
	186	*/
	187	#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
	188	#define VPU_PRESENT_CALL_PERIOD_MS_MIN 16
	189	#define VPU_PRESENT_CALL_PERIOD_MS_MAX 10000
	190
	191	/**
3bd0edf8	192	* Macros to enable various power profiles within the NPU.
8c63b474 KP	193	* To be defined as part of 32 bit mask.
8c63b474 KP	194	*/
3bd0edf8	195	#define POWER_PROFILE_SURVIVABILITY 0x1
8c63b474	196
02d5b0aa JL	197	struct vpu_boot_params {
	198	u32 magic;
	199	u32 vpu_id;
	200	u32 vpu_count;
	201	u32 pad0[5];
	202	/* Clock frequencies: 0x20 - 0xFF */
	203	u32 frequency;
	204	u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
	205	u32 perf_clk_frequency;
	206	u32 pad1[42];
	207	/* Memory regions: 0x100 - 0x1FF */
	208	u64 ipc_header_area_start;
	209	u32 ipc_header_area_size;
	210	u64 shared_region_base;
	211	u32 shared_region_size;
	212	u64 ipc_payload_area_start;
	213	u32 ipc_payload_area_size;
	214	u64 global_aliased_pio_base;
	215	u32 global_aliased_pio_size;
	216	u32 autoconfig;
	217	struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
	218	u64 global_memory_allocator_base;
	219	u32 global_memory_allocator_size;
	220	/**
	221	* ShaveNN FW section VPU base address
	222	* On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
	223	*/
	224	u64 shave_nn_fw_base;
	225	u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
	226	u32 pad2[43];
	227	/* IRQ re-direct numbers: 0x200 - 0x2FF */
	228	s32 watchdog_irq_mss;
	229	s32 watchdog_irq_nce;
	230	/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
	231	u32 host_to_vpu_irq;
	232	/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
	233	u32 job_done_irq;
	234	/* VPU -> ARM IRQ line to use to request MMU update. */
	235	u32 mmu_update_request_irq;
	236	/* ARM -> VPU IRQ line to use to notify of MMU update completion. */
	237	u32 mmu_update_done_irq;
	238	/* ARM -> VPU IRQ line to use to request power level change. */
	239	u32 set_power_level_irq;
	240	/* VPU -> ARM IRQ line to use to notify of power level change completion. */
	241	u32 set_power_level_done_irq;
	242	/* VPU -> ARM IRQ line to use to notify of VPU idle state change */
	243	u32 set_vpu_idle_update_irq;
	244	/* VPU -> ARM IRQ line to use to request counter reset. */
	245	u32 metric_query_event_irq;
	246	/* ARM -> VPU IRQ line to use to notify of counter reset completion. */
	247	u32 metric_query_event_done_irq;
	248	/* VPU -> ARM IRQ line to use to notify of preemption completion. */
	249	u32 preemption_done_irq;
	250	/* Padding. */
	251	u32 pad3[52];
	252	/* Silicon information: 0x300 - 0x3FF */
	253	u32 host_version_id;
	254	u32 si_stepping;
	255	u64 device_id;
	256	u64 feature_exclusion;
	257	u64 sku;
	258	/** PLL ratio for minimum clock frequency */
	259	u32 min_freq_pll_ratio;
	260	/** PLL ratio for maximum clock frequency */
261	u32 max_freq_pll_ratio;
262	/**
263	* Initial log level threshold (messages with log level severity less than
264	* the threshold will not be logged); applies to every enabled logging
265	* destination and loggable HW component. See 'mvLog_t' enum for acceptable
266	* values.
8c63b474	267	* TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
02d5b0aa JL	268	*/
	269	u32 default_trace_level;
	270	u32 boot_type;
	271	u64 punit_telemetry_sram_base;
	272	u64 punit_telemetry_sram_size;
	273	u32 vpu_telemetry_enable;
	274	u64 crit_tracing_buff_addr;
	275	u32 crit_tracing_buff_size;
	276	u64 verbose_tracing_buff_addr;
	277	u32 verbose_tracing_buff_size;
	278	u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
	279	/**
	280	* Mask of destinations to which logging messages are delivered; bitwise OR
	281	* of values defined in vpu_trace_destination enum.
	282	*/
	283	u32 trace_destination_mask;
	284	/**
	285	* Mask of hardware components for which logging is enabled; bitwise OR of
	286	* bits defined by the VPU_TRACE_PROC_BIT_* macros.
	287	*/
	288	u64 trace_hw_component_mask;
	289	/** Mask of trace message formats supported by the driver */
	290	u64 tracing_buff_message_format_mask;
	291	u64 trace_reserved_1[2];
	292	/**
	293	* Period at which the VPU reads the temp sensor values into MMIO, on
	294	* platforms where that is necessary (in ms). 0 to disable reads.
	295	*/
	296	u32 temp_sensor_period_ms;
	297	/** PLL ratio for efficient clock frequency */
	298	u32 pn_freq_pll_ratio;
8c63b474 KP	299	/** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */
	300	u32 dvfs_mode;
	301	/**
	302	* Depending on DVFS Mode:
	303	* On-demand: Default if 0.
	304	* Bit 0-7 - uint8_t: Highest residency percent
	305	* Bit 8-15 - uint8_t: High residency percent
	306	* Bit 16-23 - uint8_t: Low residency percent
	307	* Bit 24-31 - uint8_t: Lowest residency percent
	308	* Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
	309	* Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
	310	* Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
	311	* Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
	312	* Bit 48-55 - uint8_t: Period (ms) for residency decisions
	313	* Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
	314	* Power Save/Max Performance: Unused
	315	*/
	316	u64 dvfs_param;
	317	/**
	318	* D0i3 delayed entry
	319	* Bit0: Disable CPU state save on D0i2 entry flow.
	320	* 0: Every D0i2 entry saves state. Save state IPC message ignored.
	321	* 1: IPC message required to save state on D0i3 entry flow.
	322	*/
	323	u32 d0i3_delayed_entry;
	324	/* Time spent by VPU in D0i3 state */
	325	u64 d0i3_residency_time_us;
	326	/* Value of VPU perf counter at the time of entering D0i3 state . */
	327	u64 d0i3_entry_vpu_ts;
3bd0edf8 JL	328	/*
	329	* The system time of the host operating system in microseconds.
	330	* E.g the number of microseconds since 1st of January 1970, or whatever date the
	331	* host operating system uses to maintain system time.
	332	* This value will be used to track system time on the VPU.
	333	* The KMD is required to update this value on every VPU reset.
	334	*/
	335	u64 system_time_us;
	336	u32 pad4[18];
02d5b0aa JL	337	/* Warm boot information: 0x400 - 0x43F */
	338	u32 warm_boot_sections_count;
	339	u32 warm_boot_start_address_reference;
	340	u32 warm_boot_section_info_address_offset;
	341	u32 pad5[13];
	342	/* Power States transitions timestamps: 0x440 - 0x46F*/
	343	struct {
	344	/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
	345	u64 vpu_active_state_requested;
	346	/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
	347	u64 vpu_active_state_achieved;
	348	/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
	349	u64 vpu_idle_state_requested;
	350	/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
	351	u64 vpu_idle_state_achieved;
	352	/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
	353	u64 vpu_standby_state_requested;
	354	/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
	355	u64 vpu_standby_state_achieved;
	356	} power_states_timestamps;
	357	/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
	358	u32 vpu_scheduling_mode;
	359	/* Present call period in milliseconds. */
	360	u32 vpu_focus_present_timer_ms;
8c63b474 KP	361	/* VPU ECC Signaling */
8c63b474 KP	362	u32 vpu_uses_ecc_mca_signal;
3bd0edf8 JL	363	/* Values defined by POWER_PROFILE* macros */
	364	u32 power_profile;
	365	/* Microsecond value for DCT active cycle */
	366	u32 dct_active_us;
	367	/* Microsecond value for DCT inactive cycle */
	368	u32 dct_inactive_us;
	369	/* Unused/reserved: 0x488 - 0xFFF */
	370	u32 pad6[734];
02d5b0aa JL	371	};
	372
	373	/*
	374	* Magic numbers set between host and vpu to detect corruptio of tracing init
	375	*/
	376
	377	#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
	378
	379	/* Tracing buffer message format definitions */
	380	#define VPU_TRACING_FORMAT_STRING 0
	381	#define VPU_TRACING_FORMAT_MIPI 2
	382	/*
	383	* Header of the tracing buffer.
	384	* The below defined header will be stored at the beginning of
	385	* each allocated tracing buffer, followed by a series of 256b
	386	* of ASCII trace message entries.
	387	*/
	388	struct vpu_tracing_buffer_header {
	389	/**
	390	* Magic number set by host to detect corruption
	391	* @see VPU_TRACING_BUFFER_CANARY
	392	*/
	393	u32 host_canary_start;
	394	/* offset from start of buffer for trace entries */
	395	u32 read_index;
	396	u32 pad_to_cache_line_size_0[14];
	397	/* End of first cache line */
	398
	399	/**
	400	* Magic number set by host to detect corruption
	401	* @see VPU_TRACING_BUFFER_CANARY
	402	*/
	403	u32 vpu_canary_start;
	404	/* offset from start of buffer from write start */
	405	u32 write_index;
	406	/* counter for buffer wrapping */
	407	u32 wrap_count;
	408	/* legacy field - do not use */
	409	u32 reserved_0;
	410	/**
	411	* Size of the log buffer include this header (@header_size) and space
	412	* reserved for all messages. If @alignment` is greater that 0 the @Size
	413	* must be multiple of @Alignment.
	414	*/
	415	u32 size;
	416	/* Header version */
	417	u16 header_version;
	418	/* Header size */
	419	u16 header_size;
	420	/*
	421	* Format of the messages in the trace buffer
	422	* 0 - null terminated string
	423	* 1 - size + null terminated string
	424	* 2 - MIPI-SysT encoding
	425	*/
	426	u32 format;
	427	/*
	428	* Message alignment
	429	* 0 - messages are place 1 after another
	430	* n - every message starts and multiple on offset
	431	*/
	432	u32 alignment; /* 64, 128, 256 */
	433	/* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
	434	char name[16];
435	u32 pad_to_cache_line_size_1[4];
436	/* End of second cache line */
437	};
438
439	#pragma pack(pop)
440
441	#endif