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02d5b0aa JL |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* | |
990b1e3d | 3 | * Copyright (C) 2020-2024 Intel Corporation |
02d5b0aa JL |
4 | */ |
5 | ||
6 | #ifndef __IVPU_FW_H__ | |
7 | #define __IVPU_FW_H__ | |
8 | ||
436b67d6 JL |
9 | #include "vpu_jsm_api.h" |
10 | ||
990b1e3d JL |
11 | #define FW_VERSION_HEADER_SIZE SZ_4K |
12 | #define FW_VERSION_STR_SIZE SZ_256 | |
13 | ||
02d5b0aa JL |
14 | struct ivpu_device; |
15 | struct ivpu_bo; | |
16 | struct vpu_boot_params; | |
17 | ||
18 | struct ivpu_fw_info { | |
19 | const struct firmware *file; | |
f9d918cf | 20 | const char *name; |
990b1e3d | 21 | char version[FW_VERSION_STR_SIZE]; |
02d5b0aa JL |
22 | struct ivpu_bo *mem; |
23 | struct ivpu_bo *mem_shave_nn; | |
24 | struct ivpu_bo *mem_log_crit; | |
25 | struct ivpu_bo *mem_log_verb; | |
26 | u64 runtime_addr; | |
27 | u32 runtime_size; | |
28 | u64 image_load_offset; | |
29 | u32 image_size; | |
30 | u32 shave_nn_size; | |
31 | u64 entry_point; /* Cold or warm boot entry point for next boot */ | |
32 | u64 cold_boot_entry_point; | |
d4e4257a SG |
33 | u32 trace_level; |
34 | u32 trace_destination_mask; | |
35 | u64 trace_hw_component_mask; | |
f13108fc | 36 | u32 dvfs_mode; |
eb756b4c WK |
37 | u32 primary_preempt_buf_size; |
38 | u32 secondary_preempt_buf_size; | |
72b96ec6 WK |
39 | u64 read_only_addr; |
40 | u32 read_only_size; | |
436b67d6 | 41 | u32 sched_mode; |
0e7db503 | 42 | u64 last_heartbeat; |
02d5b0aa JL |
43 | }; |
44 | ||
45 | int ivpu_fw_init(struct ivpu_device *vdev); | |
46 | void ivpu_fw_fini(struct ivpu_device *vdev); | |
53d98420 | 47 | void ivpu_fw_load(struct ivpu_device *vdev); |
02d5b0aa JL |
48 | void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *bp); |
49 | ||
50 | static inline bool ivpu_fw_is_cold_boot(struct ivpu_device *vdev) | |
51 | { | |
52 | return vdev->fw->entry_point == vdev->fw->cold_boot_entry_point; | |
53 | } | |
54 | ||
55 | #endif /* __IVPU_FW_H__ */ |