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35b13763 JL |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* | |
e3caadf1 | 3 | * Copyright (C) 2020-2024 Intel Corporation |
35b13763 JL |
4 | */ |
5 | ||
6 | #ifndef __IVPU_DRV_H__ | |
7 | #define __IVPU_DRV_H__ | |
8 | ||
9 | #include <drm/drm_device.h> | |
4522ad76 | 10 | #include <drm/drm_drv.h> |
35b13763 JL |
11 | #include <drm/drm_managed.h> |
12 | #include <drm/drm_mm.h> | |
13 | #include <drm/drm_print.h> | |
14 | ||
15 | #include <linux/pci.h> | |
16 | #include <linux/xarray.h> | |
17 | #include <uapi/drm/ivpu_accel.h> | |
18 | ||
263b2ba5 | 19 | #include "ivpu_mmu_context.h" |
3b434a34 | 20 | #include "ivpu_ipc.h" |
263b2ba5 | 21 | |
35b13763 | 22 | #define DRIVER_NAME "intel_vpu" |
2fc1a50f | 23 | #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" |
35b13763 JL |
24 | #define DRIVER_DATE "20230117" |
25 | ||
26 | #define PCI_DEVICE_ID_MTL 0x7d1d | |
9c1b2429 | 27 | #define PCI_DEVICE_ID_ARL 0xad1d |
79cdc56c | 28 | #define PCI_DEVICE_ID_LNL 0x643e |
35b13763 | 29 | |
51d66a7b | 30 | #define IVPU_HW_37XX 37 |
79cdc56c | 31 | #define IVPU_HW_40XX 40 |
51d66a7b | 32 | |
34d03f2a KW |
33 | #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 |
34 | /* SSID 1 is used by the VPU to represent reserved context */ | |
35 | #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 | |
36 | #define IVPU_USER_CONTEXT_MIN_SSID 2 | |
37 | #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) | |
3ff6edbc | 38 | |
f32d5967 WK |
39 | #define IVPU_MIN_DB 1 |
40 | #define IVPU_MAX_DB 255 | |
41 | ||
34d03f2a | 42 | #define IVPU_NUM_ENGINES 2 |
35b13763 JL |
43 | |
44 | #define IVPU_PLATFORM_SILICON 0 | |
45 | #define IVPU_PLATFORM_SIMICS 2 | |
46 | #define IVPU_PLATFORM_FPGA 3 | |
47 | #define IVPU_PLATFORM_INVALID 8 | |
48 | ||
49 | #define IVPU_DBG_REG BIT(0) | |
50 | #define IVPU_DBG_IRQ BIT(1) | |
51 | #define IVPU_DBG_MMU BIT(2) | |
52 | #define IVPU_DBG_FILE BIT(3) | |
53 | #define IVPU_DBG_MISC BIT(4) | |
54 | #define IVPU_DBG_FW_BOOT BIT(5) | |
55 | #define IVPU_DBG_PM BIT(6) | |
56 | #define IVPU_DBG_IPC BIT(7) | |
57 | #define IVPU_DBG_BO BIT(8) | |
58 | #define IVPU_DBG_JOB BIT(9) | |
59 | #define IVPU_DBG_JSM BIT(10) | |
60 | #define IVPU_DBG_KREF BIT(11) | |
61 | #define IVPU_DBG_RPM BIT(12) | |
8047d36f | 62 | #define IVPU_DBG_MMU_MAP BIT(13) |
35b13763 JL |
63 | |
64 | #define ivpu_err(vdev, fmt, ...) \ | |
65 | drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) | |
66 | ||
67 | #define ivpu_err_ratelimited(vdev, fmt, ...) \ | |
68 | drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) | |
69 | ||
70 | #define ivpu_warn(vdev, fmt, ...) \ | |
71 | drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) | |
72 | ||
73 | #define ivpu_warn_ratelimited(vdev, fmt, ...) \ | |
74 | drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) | |
75 | ||
76 | #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) | |
77 | ||
78 | #define ivpu_dbg(vdev, type, fmt, args...) do { \ | |
79 | if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ | |
80 | dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ | |
81 | } while (0) | |
82 | ||
83 | #define IVPU_WA(wa_name) (vdev->wa.wa_name) | |
84 | ||
eefa13a6 SG |
85 | #define IVPU_PRINT_WA(wa_name) do { \ |
86 | if (IVPU_WA(wa_name)) \ | |
87 | ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ | |
88 | } while (0) | |
89 | ||
35b13763 JL |
90 | struct ivpu_wa_table { |
91 | bool punit_disabled; | |
92 | bool clear_runtime_mem; | |
7f34e01f | 93 | bool interrupt_clear_with_0; |
79cdc56c | 94 | bool disable_clock_relinquish; |
3198a62e | 95 | bool disable_d0i3_msg; |
35b13763 JL |
96 | }; |
97 | ||
98 | struct ivpu_hw_info; | |
263b2ba5 | 99 | struct ivpu_mmu_info; |
02d5b0aa | 100 | struct ivpu_fw_info; |
5d7422cf | 101 | struct ivpu_ipc_info; |
852be13f | 102 | struct ivpu_pm_info; |
35b13763 JL |
103 | |
104 | struct ivpu_device { | |
105 | struct drm_device drm; | |
106 | void __iomem *regb; | |
107 | void __iomem *regv; | |
108 | u32 platform; | |
109 | u32 irq; | |
110 | ||
111 | struct ivpu_wa_table wa; | |
112 | struct ivpu_hw_info *hw; | |
263b2ba5 | 113 | struct ivpu_mmu_info *mmu; |
02d5b0aa | 114 | struct ivpu_fw_info *fw; |
5d7422cf | 115 | struct ivpu_ipc_info *ipc; |
852be13f | 116 | struct ivpu_pm_info *pm; |
35b13763 | 117 | |
263b2ba5 | 118 | struct ivpu_mmu_context gctx; |
34d03f2a | 119 | struct ivpu_mmu_context rctx; |
f1cc6ace | 120 | struct mutex context_list_lock; /* Protects user context addition/removal */ |
35b13763 JL |
121 | struct xarray context_xa; |
122 | struct xa_limit context_xa_limit; | |
123 | ||
f32d5967 WK |
124 | struct xarray db_xa; |
125 | ||
48aea7f2 JL |
126 | struct mutex bo_list_lock; /* Protects bo_list */ |
127 | struct list_head bo_list; | |
128 | ||
cd727221 | 129 | struct xarray submitted_jobs_xa; |
3b434a34 | 130 | struct ivpu_ipc_consumer job_done_consumer; |
cd727221 | 131 | |
02d5b0aa JL |
132 | atomic64_t unique_id_counter; |
133 | ||
35b13763 JL |
134 | struct { |
135 | int boot; | |
136 | int jsm; | |
137 | int tdr; | |
138 | int reschedule_suspend; | |
8ed520ff | 139 | int autosuspend; |
3198a62e | 140 | int d0i3_entry_msg; |
35b13763 JL |
141 | } timeout; |
142 | }; | |
143 | ||
144 | /* | |
145 | * file_priv has its own refcount (ref) that allows user space to close the fd | |
146 | * without blocking even if VPU is still processing some jobs. | |
147 | */ | |
148 | struct ivpu_file_priv { | |
149 | struct kref ref; | |
150 | struct ivpu_device *vdev; | |
cd727221 JL |
151 | struct mutex lock; /* Protects cmdq */ |
152 | struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; | |
263b2ba5 | 153 | struct ivpu_mmu_context ctx; |
263b2ba5 | 154 | bool has_mmu_faults; |
f1cc6ace | 155 | bool bound; |
35b13763 JL |
156 | }; |
157 | ||
158 | extern int ivpu_dbg_mask; | |
159 | extern u8 ivpu_pll_min_ratio; | |
160 | extern u8 ivpu_pll_max_ratio; | |
95d44018 | 161 | extern bool ivpu_disable_mmu_cont_pages; |
35b13763 | 162 | |
3198a62e AK |
163 | #define IVPU_TEST_MODE_FW_TEST BIT(0) |
164 | #define IVPU_TEST_MODE_NULL_HW BIT(1) | |
165 | #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) | |
166 | #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) | |
167 | #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) | |
02d5b0aa JL |
168 | extern int ivpu_test_mode; |
169 | ||
35b13763 JL |
170 | struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); |
171 | void ivpu_file_priv_put(struct ivpu_file_priv **link); | |
02d5b0aa JL |
172 | |
173 | int ivpu_boot(struct ivpu_device *vdev); | |
35b13763 | 174 | int ivpu_shutdown(struct ivpu_device *vdev); |
828d6304 | 175 | void ivpu_prepare_for_reset(struct ivpu_device *vdev); |
35b13763 | 176 | |
35b13763 JL |
177 | static inline u8 ivpu_revision(struct ivpu_device *vdev) |
178 | { | |
179 | return to_pci_dev(vdev->drm.dev)->revision; | |
180 | } | |
181 | ||
182 | static inline u16 ivpu_device_id(struct ivpu_device *vdev) | |
183 | { | |
184 | return to_pci_dev(vdev->drm.dev)->device; | |
185 | } | |
186 | ||
51d66a7b JL |
187 | static inline int ivpu_hw_gen(struct ivpu_device *vdev) |
188 | { | |
189 | switch (ivpu_device_id(vdev)) { | |
190 | case PCI_DEVICE_ID_MTL: | |
9c1b2429 | 191 | case PCI_DEVICE_ID_ARL: |
51d66a7b | 192 | return IVPU_HW_37XX; |
79cdc56c SG |
193 | case PCI_DEVICE_ID_LNL: |
194 | return IVPU_HW_40XX; | |
51d66a7b | 195 | default: |
b7f9b9b6 | 196 | ivpu_err(vdev, "Unknown NPU device\n"); |
51d66a7b JL |
197 | return 0; |
198 | } | |
199 | } | |
200 | ||
35b13763 JL |
201 | static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) |
202 | { | |
203 | return container_of(dev, struct ivpu_device, drm); | |
204 | } | |
205 | ||
206 | static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) | |
207 | { | |
208 | struct xa_limit ctx_limit = vdev->context_xa_limit; | |
209 | ||
210 | return (ctx_limit.max - ctx_limit.min + 1); | |
211 | } | |
212 | ||
213 | static inline u32 ivpu_get_platform(struct ivpu_device *vdev) | |
214 | { | |
215 | WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); | |
216 | return vdev->platform; | |
217 | } | |
218 | ||
219 | static inline bool ivpu_is_silicon(struct ivpu_device *vdev) | |
220 | { | |
221 | return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; | |
222 | } | |
223 | ||
224 | static inline bool ivpu_is_simics(struct ivpu_device *vdev) | |
225 | { | |
226 | return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; | |
227 | } | |
228 | ||
229 | static inline bool ivpu_is_fpga(struct ivpu_device *vdev) | |
230 | { | |
231 | return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; | |
232 | } | |
233 | ||
234 | #endif /* __IVPU_DRV_H__ */ |