projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 0d456bad MF |
1 | /* |
| 2 | * arch/xtensa/platform/xtavnet/include/platform/hardware.h | |
| 3 | * | |
| 4 | * This file is subject to the terms and conditions of the GNU General Public | |
| 5 | * License. See the file "COPYING" in the main directory of this archive | |
| 6 | * for more details. | |
| 7 | * | |
| 8 | * Copyright (C) 2006 Tensilica Inc. | |
| 9 | */ | |
| 10 | ||
| 11 | /* | |
| 12 | * This file contains the hardware configuration of the XTAVNET boards. | |
| 13 | */ | |
| 14 | ||
| b85d4594 MF |
15 | #include <asm/types.h> |
| 16 | ||
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17 | #ifndef __XTENSA_XTAVNET_HARDWARE_H |
| 18 | #define __XTENSA_XTAVNET_HARDWARE_H | |
| 19 | ||
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20 | /* Memory configuration. */ |
| 21 | ||
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22 | #define PLATFORM_DEFAULT_MEM_START __XTENSA_UL(CONFIG_DEFAULT_MEM_START) |
| 23 | #define PLATFORM_DEFAULT_MEM_SIZE __XTENSA_UL(CONFIG_DEFAULT_MEM_SIZE) | |
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24 | |
| 25 | /* Interrupt configuration. */ | |
| 26 | ||
| 27 | #define PLATFORM_NR_IRQS 10 | |
| 28 | ||
| 29 | /* Default assignment of LX60 devices to external interrupts. */ | |
| 30 | ||
| f615136c | 31 | #ifdef CONFIG_XTENSA_MX |
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32 | #define DUART16552_INTNUM XCHAL_EXTINT3_NUM |
| 33 | #define OETH_IRQ XCHAL_EXTINT4_NUM | |
| 34 | #else | |
| 35 | #define DUART16552_INTNUM XCHAL_EXTINT0_NUM | |
| 36 | #define OETH_IRQ XCHAL_EXTINT1_NUM | |
| 37 | #endif | |
| 38 | ||
| 39 | /* | |
| 40 | * Device addresses and parameters. | |
| 41 | */ | |
| 42 | ||
| 43 | /* UART */ | |
| 44 | #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020) | |
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45 | |
| 46 | /* Misc. */ | |
| 47 | #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000) | |
| 48 | /* Clock frequency in Hz (read-only): */ | |
| 49 | #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) | |
| 50 | /* Setting of 8 DIP switches: */ | |
| 51 | #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C) | |
| 52 | /* Software reset (write 0xdead): */ | |
| 53 | #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10) | |
| 54 | ||
| 55 | /* OpenCores Ethernet controller: */ | |
| 56 | /* regs + RX/TX descriptors */ | |
| 57 | #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000) | |
| 58 | #define OETH_REGS_SIZE 0x1000 | |
| 59 | #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000) | |
| 60 | ||
| 61 | /* 5*rx buffs + 5*tx buffs */ | |
| 62 | #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600) | |
| 63 | ||
| e0bf6c5c MF |
64 | #define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000) |
| 65 | #define C67X00_SIZE 0x10 | |
| 66 | #define C67X00_IRQ 5 | |
| 0d456bad | 67 | #endif /* __XTENSA_XTAVNET_HARDWARE_H */ |