[linux-block.git] / arch / xtensa / mm / cache.c

/*
 * arch/xtensa/mm/cache.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001-2006 Tensilica Inc.
 *
 * Chris Zankel	<chris@zankel.net>
 * Joe Taylor
 * Marc Gauthier
 *
 */

#include <linux/init.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/memblock.h>
#include <linux/swap.h>
#include <linux/pagemap.h>
#include <linux/pgtable.h>

#include <asm/bootparam.h>
#include <asm/mmu_context.h>
#include <asm/tlb.h>
#include <asm/tlbflush.h>
#include <asm/page.h>

/* 
 * Note:
 * The kernel provides one architecture bit PG_arch_1 in the page flags that 
 * can be used for cache coherency.
 *
 * I$-D$ coherency.
 *
 * The Xtensa architecture doesn't keep the instruction cache coherent with
 * the data cache. We use the architecture bit to indicate if the caches
 * are coherent. The kernel clears this bit whenever a page is added to the
 * page cache. At that time, the caches might not be in sync. We, therefore,
 * define this flag as 'clean' if set.
 *
 * D-cache aliasing.
 *
 * With cache aliasing, we have to always flush the cache when pages are
 * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
 * page.
 * 
 *
 *
 */

#if (DCACHE_WAY_SIZE > PAGE_SIZE)
static inline void kmap_invalidate_coherent(struct page *page,
					    unsigned long vaddr)
{
	if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
		unsigned long kvaddr;

		if (!PageHighMem(page)) {
			kvaddr = (unsigned long)page_to_virt(page);

			__invalidate_dcache_page(kvaddr);
		} else {
			kvaddr = TLBTEMP_BASE_1 +
				(page_to_phys(page) & DCACHE_ALIAS_MASK);

			preempt_disable();
			__invalidate_dcache_page_alias(kvaddr,
						       page_to_phys(page));
			preempt_enable();
		}
	}
}

static inline void *coherent_kvaddr(struct page *page, unsigned long base,
				    unsigned long vaddr, unsigned long *paddr)
{
	*paddr = page_to_phys(page);
	return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
}

void clear_user_highpage(struct page *page, unsigned long vaddr)
{
	struct folio *folio = page_folio(page);
	unsigned long paddr;
	void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);

	preempt_disable();
	kmap_invalidate_coherent(page, vaddr);
	set_bit(PG_arch_1, folio_flags(folio, 0));
	clear_page_alias(kvaddr, paddr);
	preempt_enable();
}
EXPORT_SYMBOL(clear_user_highpage);

void copy_user_highpage(struct page *dst, struct page *src,
			unsigned long vaddr, struct vm_area_struct *vma)
{
	struct folio *folio = page_folio(dst);
	unsigned long dst_paddr, src_paddr;
	void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
					  &dst_paddr);
	void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
					  &src_paddr);

	preempt_disable();
	kmap_invalidate_coherent(dst, vaddr);
	set_bit(PG_arch_1, folio_flags(folio, 0));
	copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
	preempt_enable();
}
EXPORT_SYMBOL(copy_user_highpage);

/*
 * Any time the kernel writes to a user page cache page, or it is about to
 * read from a page cache page this routine is called.
 *
 */

void flush_dcache_folio(struct folio *folio)
{
	struct address_space *mapping = folio_flush_mapping(folio);

	/*
	 * If we have a mapping but the page is not mapped to user-space
	 * yet, we simply mark this page dirty and defer flushing the 
	 * caches until update_mmu().
	 */

	if (mapping && !mapping_mapped(mapping)) {
		if (!test_bit(PG_arch_1, &folio->flags))
			set_bit(PG_arch_1, &folio->flags);
		return;

	} else {
		unsigned long phys = folio_pfn(folio) * PAGE_SIZE;
		unsigned long temp = folio_pos(folio);
		unsigned int i, nr = folio_nr_pages(folio);
		unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
		unsigned long virt;

		/* 
		 * Flush the page in kernel space and user space.
		 * Note that we can omit that step if aliasing is not
		 * an issue, but we do have to synchronize I$ and D$
		 * if we have a mapping.
		 */

		if (!alias && !mapping)
			return;

		preempt_disable();
		for (i = 0; i < nr; i++) {
			virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
			__flush_invalidate_dcache_page_alias(virt, phys);

			virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);

			if (alias)
				__flush_invalidate_dcache_page_alias(virt, phys);

			if (mapping)
				__invalidate_icache_page_alias(virt, phys);
			phys += PAGE_SIZE;
			temp += PAGE_SIZE;
		}
		preempt_enable();
	}

	/* There shouldn't be an entry in the cache for this page anymore. */
}
EXPORT_SYMBOL(flush_dcache_folio);

/*
 * For now, flush the whole cache. FIXME??
 */

void local_flush_cache_range(struct vm_area_struct *vma,
		       unsigned long start, unsigned long end)
{
	__flush_invalidate_dcache_all();
	__invalidate_icache_all();
}
EXPORT_SYMBOL(local_flush_cache_range);

/* 
 * Remove any entry in the cache for this page. 
 *
 * Note that this function is only called for user pages, so use the
 * alias versions of the cache flush functions.
 */

void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
		      unsigned long pfn)
{
	/* Note that we have to use the 'alias' address to avoid multi-hit */

	unsigned long phys = page_to_phys(pfn_to_page(pfn));
	unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);

	preempt_disable();
	__flush_invalidate_dcache_page_alias(virt, phys);
	__invalidate_icache_page_alias(virt, phys);
	preempt_enable();
}
EXPORT_SYMBOL(local_flush_cache_page);

#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */

void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
		unsigned long addr, pte_t *ptep, unsigned int nr)
{
	unsigned long pfn = pte_pfn(*ptep);
	struct folio *folio;
	unsigned int i;

	if (!pfn_valid(pfn))
		return;

	folio = page_folio(pfn_to_page(pfn));

	/* Invalidate old entries in TLBs */
	for (i = 0; i < nr; i++)
		flush_tlb_page(vma, addr + i * PAGE_SIZE);
	nr = folio_nr_pages(folio);

#if (DCACHE_WAY_SIZE > PAGE_SIZE)

	if (!folio_test_reserved(folio) && test_bit(PG_arch_1, &folio->flags)) {
		unsigned long phys = folio_pfn(folio) * PAGE_SIZE;
		unsigned long tmp;

		preempt_disable();
		for (i = 0; i < nr; i++) {
			tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
			__flush_invalidate_dcache_page_alias(tmp, phys);
			tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
			__flush_invalidate_dcache_page_alias(tmp, phys);
			__invalidate_icache_page_alias(tmp, phys);
			phys += PAGE_SIZE;
		}
		preempt_enable();

		clear_bit(PG_arch_1, &folio->flags);
	}
#else
	if (!folio_test_reserved(folio) && !test_bit(PG_arch_1, &folio->flags)
	    && (vma->vm_flags & VM_EXEC) != 0) {
		for (i = 0; i < nr; i++) {
			void *paddr = kmap_local_folio(folio, i * PAGE_SIZE);
			__flush_dcache_page((unsigned long)paddr);
			__invalidate_icache_page((unsigned long)paddr);
			kunmap_local(paddr);
		}
		set_bit(PG_arch_1, &folio->flags);
	}
#endif
}

/*
 * access_process_vm() has called get_user_pages(), which has done a
 * flush_dcache_page() on the page.
 */

#if (DCACHE_WAY_SIZE > PAGE_SIZE)

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		unsigned long vaddr, void *dst, const void *src,
		unsigned long len)
{
	unsigned long phys = page_to_phys(page);
	unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));

	/* Flush and invalidate user page if aliased. */

	if (alias) {
		unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
		preempt_disable();
		__flush_invalidate_dcache_page_alias(t, phys);
		preempt_enable();
	}

	/* Copy data */
	
	memcpy(dst, src, len);

	/*
	 * Flush and invalidate kernel page if aliased and synchronize 
	 * data and instruction caches for executable pages. 
	 */

	if (alias) {
		unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);

		preempt_disable();
		__flush_invalidate_dcache_range((unsigned long) dst, len);
		if ((vma->vm_flags & VM_EXEC) != 0)
			__invalidate_icache_page_alias(t, phys);
		preempt_enable();

	} else if ((vma->vm_flags & VM_EXEC) != 0) {
		__flush_dcache_range((unsigned long)dst,len);
		__invalidate_icache_range((unsigned long) dst, len);
	}
}

extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
		unsigned long vaddr, void *dst, const void *src,
		unsigned long len)
{
	unsigned long phys = page_to_phys(page);
	unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));

	/*
	 * Flush user page if aliased. 
	 * (Note: a simply flush would be sufficient) 
	 */

	if (alias) {
		unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
		preempt_disable();
		__flush_invalidate_dcache_page_alias(t, phys);
		preempt_enable();
	}

	memcpy(dst, src, len);
}

#endif
Commit	Line	Data
6656920b CZ	1	/*
	2	* arch/xtensa/mm/cache.c
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2001-2006 Tensilica Inc.
	9	*
	10	* Chris Zankel <chris@zankel.net>
	11	* Joe Taylor
	12	* Marc Gauthier
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/signal.h>
	18	#include <linux/sched.h>
	19	#include <linux/kernel.h>
	20	#include <linux/errno.h>
	21	#include <linux/string.h>
	22	#include <linux/types.h>
	23	#include <linux/ptrace.h>
57c8a661	24	#include <linux/memblock.h>
6656920b CZ	25	#include <linux/swap.h>
6656920b CZ	26	#include <linux/pagemap.h>
65fddcfc	27	#include <linux/pgtable.h>
6656920b	28
6656920b CZ	29	#include <asm/bootparam.h>
	30	#include <asm/mmu_context.h>
	31	#include <asm/tlb.h>
	32	#include <asm/tlbflush.h>
	33	#include <asm/page.h>
6656920b	34
6656920b CZ	35	/*
	36	* Note:
	37	* The kernel provides one architecture bit PG_arch_1 in the page flags that
	38	* can be used for cache coherency.
	39	*
	40	* I$-D$ coherency.
	41	*
	42	* The Xtensa architecture doesn't keep the instruction cache coherent with
	43	* the data cache. We use the architecture bit to indicate if the caches
	44	* are coherent. The kernel clears this bit whenever a page is added to the
	45	* page cache. At that time, the caches might not be in sync. We, therefore,
	46	* define this flag as 'clean' if set.
	47	*
	48	* D-cache aliasing.
	49	*
	50	* With cache aliasing, we have to always flush the cache when pages are
	51	* unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
	52	* page.
	53	*
	54	*
	55	*
	56	*/
	57
a91902db MF	58	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
	59	static inline void kmap_invalidate_coherent(struct page *page,
	60	unsigned long vaddr)
	61	{
	62	if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
	63	unsigned long kvaddr;
	64
	65	if (!PageHighMem(page)) {
	66	kvaddr = (unsigned long)page_to_virt(page);
	67
	68	__invalidate_dcache_page(kvaddr);
	69	} else {
	70	kvaddr = TLBTEMP_BASE_1 +
	71	(page_to_phys(page) & DCACHE_ALIAS_MASK);
	72
3a860d16	73	preempt_disable();
a91902db MF	74	__invalidate_dcache_page_alias(kvaddr,
a91902db MF	75	page_to_phys(page));
3a860d16	76	preempt_enable();
a91902db MF	77	}
	78	}
	79	}
	80
	81	static inline void coherent_kvaddr(struct page page, unsigned long base,
	82	unsigned long vaddr, unsigned long *paddr)
	83	{
4f22ca7e MF	84	*paddr = page_to_phys(page);
4f22ca7e MF	85	return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
a91902db MF	86	}
	87
	88	void clear_user_highpage(struct page *page, unsigned long vaddr)
	89	{
fa92722e	90	struct folio *folio = page_folio(page);
a91902db MF	91	unsigned long paddr;
	92	void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
	93
a67cc9aa	94	preempt_disable();
a91902db	95	kmap_invalidate_coherent(page, vaddr);
fa92722e	96	set_bit(PG_arch_1, folio_flags(folio, 0));
a91902db	97	clear_page_alias(kvaddr, paddr);
a67cc9aa	98	preempt_enable();
a91902db	99	}
bc652eb6	100	EXPORT_SYMBOL(clear_user_highpage);
a91902db MF	101
	102	void copy_user_highpage(struct page dst, struct page src,
	103	unsigned long vaddr, struct vm_area_struct *vma)
	104	{
fa92722e	105	struct folio *folio = page_folio(dst);
a91902db MF	106	unsigned long dst_paddr, src_paddr;
	107	void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
	108	&dst_paddr);
	109	void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
	110	&src_paddr);
	111
a67cc9aa	112	preempt_disable();
a91902db	113	kmap_invalidate_coherent(dst, vaddr);
fa92722e	114	set_bit(PG_arch_1, folio_flags(folio, 0));
a91902db	115	copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
a67cc9aa	116	preempt_enable();
a91902db	117	}
bc652eb6	118	EXPORT_SYMBOL(copy_user_highpage);
a91902db	119
6656920b CZ	120	/*
	121	* Any time the kernel writes to a user page cache page, or it is about to
	122	* read from a page cache page this routine is called.
	123	*
	124	*/
	125
4fbb7e7f	126	void flush_dcache_folio(struct folio *folio)
6656920b	127	{
4fbb7e7f	128	struct address_space *mapping = folio_flush_mapping(folio);
6656920b CZ	129
	130	/*
	131	* If we have a mapping but the page is not mapped to user-space
	132	* yet, we simply mark this page dirty and defer flushing the
	133	* caches until update_mmu().
	134	*/
	135
	136	if (mapping && !mapping_mapped(mapping)) {
4fbb7e7f MWO	137	if (!test_bit(PG_arch_1, &folio->flags))
4fbb7e7f MWO	138	set_bit(PG_arch_1, &folio->flags);
6656920b CZ	139	return;
	140
	141	} else {
4fbb7e7f MWO	142	unsigned long phys = folio_pfn(folio) * PAGE_SIZE;
	143	unsigned long temp = folio_pos(folio);
	144	unsigned int i, nr = folio_nr_pages(folio);
6656920b CZ	145	unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
	146	unsigned long virt;
	147
	148	/*
	149	* Flush the page in kernel space and user space.
	150	* Note that we can omit that step if aliasing is not
	151	* an issue, but we do have to synchronize I$ and D$
	152	* if we have a mapping.
	153	*/
	154
	155	if (!alias && !mapping)
	156	return;
	157
3a860d16	158	preempt_disable();
4fbb7e7f MWO	159	for (i = 0; i < nr; i++) {
	160	virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
	161	__flush_invalidate_dcache_page_alias(virt, phys);
6656920b	162
4fbb7e7f	163	virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
6656920b	164
4fbb7e7f MWO	165	if (alias)
4fbb7e7f MWO	166	__flush_invalidate_dcache_page_alias(virt, phys);
6656920b	167
4fbb7e7f MWO	168	if (mapping)
	169	__invalidate_icache_page_alias(virt, phys);
	170	phys += PAGE_SIZE;
	171	temp += PAGE_SIZE;
	172	}
3a860d16	173	preempt_enable();
6656920b CZ	174	}
	175
	176	/* There shouldn't be an entry in the cache for this page anymore. */
	177	}
4fbb7e7f	178	EXPORT_SYMBOL(flush_dcache_folio);
6656920b CZ	179
	180	/*
	181	* For now, flush the whole cache. FIXME??
	182	*/
	183
f615136c	184	void local_flush_cache_range(struct vm_area_struct *vma,
6656920b CZ	185	unsigned long start, unsigned long end)
	186	{
	187	__flush_invalidate_dcache_all();
	188	__invalidate_icache_all();
	189	}
bc652eb6	190	EXPORT_SYMBOL(local_flush_cache_range);
6656920b CZ	191
	192	/*
	193	* Remove any entry in the cache for this page.
	194	*
	195	* Note that this function is only called for user pages, so use the
	196	* alias versions of the cache flush functions.
	197	*/
	198
f615136c	199	void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
c4c4594b	200	unsigned long pfn)
6656920b CZ	201	{
	202	/* Note that we have to use the 'alias' address to avoid multi-hit */
	203
	204	unsigned long phys = page_to_phys(pfn_to_page(pfn));
	205	unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
	206
3a860d16	207	preempt_disable();
6656920b CZ	208	__flush_invalidate_dcache_page_alias(virt, phys);
6656920b CZ	209	__invalidate_icache_page_alias(virt, phys);
3a860d16	210	preempt_enable();
6656920b	211	}
bc652eb6	212	EXPORT_SYMBOL(local_flush_cache_page);
6656920b	213
6d0f581d	214	#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
6656920b	215
4fbb7e7f MWO	216	void update_mmu_cache_range(struct vm_fault vmf, struct vm_area_struct vma,
4fbb7e7f MWO	217	unsigned long addr, pte_t *ptep, unsigned int nr)
6656920b	218	{
4b3073e1	219	unsigned long pfn = pte_pfn(*ptep);
4fbb7e7f MWO	220	struct folio *folio;
4fbb7e7f MWO	221	unsigned int i;
6656920b CZ	222
	223	if (!pfn_valid(pfn))
	224	return;
	225
4fbb7e7f	226	folio = page_folio(pfn_to_page(pfn));
6656920b	227
4fbb7e7f MWO	228	/* Invalidate old entries in TLBs */
	229	for (i = 0; i < nr; i++)
	230	flush_tlb_page(vma, addr + i * PAGE_SIZE);
	231	nr = folio_nr_pages(folio);
6656920b	232
6d0f581d	233	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
6656920b	234
4fbb7e7f MWO	235	if (!folio_test_reserved(folio) && test_bit(PG_arch_1, &folio->flags)) {
4fbb7e7f MWO	236	unsigned long phys = folio_pfn(folio) * PAGE_SIZE;
270eec76	237	unsigned long tmp;
6656920b	238
3a860d16	239	preempt_disable();
4fbb7e7f MWO	240	for (i = 0; i < nr; i++) {
	241	tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
	242	__flush_invalidate_dcache_page_alias(tmp, phys);
	243	tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
	244	__flush_invalidate_dcache_page_alias(tmp, phys);
	245	__invalidate_icache_page_alias(tmp, phys);
	246	phys += PAGE_SIZE;
	247	}
3a860d16	248	preempt_enable();
6656920b	249
4fbb7e7f	250	clear_bit(PG_arch_1, &folio->flags);
6656920b CZ	251	}
6656920b CZ	252	#else
4fbb7e7f	253	if (!folio_test_reserved(folio) && !test_bit(PG_arch_1, &folio->flags)
6656920b	254	&& (vma->vm_flags & VM_EXEC) != 0) {
4fbb7e7f MWO	255	for (i = 0; i < nr; i++) {
	256	void paddr = kmap_local_folio(folio, i PAGE_SIZE);
	257	__flush_dcache_page((unsigned long)paddr);
	258	__invalidate_icache_page((unsigned long)paddr);
	259	kunmap_local(paddr);
	260	}
	261	set_bit(PG_arch_1, &folio->flags);
6656920b CZ	262	}
	263	#endif
	264	}
	265
	266	/*
	267	* access_process_vm() has called get_user_pages(), which has done a
	268	* flush_dcache_page() on the page.
	269	*/
	270
6d0f581d	271	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
6656920b	272
c4c4594b	273	void copy_to_user_page(struct vm_area_struct vma, struct page page,
6656920b CZ	274	unsigned long vaddr, void dst, const void src,
	275	unsigned long len)
	276	{
	277	unsigned long phys = page_to_phys(page);
	278	unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
	279
	280	/* Flush and invalidate user page if aliased. */
	281
	282	if (alias) {
c4c4594b	283	unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
3a860d16	284	preempt_disable();
c4c4594b	285	__flush_invalidate_dcache_page_alias(t, phys);
3a860d16	286	preempt_enable();
6656920b CZ	287	}
	288
	289	/* Copy data */
	290
	291	memcpy(dst, src, len);
	292
	293	/*
	294	* Flush and invalidate kernel page if aliased and synchronize
	295	* data and instruction caches for executable pages.
	296	*/
	297
	298	if (alias) {
c4c4594b	299	unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
6656920b	300
3a860d16	301	preempt_disable();
6656920b	302	__flush_invalidate_dcache_range((unsigned long) dst, len);
c4c4594b CZ	303	if ((vma->vm_flags & VM_EXEC) != 0)
c4c4594b CZ	304	__invalidate_icache_page_alias(t, phys);
3a860d16	305	preempt_enable();
6656920b CZ	306
	307	} else if ((vma->vm_flags & VM_EXEC) != 0) {
	308	__flush_dcache_range((unsigned long)dst,len);
	309	__invalidate_icache_range((unsigned long) dst, len);
	310	}
	311	}
	312
	313	extern void copy_from_user_page(struct vm_area_struct vma, struct page page,
	314	unsigned long vaddr, void dst, const void src,
	315	unsigned long len)
	316	{
	317	unsigned long phys = page_to_phys(page);
	318	unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
	319
	320	/*
	321	* Flush user page if aliased.
	322	* (Note: a simply flush would be sufficient)
	323	*/
	324
	325	if (alias) {
c4c4594b	326	unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
3a860d16	327	preempt_disable();
c4c4594b	328	__flush_invalidate_dcache_page_alias(t, phys);
3a860d16	329	preempt_enable();
6656920b CZ	330	}
	331
	332	memcpy(dst, src, len);
	333	}
	334
	335	#endif