Commit | Line | Data |
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5a0015d6 CZ |
1 | /* |
2 | * arch/xtensa/kernel/time.c | |
3 | * | |
4 | * Timer and clock support. | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | * Copyright (C) 2005 Tensilica Inc. | |
11 | * | |
12 | * Chris Zankel <chris@zankel.net> | |
13 | */ | |
14 | ||
205ad548 MF |
15 | #include <linux/clk.h> |
16 | #include <linux/clk-provider.h> | |
5a0015d6 | 17 | #include <linux/errno.h> |
d43c36dc | 18 | #include <linux/sched.h> |
5a0015d6 | 19 | #include <linux/time.h> |
fcc8f0f8 | 20 | #include <linux/clocksource.h> |
925f5532 | 21 | #include <linux/clockchips.h> |
5a0015d6 CZ |
22 | #include <linux/interrupt.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/profile.h> | |
27 | #include <linux/delay.h> | |
2206d5dd | 28 | #include <linux/irqdomain.h> |
e3f43291 | 29 | #include <linux/sched_clock.h> |
5a0015d6 CZ |
30 | |
31 | #include <asm/timex.h> | |
32 | #include <asm/platform.h> | |
33 | ||
e504c4b6 | 34 | unsigned long ccount_freq; /* ccount Hz */ |
45ec8860 | 35 | EXPORT_SYMBOL(ccount_freq); |
5a0015d6 | 36 | |
a5a1d1c2 | 37 | static u64 ccount_read(struct clocksource *cs) |
fcc8f0f8 | 38 | { |
a5a1d1c2 | 39 | return (u64)get_ccount(); |
fcc8f0f8 JW |
40 | } |
41 | ||
3ade4f81 | 42 | static u64 notrace ccount_sched_clock_read(void) |
e3f43291 BS |
43 | { |
44 | return get_ccount(); | |
45 | } | |
46 | ||
fcc8f0f8 JW |
47 | static struct clocksource ccount_clocksource = { |
48 | .name = "ccount", | |
49 | .rating = 200, | |
50 | .read = ccount_read, | |
51 | .mask = CLOCKSOURCE_MASK(32), | |
0fb4040e | 52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
fcc8f0f8 JW |
53 | }; |
54 | ||
925f5532 BS |
55 | static int ccount_timer_set_next_event(unsigned long delta, |
56 | struct clock_event_device *dev); | |
62351531 | 57 | struct ccount_timer { |
925f5532 BS |
58 | struct clock_event_device evt; |
59 | int irq_enabled; | |
62351531 | 60 | char name[24]; |
925f5532 | 61 | }; |
62351531 | 62 | static DEFINE_PER_CPU(struct ccount_timer, ccount_timer); |
925f5532 BS |
63 | |
64 | static int ccount_timer_set_next_event(unsigned long delta, | |
65 | struct clock_event_device *dev) | |
66 | { | |
67 | unsigned long flags, next; | |
68 | int ret = 0; | |
69 | ||
70 | local_irq_save(flags); | |
71 | next = get_ccount() + delta; | |
72 | set_linux_timer(next); | |
73 | if (next - get_ccount() > delta) | |
74 | ret = -ETIME; | |
75 | local_irq_restore(flags); | |
76 | ||
77 | return ret; | |
78 | } | |
79 | ||
8e40fc4b VK |
80 | /* |
81 | * There is no way to disable the timer interrupt at the device level, | |
82 | * only at the intenable register itself. Since enable_irq/disable_irq | |
83 | * calls are nested, we need to make sure that these calls are | |
84 | * balanced. | |
85 | */ | |
86 | static int ccount_timer_shutdown(struct clock_event_device *evt) | |
87 | { | |
88 | struct ccount_timer *timer = | |
89 | container_of(evt, struct ccount_timer, evt); | |
90 | ||
91 | if (timer->irq_enabled) { | |
92 | disable_irq(evt->irq); | |
93 | timer->irq_enabled = 0; | |
94 | } | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int ccount_timer_set_oneshot(struct clock_event_device *evt) | |
925f5532 | 99 | { |
62351531 MF |
100 | struct ccount_timer *timer = |
101 | container_of(evt, struct ccount_timer, evt); | |
925f5532 | 102 | |
8e40fc4b VK |
103 | if (!timer->irq_enabled) { |
104 | enable_irq(evt->irq); | |
105 | timer->irq_enabled = 1; | |
925f5532 | 106 | } |
8e40fc4b | 107 | return 0; |
925f5532 BS |
108 | } |
109 | ||
fd43fe19 | 110 | static irqreturn_t timer_interrupt(int irq, void *dev_id); |
5a0015d6 CZ |
111 | static struct irqaction timer_irqaction = { |
112 | .handler = timer_interrupt, | |
925f5532 | 113 | .flags = IRQF_TIMER, |
5a0015d6 CZ |
114 | .name = "timer", |
115 | }; | |
116 | ||
62351531 MF |
117 | void local_timer_setup(unsigned cpu) |
118 | { | |
119 | struct ccount_timer *timer = &per_cpu(ccount_timer, cpu); | |
120 | struct clock_event_device *clockevent = &timer->evt; | |
121 | ||
122 | timer->irq_enabled = 1; | |
123 | clockevent->name = timer->name; | |
124 | snprintf(timer->name, sizeof(timer->name), "ccount_clockevent_%u", cpu); | |
125 | clockevent->features = CLOCK_EVT_FEAT_ONESHOT; | |
126 | clockevent->rating = 300; | |
127 | clockevent->set_next_event = ccount_timer_set_next_event; | |
8e40fc4b VK |
128 | clockevent->set_state_shutdown = ccount_timer_shutdown; |
129 | clockevent->set_state_oneshot = ccount_timer_set_oneshot; | |
130 | clockevent->tick_resume = ccount_timer_set_oneshot; | |
62351531 MF |
131 | clockevent->cpumask = cpumask_of(cpu); |
132 | clockevent->irq = irq_create_mapping(NULL, LINUX_TIMER_INT); | |
133 | if (WARN(!clockevent->irq, "error: can't map timer irq")) | |
134 | return; | |
135 | clockevents_config_and_register(clockevent, ccount_freq, | |
136 | 0xf, 0xffffffff); | |
137 | } | |
138 | ||
205ad548 MF |
139 | #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT |
140 | #ifdef CONFIG_OF | |
141 | static void __init calibrate_ccount(void) | |
142 | { | |
143 | struct device_node *cpu; | |
144 | struct clk *clk; | |
145 | ||
146 | cpu = of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu"); | |
147 | if (cpu) { | |
148 | clk = of_clk_get(cpu, 0); | |
149 | if (!IS_ERR(clk)) { | |
150 | ccount_freq = clk_get_rate(clk); | |
151 | return; | |
152 | } else { | |
153 | pr_warn("%s: CPU input clock not found\n", | |
154 | __func__); | |
155 | } | |
156 | } else { | |
157 | pr_warn("%s: CPU node not found in the device tree\n", | |
158 | __func__); | |
159 | } | |
160 | ||
161 | platform_calibrate_ccount(); | |
162 | } | |
163 | #else | |
164 | static inline void calibrate_ccount(void) | |
165 | { | |
166 | platform_calibrate_ccount(); | |
167 | } | |
168 | #endif | |
169 | #endif | |
170 | ||
5a0015d6 CZ |
171 | void __init time_init(void) |
172 | { | |
205ad548 | 173 | of_clk_init(NULL); |
288a60cf | 174 | #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT |
d4eccafc | 175 | pr_info("Calibrating CPU frequency "); |
205ad548 | 176 | calibrate_ccount(); |
d4eccafc MF |
177 | pr_cont("%d.%02d MHz\n", |
178 | (int)ccount_freq / 1000000, | |
179 | (int)(ccount_freq / 10000) % 100); | |
fedc21dc BS |
180 | #else |
181 | ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL; | |
5a0015d6 | 182 | #endif |
205ad548 MF |
183 | WARN(!ccount_freq, |
184 | "%s: CPU clock frequency is not set up correctly\n", | |
185 | __func__); | |
8d5e1d8e | 186 | clocksource_register_hz(&ccount_clocksource, ccount_freq); |
62351531 MF |
187 | local_timer_setup(0); |
188 | setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction); | |
3ade4f81 | 189 | sched_clock_register(ccount_sched_clock_read, 32, ccount_freq); |
3722ed23 | 190 | clocksource_probe(); |
5a0015d6 CZ |
191 | } |
192 | ||
5a0015d6 CZ |
193 | /* |
194 | * The timer interrupt is called HZ times per second. | |
195 | */ | |
196 | ||
62351531 | 197 | irqreturn_t timer_interrupt(int irq, void *dev_id) |
5a0015d6 | 198 | { |
62351531 | 199 | struct clock_event_device *evt = &this_cpu_ptr(&ccount_timer)->evt; |
5a0015d6 | 200 | |
bae07f8a | 201 | set_linux_timer(get_linux_timer()); |
925f5532 | 202 | evt->event_handler(evt); |
5a0015d6 | 203 | |
2b8aea74 | 204 | /* Allow platform to do something useful (Wdog). */ |
2b8aea74 | 205 | platform_heartbeat(); |
5a0015d6 | 206 | |
5a0015d6 CZ |
207 | return IRQ_HANDLED; |
208 | } | |
209 | ||
210 | #ifndef CONFIG_GENERIC_CALIBRATE_DELAY | |
6cb4c159 | 211 | void calibrate_delay(void) |
5a0015d6 | 212 | { |
8d5e1d8e | 213 | loops_per_jiffy = ccount_freq / HZ; |
d4eccafc MF |
214 | pr_info("Calibrating delay loop (skipped)... %lu.%02lu BogoMIPS preset\n", |
215 | loops_per_jiffy / (1000000 / HZ), | |
216 | (loops_per_jiffy / (10000 / HZ)) % 100); | |
5a0015d6 CZ |
217 | } |
218 | #endif |