[linux-block.git] / arch / xtensa / kernel / hw_breakpoint.c

/*
 * Xtensa hardware breakpoints/watchpoints handling functions
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2016 Cadence Design Systems Inc.
 */

#include <linux/hw_breakpoint.h>
#include <linux/log2.h>
#include <linux/percpu.h>
#include <linux/perf_event.h>
#include <asm/core.h>
#include <asm/hw_breakpoint.h>

/* Breakpoint currently in use for each IBREAKA. */
static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);

/* Watchpoint currently in use for each DBREAKA. */
static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);

int hw_breakpoint_slots(int type)
{
	switch (type) {
	case TYPE_INST:
		return XCHAL_NUM_IBREAK;
	case TYPE_DATA:
		return XCHAL_NUM_DBREAK;
	default:
		pr_warn("unknown slot type: %d\n", type);
		return 0;
	}
}

int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
{
	unsigned int len;
	unsigned long va;

	va = hw->address;
	len = hw->len;

	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
}

/*
 * Construct an arch_hw_breakpoint from a perf_event.
 */
int hw_breakpoint_arch_parse(struct perf_event *bp,
			     const struct perf_event_attr *attr,
			     struct arch_hw_breakpoint *hw)
{
	/* Type */
	switch (attr->bp_type) {
	case HW_BREAKPOINT_X:
		hw->type = XTENSA_BREAKPOINT_EXECUTE;
		break;
	case HW_BREAKPOINT_R:
		hw->type = XTENSA_BREAKPOINT_LOAD;
		break;
	case HW_BREAKPOINT_W:
		hw->type = XTENSA_BREAKPOINT_STORE;
		break;
	case HW_BREAKPOINT_RW:
		hw->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
		break;
	default:
		return -EINVAL;
	}

	/* Len */
	hw->len = attr->bp_len;
	if (hw->len < 1 || hw->len > 64 || !is_power_of_2(hw->len))
		return -EINVAL;

	/* Address */
	hw->address = attr->bp_addr;
	if (hw->address & (hw->len - 1))
		return -EINVAL;

	return 0;
}

int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
				    unsigned long val, void *data)
{
	return NOTIFY_DONE;
}

static void xtensa_wsr(unsigned long v, u8 sr)
{
	/* We don't have indexed wsr and creating instruction dynamically
	 * doesn't seem worth it given how small XCHAL_NUM_IBREAK and
	 * XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
	 * the switch below needs to be extended.
	 */
	BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
	BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);

	switch (sr) {
#if XCHAL_NUM_IBREAK > 0
	case SREG_IBREAKA + 0:
		xtensa_set_sr(v, SREG_IBREAKA + 0);
		break;
#endif
#if XCHAL_NUM_IBREAK > 1
	case SREG_IBREAKA + 1:
		xtensa_set_sr(v, SREG_IBREAKA + 1);
		break;
#endif

#if XCHAL_NUM_DBREAK > 0
	case SREG_DBREAKA + 0:
		xtensa_set_sr(v, SREG_DBREAKA + 0);
		break;
	case SREG_DBREAKC + 0:
		xtensa_set_sr(v, SREG_DBREAKC + 0);
		break;
#endif
#if XCHAL_NUM_DBREAK > 1
	case SREG_DBREAKA + 1:
		xtensa_set_sr(v, SREG_DBREAKA + 1);
		break;

	case SREG_DBREAKC + 1:
		xtensa_set_sr(v, SREG_DBREAKC + 1);
		break;
#endif
	}
}

static int alloc_slot(struct perf_event **slot, size_t n,
		      struct perf_event *bp)
{
	size_t i;

	for (i = 0; i < n; ++i) {
		if (!slot[i]) {
			slot[i] = bp;
			return i;
		}
	}
	return -EBUSY;
}

static void set_ibreak_regs(int reg, struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long ibreakenable;

	xtensa_wsr(info->address, SREG_IBREAKA + reg);
	ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
	xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
}

static void set_dbreak_regs(int reg, struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;

	if (info->type & XTENSA_BREAKPOINT_LOAD)
		dbreakc |= DBREAKC_LOAD_MASK;
	if (info->type & XTENSA_BREAKPOINT_STORE)
		dbreakc |= DBREAKC_STOR_MASK;

	xtensa_wsr(info->address, SREG_DBREAKA + reg);
	xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
}

int arch_install_hw_breakpoint(struct perf_event *bp)
{
	int i;

	if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
		/* Breakpoint */
		i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
		if (i < 0)
			return i;
		set_ibreak_regs(i, bp);

	} else {
		/* Watchpoint */
		i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
		if (i < 0)
			return i;
		set_dbreak_regs(i, bp);
	}
	return 0;
}

static int free_slot(struct perf_event **slot, size_t n,
		     struct perf_event *bp)
{
	size_t i;

	for (i = 0; i < n; ++i) {
		if (slot[i] == bp) {
			slot[i] = NULL;
			return i;
		}
	}
	return -EBUSY;
}

void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	int i;

	if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
		unsigned long ibreakenable;

		/* Breakpoint */
		i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
		if (i >= 0) {
			ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
			xtensa_set_sr(ibreakenable & ~(1 << i),
				      SREG_IBREAKENABLE);
		}
	} else {
		/* Watchpoint */
		i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
		if (i >= 0)
			xtensa_wsr(0, SREG_DBREAKC + i);
	}
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
}

void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	int i;
	struct thread_struct *t = &tsk->thread;

	for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
		if (t->ptrace_bp[i]) {
			unregister_hw_breakpoint(t->ptrace_bp[i]);
			t->ptrace_bp[i] = NULL;
		}
	}
	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
		if (t->ptrace_wp[i]) {
			unregister_hw_breakpoint(t->ptrace_wp[i]);
			t->ptrace_wp[i] = NULL;
		}
	}
}

/*
 * Set ptrace breakpoint pointers to zero for this task.
 * This is required in order to prevent child processes from unregistering
 * breakpoints held by their parent.
 */
void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
	memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
}

void restore_dbreak(void)
{
	int i;

	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
		struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];

		if (bp)
			set_dbreak_regs(i, bp);
	}
	clear_thread_flag(TIF_DB_DISABLED);
}

int check_hw_breakpoint(struct pt_regs *regs)
{
	if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
		int i;
		struct perf_event **bp = this_cpu_ptr(bp_on_reg);

		for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
			if (bp[i] && !bp[i]->attr.disabled &&
			    regs->pc == bp[i]->attr.bp_addr)
				perf_bp_event(bp[i], regs);
		}
		return 0;
	} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
		struct perf_event **bp = this_cpu_ptr(wp_on_reg);
		int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
			DEBUGCAUSE_DBNUM_SHIFT;

		if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
			if (user_mode(regs)) {
				perf_bp_event(bp[dbnum], regs);
			} else {
				set_thread_flag(TIF_DB_DISABLED);
				xtensa_wsr(0, SREG_DBREAKC + dbnum);
			}
		} else {
			WARN_ONCE(1,
				  "Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
				  dbnum);
		}
		return 0;
	}
	return -ENOENT;
}
Commit	Line	Data
c91e02bd MF	1	/*
	2	* Xtensa hardware breakpoints/watchpoints handling functions
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2016 Cadence Design Systems Inc.
	9	*/
	10
	11	#include <linux/hw_breakpoint.h>
	12	#include <linux/log2.h>
	13	#include <linux/percpu.h>
	14	#include <linux/perf_event.h>
8f8d5745	15	#include <asm/core.h>
2e413b1e	16	#include <asm/hw_breakpoint.h>
c91e02bd MF	17
	18	/* Breakpoint currently in use for each IBREAKA. */
	19	static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
	20
	21	/* Watchpoint currently in use for each DBREAKA. */
	22	static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
	23
	24	int hw_breakpoint_slots(int type)
	25	{
	26	switch (type) {
	27	case TYPE_INST:
	28	return XCHAL_NUM_IBREAK;
	29	case TYPE_DATA:
	30	return XCHAL_NUM_DBREAK;
	31	default:
	32	pr_warn("unknown slot type: %d\n", type);
	33	return 0;
	34	}
	35	}
	36
8e983ff9	37	int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
c91e02bd MF	38	{
	39	unsigned int len;
	40	unsigned long va;
c91e02bd	41
8e983ff9 FW	42	va = hw->address;
8e983ff9 FW	43	len = hw->len;
c91e02bd MF	44
	45	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
	46	}
	47
	48	/*
	49	* Construct an arch_hw_breakpoint from a perf_event.
	50	*/
ac46c7fd FW	51	int hw_breakpoint_arch_parse(struct perf_event *bp,
	52	const struct perf_event_attr *attr,
	53	struct arch_hw_breakpoint *hw)
c91e02bd	54	{
c91e02bd	55	/* Type */
ac46c7fd	56	switch (attr->bp_type) {
c91e02bd	57	case HW_BREAKPOINT_X:
ac46c7fd	58	hw->type = XTENSA_BREAKPOINT_EXECUTE;
c91e02bd MF	59	break;
c91e02bd MF	60	case HW_BREAKPOINT_R:
ac46c7fd	61	hw->type = XTENSA_BREAKPOINT_LOAD;
c91e02bd MF	62	break;
c91e02bd MF	63	case HW_BREAKPOINT_W:
ac46c7fd	64	hw->type = XTENSA_BREAKPOINT_STORE;
c91e02bd MF	65	break;
c91e02bd MF	66	case HW_BREAKPOINT_RW:
ac46c7fd	67	hw->type = XTENSA_BREAKPOINT_LOAD \| XTENSA_BREAKPOINT_STORE;
c91e02bd MF	68	break;
	69	default:
	70	return -EINVAL;
	71	}
	72
	73	/* Len */
ac46c7fd FW	74	hw->len = attr->bp_len;
ac46c7fd FW	75	if (hw->len < 1 \|\| hw->len > 64 \|\| !is_power_of_2(hw->len))
c91e02bd MF	76	return -EINVAL;
	77
	78	/* Address */
ac46c7fd FW	79	hw->address = attr->bp_addr;
ac46c7fd FW	80	if (hw->address & (hw->len - 1))
c91e02bd MF	81	return -EINVAL;
	82
	83	return 0;
	84	}
	85
c91e02bd MF	86	int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
	87	unsigned long val, void *data)
	88	{
	89	return NOTIFY_DONE;
	90	}
	91
	92	static void xtensa_wsr(unsigned long v, u8 sr)
	93	{
	94	/* We don't have indexed wsr and creating instruction dynamically
	95	* doesn't seem worth it given how small XCHAL_NUM_IBREAK and
	96	* XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
	97	* the switch below needs to be extended.
	98	*/
	99	BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
	100	BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
	101
	102	switch (sr) {
	103	#if XCHAL_NUM_IBREAK > 0
	104	case SREG_IBREAKA + 0:
cad6fade	105	xtensa_set_sr(v, SREG_IBREAKA + 0);
c91e02bd MF	106	break;
	107	#endif
	108	#if XCHAL_NUM_IBREAK > 1
	109	case SREG_IBREAKA + 1:
cad6fade	110	xtensa_set_sr(v, SREG_IBREAKA + 1);
c91e02bd MF	111	break;
	112	#endif
	113
	114	#if XCHAL_NUM_DBREAK > 0
	115	case SREG_DBREAKA + 0:
cad6fade	116	xtensa_set_sr(v, SREG_DBREAKA + 0);
c91e02bd MF	117	break;
c91e02bd MF	118	case SREG_DBREAKC + 0:
cad6fade	119	xtensa_set_sr(v, SREG_DBREAKC + 0);
c91e02bd MF	120	break;
	121	#endif
	122	#if XCHAL_NUM_DBREAK > 1
	123	case SREG_DBREAKA + 1:
cad6fade	124	xtensa_set_sr(v, SREG_DBREAKA + 1);
c91e02bd MF	125	break;
	126
	127	case SREG_DBREAKC + 1:
cad6fade	128	xtensa_set_sr(v, SREG_DBREAKC + 1);
c91e02bd MF	129	break;
	130	#endif
	131	}
	132	}
	133
	134	static int alloc_slot(struct perf_event **slot, size_t n,
	135	struct perf_event *bp)
	136	{
	137	size_t i;
	138
	139	for (i = 0; i < n; ++i) {
	140	if (!slot[i]) {
	141	slot[i] = bp;
	142	return i;
	143	}
	144	}
	145	return -EBUSY;
	146	}
	147
	148	static void set_ibreak_regs(int reg, struct perf_event *bp)
	149	{
	150	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	151	unsigned long ibreakenable;
	152
	153	xtensa_wsr(info->address, SREG_IBREAKA + reg);
cad6fade MF	154	ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
cad6fade MF	155	xtensa_set_sr(ibreakenable \| (1 << reg), SREG_IBREAKENABLE);
c91e02bd MF	156	}
	157
	158	static void set_dbreak_regs(int reg, struct perf_event *bp)
	159	{
	160	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	161	unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
	162
	163	if (info->type & XTENSA_BREAKPOINT_LOAD)
	164	dbreakc \|= DBREAKC_LOAD_MASK;
	165	if (info->type & XTENSA_BREAKPOINT_STORE)
	166	dbreakc \|= DBREAKC_STOR_MASK;
	167
	168	xtensa_wsr(info->address, SREG_DBREAKA + reg);
	169	xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
	170	}
	171
	172	int arch_install_hw_breakpoint(struct perf_event *bp)
	173	{
	174	int i;
	175
	176	if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
	177	/* Breakpoint */
	178	i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
	179	if (i < 0)
	180	return i;
	181	set_ibreak_regs(i, bp);
	182
	183	} else {
	184	/* Watchpoint */
	185	i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
	186	if (i < 0)
	187	return i;
	188	set_dbreak_regs(i, bp);
	189	}
	190	return 0;
	191	}
	192
	193	static int free_slot(struct perf_event **slot, size_t n,
	194	struct perf_event *bp)
	195	{
	196	size_t i;
	197
	198	for (i = 0; i < n; ++i) {
	199	if (slot[i] == bp) {
	200	slot[i] = NULL;
	201	return i;
	202	}
	203	}
	204	return -EBUSY;
	205	}
	206
	207	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
	208	{
	209	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	210	int i;
	211
	212	if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
	213	unsigned long ibreakenable;
	214
	215	/* Breakpoint */
	216	i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
	217	if (i >= 0) {
cad6fade MF	218	ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
	219	xtensa_set_sr(ibreakenable & ~(1 << i),
	220	SREG_IBREAKENABLE);
c91e02bd MF	221	}
	222	} else {
	223	/* Watchpoint */
	224	i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
	225	if (i >= 0)
	226	xtensa_wsr(0, SREG_DBREAKC + i);
	227	}
	228	}
	229
	230	void hw_breakpoint_pmu_read(struct perf_event *bp)
	231	{
	232	}
	233
	234	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
	235	{
	236	int i;
	237	struct thread_struct *t = &tsk->thread;
	238
	239	for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
	240	if (t->ptrace_bp[i]) {
	241	unregister_hw_breakpoint(t->ptrace_bp[i]);
	242	t->ptrace_bp[i] = NULL;
	243	}
	244	}
	245	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
	246	if (t->ptrace_wp[i]) {
	247	unregister_hw_breakpoint(t->ptrace_wp[i]);
	248	t->ptrace_wp[i] = NULL;
	249	}
	250	}
	251	}
	252
	253	/*
	254	* Set ptrace breakpoint pointers to zero for this task.
	255	* This is required in order to prevent child processes from unregistering
	256	* breakpoints held by their parent.
	257	*/
	258	void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
	259	{
	260	memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
	261	memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
	262	}
	263
	264	void restore_dbreak(void)
	265	{
	266	int i;
	267
	268	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
	269	struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
	270
	271	if (bp)
	272	set_dbreak_regs(i, bp);
	273	}
	274	clear_thread_flag(TIF_DB_DISABLED);
	275	}
	276
	277	int check_hw_breakpoint(struct pt_regs *regs)
	278	{
	279	if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
	280	int i;
	281	struct perf_event **bp = this_cpu_ptr(bp_on_reg);
	282
	283	for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
	284	if (bp[i] && !bp[i]->attr.disabled &&
285	regs->pc == bp[i]->attr.bp_addr)
286	perf_bp_event(bp[i], regs);
287	}
288	return 0;
289	} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
290	struct perf_event **bp = this_cpu_ptr(wp_on_reg);
291	int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
292	DEBUGCAUSE_DBNUM_SHIFT;
293
294	if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
295	if (user_mode(regs)) {
296	perf_bp_event(bp[dbnum], regs);
297	} else {
298	set_thread_flag(TIF_DB_DISABLED);
299	xtensa_wsr(0, SREG_DBREAKC + dbnum);
300	}
301	} else {
302	WARN_ONCE(1,
303	"Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
304	dbnum);
305	}
306	return 0;
307	}
308	return -ENOENT;
309	}