Commit | Line | Data |
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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
8e1a6dd2 | 2 | config XTENSA |
35f9cd08 | 3 | def_bool y |
942fa985 | 4 | select ARCH_32BIT_OFF_T |
aef0f78e | 5 | select ARCH_HAS_BINFMT_FLAT if !MMU |
92652cf9 | 6 | select ARCH_HAS_CURRENT_STACK_POINTER |
af7a16e5 | 7 | select ARCH_HAS_DEBUG_VM_PGTABLE |
0f665b9e | 8 | select ARCH_HAS_DMA_PREP_COHERENT if MMU |
0847d167 | 9 | select ARCH_HAS_GCOV_PROFILE_ALL |
c49731a0 | 10 | select ARCH_HAS_KCOV |
0f665b9e CH |
11 | select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU |
12 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU | |
fa7e2247 | 13 | select ARCH_HAS_DMA_SET_UNCACHED if MMU |
e6226997 AB |
14 | select ARCH_HAS_STRNCPY_FROM_USER if !KASAN |
15 | select ARCH_HAS_STRNLEN_USER | |
dce44566 | 16 | select ARCH_USE_MEMTEST |
579afe86 MF |
17 | select ARCH_USE_QUEUED_RWLOCKS |
18 | select ARCH_USE_QUEUED_SPINLOCKS | |
8f371c75 | 19 | select ARCH_WANT_FRAME_POINTERS |
e969161b | 20 | select ARCH_WANT_IPC_PARSE_VERSION |
10916706 | 21 | select BUILDTIME_TABLE_SORT |
3e41f9ba | 22 | select CLONE_BACKWARDS |
920f8a39 | 23 | select COMMON_CLK |
f5ff79fd | 24 | select DMA_NONCOHERENT_MMAP if MMU |
920f8a39 | 25 | select GENERIC_ATOMIC64 |
920f8a39 | 26 | select GENERIC_IRQ_SHOW |
19c5699f MF |
27 | select GENERIC_LIB_CMPDI2 |
28 | select GENERIC_LIB_MULDI3 | |
29 | select GENERIC_LIB_UCMPDI2 | |
920f8a39 MF |
30 | select GENERIC_PCI_IOMAP |
31 | select GENERIC_SCHED_CLOCK | |
ef1a935c | 32 | select HAVE_ARCH_AUDITSYSCALL |
7af710d9 MF |
33 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
34 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL | |
725aea87 | 35 | select HAVE_ARCH_KCSAN |
da94a40f | 36 | select HAVE_ARCH_SECCOMP_FILTER |
9f24f3c1 | 37 | select HAVE_ARCH_TRACEHOOK |
24a9c541 | 38 | select HAVE_CONTEXT_TRACKING_USER |
0e46c111 | 39 | select HAVE_DEBUG_KMEMLEAK |
9d2ffe5c | 40 | select HAVE_DMA_CONTIGUOUS |
5f56a5df | 41 | select HAVE_EXIT_THREAD |
478ba61a | 42 | select HAVE_FUNCTION_TRACER |
7dc0eb0b | 43 | select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000 |
c91e02bd | 44 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
496543c4 | 45 | select HAVE_IRQ_TIME_ACCOUNTING |
eb01d42a | 46 | select HAVE_PCI |
a6f3eefa | 47 | select HAVE_PERF_EVENTS |
d148eac0 | 48 | select HAVE_STACKPROTECTOR |
af5395c2 | 49 | select HAVE_SYSCALL_TRACEPOINTS |
50718569 | 50 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
920f8a39 MF |
51 | select IRQ_DOMAIN |
52 | select MODULES_USE_ELF_RELA | |
db8165f5 | 53 | select PERF_USE_VMALLOC |
4aae683f | 54 | select TRACE_IRQFLAGS_SUPPORT |
8e1a6dd2 CZ |
55 | help |
56 | Xtensa processors are 32-bit RISC machines designed by Tensilica | |
57 | primarily for embedded systems. These processors are both | |
58 | configurable and extensible. The Linux port to the Xtensa | |
59 | architecture supports all processor configurations and extensions, | |
60 | with reasonable minimum requirements. The Xtensa Linux project has | |
0ada4490 | 61 | a home page at <http://www.linux-xtensa.org/>. |
8e1a6dd2 | 62 | |
d4337aa5 | 63 | config GENERIC_HWEIGHT |
35f9cd08 | 64 | def_bool y |
d4337aa5 | 65 | |
f0d1b0b3 | 66 | config ARCH_HAS_ILOG2_U32 |
35f9cd08 | 67 | def_bool n |
f0d1b0b3 DH |
68 | |
69 | config ARCH_HAS_ILOG2_U64 | |
35f9cd08 | 70 | def_bool n |
f0d1b0b3 | 71 | |
ce816fa8 | 72 | config NO_IOPORT_MAP |
d046f77e | 73 | def_bool n |
5ea81769 | 74 | |
bdc80787 PA |
75 | config HZ |
76 | int | |
77 | default 100 | |
78 | ||
8f371c75 MF |
79 | config LOCKDEP_SUPPORT |
80 | def_bool y | |
81 | ||
3e4196a5 MF |
82 | config STACKTRACE_SUPPORT |
83 | def_bool y | |
84 | ||
35f9cd08 | 85 | config MMU |
de7c1c78 | 86 | def_bool n |
a8f0c31f | 87 | select PFAULT |
35f9cd08 | 88 | |
a1a2bdec BS |
89 | config HAVE_XTENSA_GPIO32 |
90 | def_bool n | |
91 | ||
c633544a MF |
92 | config KASAN_SHADOW_OFFSET |
93 | hex | |
94 | default 0x6e400000 | |
95 | ||
c425c546 MY |
96 | config CPU_BIG_ENDIAN |
97 | def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) | |
98 | ||
99 | config CPU_LITTLE_ENDIAN | |
100 | def_bool !CPU_BIG_ENDIAN | |
101 | ||
c20e1117 MF |
102 | config CC_HAVE_CALL0_ABI |
103 | def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) | |
104 | ||
8e1a6dd2 CZ |
105 | menu "Processor type and features" |
106 | ||
107 | choice | |
108 | prompt "Xtensa Processor Configuration" | |
173d6681 | 109 | default XTENSA_VARIANT_FSF |
8e1a6dd2 | 110 | |
173d6681 | 111 | config XTENSA_VARIANT_FSF |
0025427e | 112 | bool "fsf - default (not generic) configuration" |
35f9cd08 | 113 | select MMU |
0025427e CZ |
114 | |
115 | config XTENSA_VARIANT_DC232B | |
116 | bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" | |
35f9cd08 | 117 | select MMU |
a1a2bdec | 118 | select HAVE_XTENSA_GPIO32 |
0025427e | 119 | help |
35f9cd08 | 120 | This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). |
000af2c5 | 121 | |
d0b73b48 PD |
122 | config XTENSA_VARIANT_DC233C |
123 | bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" | |
124 | select MMU | |
a1a2bdec | 125 | select HAVE_XTENSA_GPIO32 |
d0b73b48 PD |
126 | help |
127 | This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). | |
128 | ||
420ae951 MF |
129 | config XTENSA_VARIANT_CUSTOM |
130 | bool "Custom Xtensa processor configuration" | |
420ae951 MF |
131 | select HAVE_XTENSA_GPIO32 |
132 | help | |
133 | Select this variant to use a custom Xtensa processor configuration. | |
134 | You will be prompted for a processor variant CORENAME. | |
8e1a6dd2 CZ |
135 | endchoice |
136 | ||
420ae951 MF |
137 | config XTENSA_VARIANT_CUSTOM_NAME |
138 | string "Xtensa Processor Custom Core Variant Name" | |
139 | depends on XTENSA_VARIANT_CUSTOM | |
140 | help | |
141 | Provide the name of a custom Xtensa processor variant. | |
142 | This CORENAME selects arch/xtensa/variant/CORENAME. | |
70cbddb9 | 143 | Don't forget you have to select MMU if you have one. |
420ae951 MF |
144 | |
145 | config XTENSA_VARIANT_NAME | |
146 | string | |
147 | default "dc232b" if XTENSA_VARIANT_DC232B | |
148 | default "dc233c" if XTENSA_VARIANT_DC233C | |
149 | default "fsf" if XTENSA_VARIANT_FSF | |
420ae951 MF |
150 | default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM |
151 | ||
152 | config XTENSA_VARIANT_MMU | |
153 | bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" | |
154 | depends on XTENSA_VARIANT_CUSTOM | |
155 | default y | |
de7c1c78 | 156 | select MMU |
420ae951 MF |
157 | help |
158 | Build a Conventional Kernel with full MMU support, | |
159 | ie: it supports a TLB with auto-loading, page protection. | |
160 | ||
9bd46da4 MF |
161 | config XTENSA_VARIANT_HAVE_PERF_EVENTS |
162 | bool "Core variant has Performance Monitor Module" | |
163 | depends on XTENSA_VARIANT_CUSTOM | |
164 | default n | |
165 | help | |
166 | Enable if core variant has Performance Monitor Module with | |
167 | External Registers Interface. | |
168 | ||
169 | If unsure, say N. | |
170 | ||
e4629194 MF |
171 | config XTENSA_FAKE_NMI |
172 | bool "Treat PMM IRQ as NMI" | |
173 | depends on XTENSA_VARIANT_HAVE_PERF_EVENTS | |
174 | default n | |
175 | help | |
176 | If PMM IRQ is the only IRQ at EXCM level it is safe to | |
177 | treat it as NMI, which improves accuracy of profiling. | |
178 | ||
179 | If there are other interrupts at or above PMM IRQ priority level | |
180 | but not above the EXCM level, PMM IRQ still may be treated as NMI, | |
181 | but only if these IRQs are not used. There will be a build warning | |
182 | saying that this is not safe, and a bugcheck if one of these IRQs | |
183 | actually fire. | |
184 | ||
185 | If unsure, say N. | |
186 | ||
a8f0c31f MF |
187 | config PFAULT |
188 | bool "Handle protection faults" if EXPERT && !MMU | |
189 | default y | |
190 | help | |
191 | Handle protection faults. MMU configurations must enable it. | |
192 | noMMU configurations may disable it if used memory map never | |
193 | generates protection faults or faults are always fatal. | |
194 | ||
195 | If unsure, say Y. | |
196 | ||
8e1a6dd2 | 197 | config XTENSA_UNALIGNED_USER |
ad33cc80 | 198 | bool "Unaligned memory access in user space" |
35f9cd08 JW |
199 | help |
200 | The Xtensa architecture currently does not handle unaligned | |
201 | memory accesses in hardware but through an exception handler. | |
202 | Per default, unaligned memory accesses are disabled in user space. | |
8e1a6dd2 | 203 | |
35f9cd08 | 204 | Say Y here to enable unaligned memory access in user space. |
8e1a6dd2 | 205 | |
f615136c MF |
206 | config HAVE_SMP |
207 | bool "System Supports SMP (MX)" | |
de7c1c78 | 208 | depends on XTENSA_VARIANT_CUSTOM |
f615136c MF |
209 | select XTENSA_MX |
210 | help | |
58bc6c69 | 211 | This option is used to indicate that the system-on-a-chip (SOC) |
f615136c MF |
212 | supports Multiprocessing. Multiprocessor support implemented above |
213 | the CPU core definition and currently needs to be selected manually. | |
214 | ||
58bc6c69 | 215 | Multiprocessor support is implemented with external cache and |
769a12a9 | 216 | interrupt controllers. |
f615136c MF |
217 | |
218 | The MX interrupt distributer adds Interprocessor Interrupts | |
219 | and causes the IRQ numbers to be increased by 4 for devices | |
220 | like the open cores ethernet driver and the serial interface. | |
221 | ||
222 | You still have to select "Enable SMP" to enable SMP on this SOC. | |
223 | ||
224 | config SMP | |
225 | bool "Enable Symmetric multi-processing support" | |
226 | depends on HAVE_SMP | |
f615136c MF |
227 | select GENERIC_SMP_IDLE_THREAD |
228 | help | |
229 | Enabled SMP Software; allows more than one CPU/CORE | |
230 | to be activated during startup. | |
231 | ||
232 | config NR_CPUS | |
233 | depends on SMP | |
234 | int "Maximum number of CPUs (2-32)" | |
235 | range 2 32 | |
236 | default "4" | |
237 | ||
49b424fe MF |
238 | config HOTPLUG_CPU |
239 | bool "Enable CPU hotplug support" | |
240 | depends on SMP | |
241 | help | |
242 | Say Y here to allow turning CPUs off and on. CPUs can be | |
243 | controlled through /sys/devices/system/cpu. | |
244 | ||
245 | Say N if you want to disable CPU hotplug. | |
246 | ||
89b184f9 MF |
247 | config SECONDARY_RESET_VECTOR |
248 | bool "Secondary cores use alternative reset vector" | |
249 | default y | |
250 | depends on HAVE_SMP | |
251 | help | |
252 | Secondary cores may be configured to use alternative reset vector, | |
253 | or all cores may use primary reset vector. | |
254 | Say Y here to supply handler for the alternative reset location. | |
255 | ||
9184289c MF |
256 | config FAST_SYSCALL_XTENSA |
257 | bool "Enable fast atomic syscalls" | |
258 | default n | |
259 | help | |
260 | fast_syscall_xtensa is a syscall that can make atomic operations | |
261 | on UP kernel when processor has no s32c1i support. | |
262 | ||
263 | This syscall is deprecated. It may have issues when called with | |
264 | invalid arguments. It is provided only for backwards compatibility. | |
265 | Only enable it if your userspace software requires it. | |
266 | ||
267 | If unsure, say N. | |
268 | ||
269 | config FAST_SYSCALL_SPILL_REGISTERS | |
270 | bool "Enable spill registers syscall" | |
271 | default n | |
272 | help | |
273 | fast_syscall_spill_registers is a syscall that spills all active | |
274 | register windows of a calling userspace task onto its stack. | |
275 | ||
276 | This syscall is deprecated. It may have issues when called with | |
277 | invalid arguments. It is provided only for backwards compatibility. | |
278 | Only enable it if your userspace software requires it. | |
279 | ||
280 | If unsure, say N. | |
281 | ||
c20e1117 MF |
282 | choice |
283 | prompt "Kernel ABI" | |
284 | default KERNEL_ABI_DEFAULT | |
285 | help | |
286 | Select ABI for the kernel code. This ABI is independent of the | |
287 | supported userspace ABI and any combination of the | |
288 | kernel/userspace ABI is possible and should work. | |
289 | ||
290 | In case both kernel and userspace support only call0 ABI | |
291 | all register windows support code will be omitted from the | |
292 | build. | |
293 | ||
294 | If unsure, choose the default ABI. | |
295 | ||
296 | config KERNEL_ABI_DEFAULT | |
297 | bool "Default ABI" | |
298 | help | |
299 | Select this option to compile kernel code with the default ABI | |
300 | selected for the toolchain. | |
301 | Normally cores with windowed registers option use windowed ABI and | |
302 | cores without it use call0 ABI. | |
303 | ||
304 | config KERNEL_ABI_CALL0 | |
305 | bool "Call0 ABI" if CC_HAVE_CALL0_ABI | |
306 | help | |
307 | Select this option to compile kernel code with call0 ABI even with | |
308 | toolchain that defaults to windowed ABI. | |
309 | When this option is not selected the default toolchain ABI will | |
310 | be used for the kernel code. | |
311 | ||
312 | endchoice | |
313 | ||
09f8a6db MF |
314 | config USER_ABI_CALL0 |
315 | bool | |
316 | ||
317 | choice | |
318 | prompt "Userspace ABI" | |
319 | default USER_ABI_DEFAULT | |
320 | help | |
321 | Select supported userspace ABI. | |
322 | ||
323 | If unsure, choose the default ABI. | |
324 | ||
325 | config USER_ABI_DEFAULT | |
326 | bool "Default ABI only" | |
327 | help | |
328 | Assume default userspace ABI. For XEA2 cores it is windowed ABI. | |
329 | call0 ABI binaries may be run on such kernel, but signal delivery | |
330 | will not work correctly for them. | |
331 | ||
332 | config USER_ABI_CALL0_ONLY | |
333 | bool "Call0 ABI only" | |
334 | select USER_ABI_CALL0 | |
335 | help | |
336 | Select this option to support only call0 ABI in userspace. | |
337 | Windowed ABI binaries will crash with a segfault caused by | |
338 | an illegal instruction exception on the first 'entry' opcode. | |
339 | ||
340 | Choose this option if you're planning to run only user code | |
341 | built with call0 ABI. | |
342 | ||
343 | config USER_ABI_CALL0_PROBE | |
344 | bool "Support both windowed and call0 ABI by probing" | |
345 | select USER_ABI_CALL0 | |
346 | help | |
347 | Select this option to support both windowed and call0 userspace | |
348 | ABIs. When enabled all processes are started with PS.WOE disabled | |
349 | and a fast user exception handler for an illegal instruction is | |
350 | used to turn on PS.WOE bit on the first 'entry' opcode executed by | |
351 | the userspace. | |
352 | ||
353 | This option should be enabled for the kernel that must support | |
354 | both call0 and windowed ABIs in userspace at the same time. | |
355 | ||
356 | Note that Xtensa ISA does not guarantee that entry opcode will | |
357 | raise an illegal instruction exception on cores with XEA2 when | |
358 | PS.WOE is disabled, check whether the target core supports it. | |
359 | ||
360 | endchoice | |
361 | ||
8e1a6dd2 CZ |
362 | endmenu |
363 | ||
35f9cd08 JW |
364 | config XTENSA_CALIBRATE_CCOUNT |
365 | def_bool n | |
366 | help | |
367 | On some platforms (XT2000, for example), the CPU clock rate can | |
368 | vary. The frequency can be determined, however, by measuring | |
369 | against a well known, fixed frequency, such as an UART oscillator. | |
370 | ||
371 | config SERIAL_CONSOLE | |
372 | def_bool n | |
373 | ||
7af710d9 MF |
374 | config PLATFORM_HAVE_XIP |
375 | def_bool n | |
376 | ||
8e1a6dd2 CZ |
377 | menu "Platform options" |
378 | ||
379 | choice | |
380 | prompt "Xtensa System Type" | |
381 | default XTENSA_PLATFORM_ISS | |
382 | ||
383 | config XTENSA_PLATFORM_ISS | |
384 | bool "ISS" | |
35f9cd08 JW |
385 | select XTENSA_CALIBRATE_CCOUNT |
386 | select SERIAL_CONSOLE | |
8e1a6dd2 CZ |
387 | help |
388 | ISS is an acronym for Tensilica's Instruction Set Simulator. | |
389 | ||
390 | config XTENSA_PLATFORM_XT2000 | |
391 | bool "XT2000" | |
392 | help | |
393 | XT2000 is the name of Tensilica's feature-rich emulation platform. | |
394 | This hardware is capable of running a full Linux distribution. | |
395 | ||
0d456bad MF |
396 | config XTENSA_PLATFORM_XTFPGA |
397 | bool "XTFPGA" | |
61e47e9b | 398 | select ETHOC if ETHERNET |
3de00482 | 399 | select PLATFORM_WANT_DEFAULT_MEM if !MMU |
0d456bad | 400 | select SERIAL_CONSOLE |
0d456bad | 401 | select XTENSA_CALIBRATE_CCOUNT |
7af710d9 | 402 | select PLATFORM_HAVE_XIP |
0d456bad MF |
403 | help |
404 | XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). | |
405 | This hardware is capable of running a full Linux distribution. | |
406 | ||
8e1a6dd2 CZ |
407 | endchoice |
408 | ||
994fa1c8 MF |
409 | config PLATFORM_NR_IRQS |
410 | int | |
411 | default 3 if XTENSA_PLATFORM_XT2000 | |
412 | default 0 | |
8e1a6dd2 | 413 | |
8e1a6dd2 CZ |
414 | config XTENSA_CPU_CLOCK |
415 | int "CPU clock rate [MHz]" | |
416 | depends on !XTENSA_CALIBRATE_CCOUNT | |
35f9cd08 | 417 | default 16 |
8e1a6dd2 CZ |
418 | |
419 | config GENERIC_CALIBRATE_DELAY | |
420 | bool "Auto calibration of the BogoMIPS value" | |
35f9cd08 | 421 | help |
82300bf4 | 422 | The BogoMIPS value can easily be derived from the CPU frequency. |
8e1a6dd2 CZ |
423 | |
424 | config CMDLINE_BOOL | |
425 | bool "Default bootloader kernel arguments" | |
426 | ||
427 | config CMDLINE | |
428 | string "Initial kernel command string" | |
429 | depends on CMDLINE_BOOL | |
430 | default "console=ttyS0,38400 root=/dev/ram" | |
431 | help | |
432 | On some architectures (EBSA110 and CATS), there is currently no way | |
433 | for the boot loader to pass arguments to the kernel. For these | |
434 | architectures, you should supply some command-line options at build | |
435 | time by entering them here. As a minimum, you should specify the | |
436 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
437 | ||
da844a81 MF |
438 | config USE_OF |
439 | bool "Flattened Device Tree support" | |
440 | select OF | |
441 | select OF_EARLY_FLATTREE | |
442 | help | |
443 | Include support for flattened device tree machine descriptions. | |
444 | ||
687cffd3 | 445 | config BUILTIN_DTB_SOURCE |
da844a81 MF |
446 | string "DTB to build into the kernel image" |
447 | depends on OF | |
448 | ||
baac1d36 MF |
449 | config PARSE_BOOTPARAM |
450 | bool "Parse bootparam block" | |
451 | default y | |
452 | help | |
453 | Parse parameters passed to the kernel from the bootloader. It may | |
454 | be disabled if the kernel is known to run without the bootloader. | |
455 | ||
456 | If unsure, say Y. | |
457 | ||
6a8eb99e MF |
458 | choice |
459 | prompt "Semihosting interface" | |
460 | default XTENSA_SIMCALL_ISS | |
461 | depends on XTENSA_PLATFORM_ISS | |
462 | help | |
463 | Choose semihosting interface that will be used for serial port, | |
464 | block device and networking. | |
465 | ||
466 | config XTENSA_SIMCALL_ISS | |
467 | bool "simcall" | |
468 | help | |
469 | Use simcall instruction. simcall is only available on simulators, | |
470 | it does nothing on hardware. | |
471 | ||
472 | config XTENSA_SIMCALL_GDBIO | |
473 | bool "GDBIO" | |
474 | help | |
475 | Use break instruction. It is available on real hardware when GDB | |
476 | is attached to it via JTAG. | |
477 | ||
478 | endchoice | |
479 | ||
b6c7e873 VP |
480 | config BLK_DEV_SIMDISK |
481 | tristate "Host file-based simulated block device support" | |
482 | default n | |
7a0684cd | 483 | depends on XTENSA_PLATFORM_ISS && BLOCK |
b6c7e873 VP |
484 | help |
485 | Create block devices that map to files in the host file system. | |
486 | Device binding to host file may be changed at runtime via proc | |
487 | interface provided the device is not in use. | |
488 | ||
489 | config BLK_DEV_SIMDISK_COUNT | |
490 | int "Number of host file-based simulated block devices" | |
491 | range 1 10 | |
492 | depends on BLK_DEV_SIMDISK | |
493 | default 2 | |
494 | help | |
495 | This is the default minimal number of created block devices. | |
496 | Kernel/module parameter 'simdisk_count' may be used to change this | |
497 | value at runtime. More file names (but no more than 10) may be | |
498 | specified as parameters, simdisk_count grows accordingly. | |
499 | ||
500 | config SIMDISK0_FILENAME | |
501 | string "Host filename for the first simulated device" | |
502 | depends on BLK_DEV_SIMDISK = y | |
503 | default "" | |
504 | help | |
505 | Attach a first simdisk to a host file. Conventionally, this file | |
506 | contains a root file system. | |
507 | ||
508 | config SIMDISK1_FILENAME | |
509 | string "Host filename for the second simulated device" | |
510 | depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 | |
511 | default "" | |
512 | help | |
513 | Another simulated disk in a host file for a buildroot-independent | |
514 | storage. | |
515 | ||
4949009e MF |
516 | config XTFPGA_LCD |
517 | bool "Enable XTFPGA LCD driver" | |
518 | depends on XTENSA_PLATFORM_XTFPGA | |
519 | default n | |
520 | help | |
521 | There's a 2x16 LCD on most of XTFPGA boards, kernel may output | |
522 | progress messages there during bootup/shutdown. It may be useful | |
523 | during board bringup. | |
524 | ||
525 | If unsure, say N. | |
526 | ||
527 | config XTFPGA_LCD_BASE_ADDR | |
528 | hex "XTFPGA LCD base address" | |
529 | depends on XTFPGA_LCD | |
530 | default "0x0d0c0000" | |
531 | help | |
532 | Base address of the LCD controller inside KIO region. | |
533 | Different boards from XTFPGA family have LCD controller at different | |
534 | addresses. Please consult prototyping user guide for your board for | |
535 | the correct address. Wrong address here may lead to hardware lockup. | |
536 | ||
537 | config XTFPGA_LCD_8BIT_ACCESS | |
538 | bool "Use 8-bit access to XTFPGA LCD" | |
539 | depends on XTFPGA_LCD | |
540 | default n | |
541 | help | |
542 | LCD may be connected with 4- or 8-bit interface, 8-bit access may | |
543 | only be used with 8-bit interface. Please consult prototyping user | |
544 | guide for your board for the correct interface width. | |
545 | ||
76743c0e MF |
546 | comment "Kernel memory layout" |
547 | ||
548 | config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX | |
549 | bool "Initialize Xtensa MMU inside the Linux kernel code" | |
550 | depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B | |
551 | default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM | |
552 | help | |
553 | Earlier version initialized the MMU in the exception vector | |
554 | before jumping to _startup in head.S and had an advantage that | |
555 | it was possible to place a software breakpoint at 'reset' and | |
556 | then enter your normal kernel breakpoints once the MMU was mapped | |
557 | to the kernel mappings (0XC0000000). | |
558 | ||
8a128bc3 | 559 | This unfortunately won't work for U-Boot and likely also won't |
76743c0e MF |
560 | work for using KEXEC to have a hot kernel ready for doing a |
561 | KDUMP. | |
562 | ||
563 | So now the MMU is initialized in head.S but it's necessary to | |
564 | use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. | |
565 | xt-gdb can't place a Software Breakpoint in the 0XD region prior | |
566 | to mapping the MMU and after mapping even if the area of low memory | |
567 | was mapped gdb wouldn't remove the breakpoint on hitting it as the | |
568 | PC wouldn't match. Since Hardware Breakpoints are recommended for | |
569 | Linux configurations it seems reasonable to just assume they exist | |
570 | and leave this older mechanism for unfortunate souls that choose | |
571 | not to follow Tensilica's recommendation. | |
572 | ||
573 | Selecting this will cause U-Boot to set the KERNEL Load and Entry | |
574 | address at 0x00003000 instead of the mapped std of 0xD0003000. | |
575 | ||
576 | If in doubt, say Y. | |
577 | ||
7af710d9 MF |
578 | config XIP_KERNEL |
579 | bool "Kernel Execute-In-Place from ROM" | |
580 | depends on PLATFORM_HAVE_XIP | |
581 | help | |
582 | Execute-In-Place allows the kernel to run from non-volatile storage | |
583 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
584 | space since the text section of the kernel is not loaded from flash | |
585 | to RAM. Read-write sections, such as the data section and stack, | |
586 | are still copied to RAM. The XIP kernel is not compressed since | |
587 | it has to run directly from flash, so it will take more space to | |
588 | store it. The flash address used to link the kernel object files, | |
589 | and for storing it, is configuration dependent. Therefore, if you | |
590 | say Y here, you must know the proper physical address where to | |
591 | store the kernel image depending on your own flash memory usage. | |
592 | ||
593 | Also note that the make target becomes "make xipImage" rather than | |
594 | "make Image" or "make uImage". The final kernel binary to put in | |
595 | ROM memory will be arch/xtensa/boot/xipImage. | |
596 | ||
597 | If unsure, say N. | |
598 | ||
76743c0e MF |
599 | config MEMMAP_CACHEATTR |
600 | hex "Cache attributes for the memory address space" | |
601 | depends on !MMU | |
602 | default 0x22222222 | |
603 | help | |
604 | These cache attributes are set up for noMMU systems. Each hex digit | |
605 | specifies cache attributes for the corresponding 512MB memory | |
606 | region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, | |
607 | bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. | |
608 | ||
609 | Cache attribute values are specific for the MMU type. | |
610 | For region protection MMUs: | |
611 | 1: WT cached, | |
612 | 2: cache bypass, | |
613 | 4: WB cached, | |
614 | f: illegal. | |
2a9b29b2 | 615 | For full MMU: |
76743c0e MF |
616 | bit 0: executable, |
617 | bit 1: writable, | |
618 | bits 2..3: | |
619 | 0: cache bypass, | |
620 | 1: WB cache, | |
621 | 2: WT cache, | |
622 | 3: special (c and e are illegal, f is reserved). | |
623 | For MPU: | |
624 | 0: illegal, | |
625 | 1: WB cache, | |
626 | 2: WB, no-write-allocate cache, | |
627 | 3: WT cache, | |
628 | 4: cache bypass. | |
629 | ||
630 | config KSEG_PADDR | |
631 | hex "Physical address of the KSEG mapping" | |
632 | depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU | |
633 | default 0x00000000 | |
634 | help | |
635 | This is the physical address where KSEG is mapped. Please refer to | |
636 | the chosen KSEG layout help for the required address alignment. | |
637 | Unpacked kernel image (including vectors) must be located completely | |
638 | within KSEG. | |
639 | Physical memory below this address is not available to linux. | |
640 | ||
641 | If unsure, leave the default value here. | |
642 | ||
7af710d9 MF |
643 | config KERNEL_VIRTUAL_ADDRESS |
644 | hex "Kernel virtual address" | |
645 | depends on MMU && XIP_KERNEL | |
646 | default 0xd0003000 | |
647 | help | |
648 | This is the virtual address where the XIP kernel is mapped. | |
649 | XIP kernel may be mapped into KSEG or KIO region, virtual address | |
650 | provided here must match kernel load address provided in | |
651 | KERNEL_LOAD_ADDRESS. | |
652 | ||
76743c0e MF |
653 | config KERNEL_LOAD_ADDRESS |
654 | hex "Kernel load address" | |
655 | default 0x60003000 if !MMU | |
656 | default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX | |
657 | default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX | |
658 | help | |
659 | This is the address where the kernel is loaded. | |
660 | It is virtual address for MMUv2 configurations and physical address | |
661 | for all other configurations. | |
662 | ||
663 | If unsure, leave the default value here. | |
664 | ||
5e4417f9 MF |
665 | choice |
666 | prompt "Relocatable vectors location" | |
667 | default XTENSA_VECTORS_IN_TEXT | |
76743c0e | 668 | help |
5e4417f9 MF |
669 | Choose whether relocatable vectors are merged into the kernel .text |
670 | or placed separately at runtime. This option does not affect | |
671 | configurations without VECBASE register where vectors are always | |
672 | placed at their hardware-defined locations. | |
76743c0e | 673 | |
5e4417f9 MF |
674 | config XTENSA_VECTORS_IN_TEXT |
675 | bool "Merge relocatable vectors into kernel text" | |
676 | depends on !MTD_XIP | |
677 | help | |
678 | This option puts relocatable vectors into the kernel .text section | |
679 | with proper alignment. | |
680 | This is a safe choice for most configurations. | |
681 | ||
682 | config XTENSA_VECTORS_SEPARATE | |
683 | bool "Put relocatable vectors at fixed address" | |
684 | help | |
685 | This option puts relocatable vectors at specific virtual address. | |
686 | Vectors are merged with the .init data in the kernel image and | |
687 | are copied into their designated location during kernel startup. | |
688 | Use it to put vectors into IRAM or out of FLASH on kernels with | |
689 | XIP-aware MTD support. | |
690 | ||
691 | endchoice | |
692 | ||
693 | config VECTORS_ADDR | |
694 | hex "Kernel vectors virtual address" | |
695 | default 0x00000000 | |
696 | depends on XTENSA_VECTORS_SEPARATE | |
697 | help | |
698 | This is the virtual address of the (relocatable) vectors base. | |
699 | It must be within KSEG if MMU is used. | |
76743c0e | 700 | |
7af710d9 MF |
701 | config XIP_DATA_ADDR |
702 | hex "XIP kernel data virtual address" | |
703 | depends on XIP_KERNEL | |
704 | default 0x00000000 | |
705 | help | |
706 | This is the virtual address where XIP kernel data is copied. | |
707 | It must be within KSEG if MMU is used. | |
708 | ||
76743c0e MF |
709 | config PLATFORM_WANT_DEFAULT_MEM |
710 | def_bool n | |
711 | ||
712 | config DEFAULT_MEM_START | |
713 | hex | |
714 | prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM | |
715 | default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM | |
716 | default 0x00000000 | |
717 | help | |
718 | This is the base address used for both PAGE_OFFSET and PHYS_OFFSET | |
719 | in noMMU configurations. | |
720 | ||
721 | If unsure, leave the default value here. | |
722 | ||
723 | choice | |
724 | prompt "KSEG layout" | |
725 | depends on MMU | |
726 | default XTENSA_KSEG_MMU_V2 | |
727 | ||
728 | config XTENSA_KSEG_MMU_V2 | |
729 | bool "MMUv2: 128MB cached + 128MB uncached" | |
730 | help | |
731 | MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting | |
732 | at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 | |
733 | without cache. | |
734 | KSEG_PADDR must be aligned to 128MB. | |
735 | ||
736 | config XTENSA_KSEG_256M | |
737 | bool "256MB cached + 256MB uncached" | |
738 | depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX | |
739 | help | |
740 | TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 | |
741 | with cache and to 0xc0000000 without cache. | |
742 | KSEG_PADDR must be aligned to 256MB. | |
743 | ||
744 | config XTENSA_KSEG_512M | |
745 | bool "512MB cached + 512MB uncached" | |
746 | depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX | |
747 | help | |
748 | TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 | |
749 | with cache and to 0xc0000000 without cache. | |
750 | KSEG_PADDR must be aligned to 256MB. | |
751 | ||
752 | endchoice | |
753 | ||
754 | config HIGHMEM | |
755 | bool "High Memory Support" | |
756 | depends on MMU | |
629ed3f7 | 757 | select KMAP_LOCAL |
76743c0e MF |
758 | help |
759 | Linux can use the full amount of RAM in the system by | |
760 | default. However, the default MMUv2 setup only maps the | |
761 | lowermost 128 MB of memory linearly to the areas starting | |
762 | at 0xd0000000 (cached) and 0xd8000000 (uncached). | |
763 | When there are more than 128 MB memory in the system not | |
764 | all of it can be "permanently mapped" by the kernel. | |
765 | The physical memory that's not permanently mapped is called | |
766 | "high memory". | |
767 | ||
768 | If you are compiling a kernel which will never run on a | |
769 | machine with more than 128 MB total physical RAM, answer | |
770 | N here. | |
771 | ||
772 | If unsure, say Y. | |
773 | ||
0192445c | 774 | config ARCH_FORCE_MAX_ORDER |
76743c0e MF |
775 | int "Maximum zone order" |
776 | default "11" | |
777 | help | |
778 | The kernel memory allocator divides physically contiguous memory | |
779 | blocks into "zones", where each zone is a power of two number of | |
780 | pages. This option selects the largest power of two that the kernel | |
781 | keeps in the memory allocator. If you need to allocate very large | |
782 | blocks of physically contiguous memory, then you may need to | |
783 | increase this value. | |
784 | ||
785 | This config option is actually maximum order plus one. For example, | |
786 | a value of 11 means that the largest free memory block is 2^10 pages. | |
787 | ||
8e1a6dd2 CZ |
788 | endmenu |
789 | ||
e00d8b2f MF |
790 | menu "Power management options" |
791 | ||
733f5c28 MF |
792 | config ARCH_HIBERNATION_POSSIBLE |
793 | def_bool y | |
794 | ||
e00d8b2f MF |
795 | source "kernel/power/Kconfig" |
796 | ||
797 | endmenu |