Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/config.h> |
42 | #include <linux/init.h> | |
43 | ||
44 | #include <linux/mm.h> | |
45 | #include <linux/kernel_stat.h> | |
46 | #include <linux/smp_lock.h> | |
1da177e4 LT |
47 | #include <linux/bootmem.h> |
48 | #include <linux/thread_info.h> | |
49 | #include <linux/module.h> | |
50 | ||
51 | #include <linux/delay.h> | |
52 | #include <linux/mc146818rtc.h> | |
53 | #include <asm/mtrr.h> | |
54 | #include <asm/pgalloc.h> | |
55 | #include <asm/desc.h> | |
56 | #include <asm/kdebug.h> | |
57 | #include <asm/tlbflush.h> | |
58 | #include <asm/proto.h> | |
75152114 | 59 | #include <asm/nmi.h> |
9cdd304b AV |
60 | #include <asm/irq.h> |
61 | #include <asm/hw_irq.h> | |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
65 | /* Package ID of each logical CPU */ | |
6c231b7b | 66 | u8 phys_proc_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
94605eff | 67 | /* core ID of each logical CPU */ |
6c231b7b | 68 | u8 cpu_core_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
69 | |
70 | /* Bitmask of currently online CPUs */ | |
6c231b7b | 71 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 72 | |
a8ab26fe AK |
73 | EXPORT_SYMBOL(cpu_online_map); |
74 | ||
75 | /* | |
76 | * Private maps to synchronize booting between AP and BP. | |
77 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
78 | */ | |
1da177e4 LT |
79 | cpumask_t cpu_callin_map; |
80 | cpumask_t cpu_callout_map; | |
a8ab26fe AK |
81 | |
82 | cpumask_t cpu_possible_map; | |
83 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
84 | |
85 | /* Per CPU bogomips and other parameters */ | |
86 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
87 | ||
a8ab26fe AK |
88 | /* Set when the idlers are all forked */ |
89 | int smp_threads_ready; | |
90 | ||
94605eff | 91 | /* representing HT siblings of each logical CPU */ |
6c231b7b | 92 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
94605eff SS |
93 | |
94 | /* representing HT and core siblings of each logical CPU */ | |
6c231b7b | 95 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
2df9fa36 | 96 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
97 | |
98 | /* | |
99 | * Trampoline 80x86 program as an array. | |
100 | */ | |
101 | ||
a8ab26fe AK |
102 | extern unsigned char trampoline_data[]; |
103 | extern unsigned char trampoline_end[]; | |
1da177e4 | 104 | |
76e4f660 AR |
105 | /* State of each CPU */ |
106 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
107 | ||
108 | /* | |
109 | * Store all idle threads, this can be reused instead of creating | |
110 | * a new thread. Also avoids complicated thread destroy functionality | |
111 | * for idle threads. | |
112 | */ | |
113 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
114 | ||
115 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
116 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Currently trivial. Write the real->protected mode | |
120 | * bootstrap into the page concerned. The caller | |
121 | * has made sure it's suitably aligned. | |
122 | */ | |
123 | ||
a8ab26fe | 124 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
125 | { |
126 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
127 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
128 | return virt_to_phys(tramp); | |
129 | } | |
130 | ||
131 | /* | |
132 | * The bootstrap kernel entry code has set these up. Save them for | |
133 | * a given CPU | |
134 | */ | |
135 | ||
a8ab26fe | 136 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
137 | { |
138 | struct cpuinfo_x86 *c = cpu_data + id; | |
139 | ||
140 | *c = boot_cpu_data; | |
141 | identify_cpu(c); | |
dda50e71 | 142 | print_cpu_info(c); |
1da177e4 LT |
143 | } |
144 | ||
145 | /* | |
dda50e71 AK |
146 | * New Funky TSC sync algorithm borrowed from IA64. |
147 | * Main advantage is that it doesn't reset the TSCs fully and | |
148 | * in general looks more robust and it works better than my earlier | |
149 | * attempts. I believe it was written by David Mosberger. Some minor | |
150 | * adjustments for x86-64 by me -AK | |
1da177e4 | 151 | * |
dda50e71 AK |
152 | * Original comment reproduced below. |
153 | * | |
154 | * Synchronize TSC of the current (slave) CPU with the TSC of the | |
155 | * MASTER CPU (normally the time-keeper CPU). We use a closed loop to | |
156 | * eliminate the possibility of unaccounted-for errors (such as | |
157 | * getting a machine check in the middle of a calibration step). The | |
158 | * basic idea is for the slave to ask the master what itc value it has | |
159 | * and to read its own itc before and after the master responds. Each | |
160 | * iteration gives us three timestamps: | |
161 | * | |
162 | * slave master | |
163 | * | |
164 | * t0 ---\ | |
165 | * ---\ | |
166 | * ---> | |
167 | * tm | |
168 | * /--- | |
169 | * /--- | |
170 | * t1 <--- | |
171 | * | |
172 | * | |
173 | * The goal is to adjust the slave's TSC such that tm falls exactly | |
174 | * half-way between t0 and t1. If we achieve this, the clocks are | |
175 | * synchronized provided the interconnect between the slave and the | |
176 | * master is symmetric. Even if the interconnect were asymmetric, we | |
177 | * would still know that the synchronization error is smaller than the | |
178 | * roundtrip latency (t0 - t1). | |
179 | * | |
180 | * When the interconnect is quiet and symmetric, this lets us | |
181 | * synchronize the TSC to within one or two cycles. However, we can | |
182 | * only *guarantee* that the synchronization is accurate to within a | |
183 | * round-trip time, which is typically in the range of several hundred | |
184 | * cycles (e.g., ~500 cycles). In practice, this means that the TSCs | |
185 | * are usually almost perfectly synchronized, but we shouldn't assume | |
186 | * that the accuracy is much better than half a micro second or so. | |
187 | * | |
188 | * [there are other errors like the latency of RDTSC and of the | |
189 | * WRMSR. These can also account to hundreds of cycles. So it's | |
190 | * probably worse. It claims 153 cycles error on a dual Opteron, | |
191 | * but I suspect the numbers are actually somewhat worse -AK] | |
1da177e4 LT |
192 | */ |
193 | ||
dda50e71 AK |
194 | #define MASTER 0 |
195 | #define SLAVE (SMP_CACHE_BYTES/8) | |
196 | ||
197 | /* Intentionally don't use cpu_relax() while TSC synchronization | |
198 | because we don't want to go into funky power save modi or cause | |
199 | hypervisors to schedule us away. Going to sleep would likely affect | |
200 | latency and low latency is the primary objective here. -AK */ | |
201 | #define no_cpu_relax() barrier() | |
202 | ||
a8ab26fe | 203 | static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock); |
dda50e71 AK |
204 | static volatile __cpuinitdata unsigned long go[SLAVE + 1]; |
205 | static int notscsync __cpuinitdata; | |
206 | ||
207 | #undef DEBUG_TSC_SYNC | |
1da177e4 | 208 | |
dda50e71 AK |
209 | #define NUM_ROUNDS 64 /* magic value */ |
210 | #define NUM_ITERS 5 /* likewise */ | |
1da177e4 | 211 | |
dda50e71 AK |
212 | /* Callback on boot CPU */ |
213 | static __cpuinit void sync_master(void *arg) | |
1da177e4 | 214 | { |
dda50e71 AK |
215 | unsigned long flags, i; |
216 | ||
dda50e71 AK |
217 | go[MASTER] = 0; |
218 | ||
219 | local_irq_save(flags); | |
220 | { | |
221 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) { | |
222 | while (!go[MASTER]) | |
223 | no_cpu_relax(); | |
224 | go[MASTER] = 0; | |
225 | rdtscll(go[SLAVE]); | |
226 | } | |
227 | } | |
228 | local_irq_restore(flags); | |
a8ab26fe | 229 | } |
1da177e4 | 230 | |
a8ab26fe | 231 | /* |
dda50e71 AK |
232 | * Return the number of cycles by which our tsc differs from the tsc |
233 | * on the master (time-keeper) CPU. A positive number indicates our | |
234 | * tsc is ahead of the master, negative that it is behind. | |
a8ab26fe | 235 | */ |
dda50e71 AK |
236 | static inline long |
237 | get_delta(long *rt, long *master) | |
a8ab26fe | 238 | { |
dda50e71 AK |
239 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; |
240 | unsigned long tcenter, t0, t1, tm; | |
241 | int i; | |
a8ab26fe | 242 | |
dda50e71 AK |
243 | for (i = 0; i < NUM_ITERS; ++i) { |
244 | rdtscll(t0); | |
245 | go[MASTER] = 1; | |
246 | while (!(tm = go[SLAVE])) | |
247 | no_cpu_relax(); | |
248 | go[SLAVE] = 0; | |
249 | rdtscll(t1); | |
250 | ||
251 | if (t1 - t0 < best_t1 - best_t0) | |
252 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
253 | } | |
254 | ||
255 | *rt = best_t1 - best_t0; | |
256 | *master = best_tm - best_t0; | |
257 | ||
258 | /* average best_t0 and best_t1 without overflow: */ | |
259 | tcenter = (best_t0/2 + best_t1/2); | |
260 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
261 | ++tcenter; | |
262 | return tcenter - best_tm; | |
1da177e4 LT |
263 | } |
264 | ||
3d483f47 | 265 | static __cpuinit void sync_tsc(unsigned int master) |
1da177e4 | 266 | { |
dda50e71 AK |
267 | int i, done = 0; |
268 | long delta, adj, adjust_latency = 0; | |
269 | unsigned long flags, rt, master_time_stamp, bound; | |
44456d37 | 270 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
271 | static struct syncdebug { |
272 | long rt; /* roundtrip time */ | |
273 | long master; /* master's timestamp */ | |
274 | long diff; /* difference between midpoint and master's timestamp */ | |
275 | long lat; /* estimate of tsc adjustment latency */ | |
276 | } t[NUM_ROUNDS] __cpuinitdata; | |
277 | #endif | |
278 | ||
3d483f47 EB |
279 | printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", |
280 | smp_processor_id(), master); | |
281 | ||
dda50e71 AK |
282 | go[MASTER] = 1; |
283 | ||
3d483f47 EB |
284 | /* It is dangerous to broadcast IPI as cpus are coming up, |
285 | * as they may not be ready to accept them. So since | |
286 | * we only need to send the ipi to the boot cpu direct | |
287 | * the message, and avoid the race. | |
288 | */ | |
289 | smp_call_function_single(master, sync_master, NULL, 1, 0); | |
dda50e71 AK |
290 | |
291 | while (go[MASTER]) /* wait for master to be ready */ | |
292 | no_cpu_relax(); | |
293 | ||
294 | spin_lock_irqsave(&tsc_sync_lock, flags); | |
295 | { | |
296 | for (i = 0; i < NUM_ROUNDS; ++i) { | |
297 | delta = get_delta(&rt, &master_time_stamp); | |
298 | if (delta == 0) { | |
299 | done = 1; /* let's lock on to this... */ | |
300 | bound = rt; | |
301 | } | |
302 | ||
303 | if (!done) { | |
304 | unsigned long t; | |
305 | if (i > 0) { | |
306 | adjust_latency += -delta; | |
307 | adj = -delta + adjust_latency/4; | |
308 | } else | |
309 | adj = -delta; | |
310 | ||
311 | rdtscll(t); | |
312 | wrmsrl(MSR_IA32_TSC, t + adj); | |
313 | } | |
44456d37 | 314 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
315 | t[i].rt = rt; |
316 | t[i].master = master_time_stamp; | |
317 | t[i].diff = delta; | |
318 | t[i].lat = adjust_latency/4; | |
319 | #endif | |
320 | } | |
321 | } | |
322 | spin_unlock_irqrestore(&tsc_sync_lock, flags); | |
323 | ||
44456d37 | 324 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
325 | for (i = 0; i < NUM_ROUNDS; ++i) |
326 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
327 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
328 | #endif | |
329 | ||
330 | printk(KERN_INFO | |
331 | "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, " | |
332 | "maxerr %lu cycles)\n", | |
3d483f47 | 333 | smp_processor_id(), master, delta, rt); |
a8ab26fe | 334 | } |
1da177e4 | 335 | |
dda50e71 | 336 | static void __cpuinit tsc_sync_wait(void) |
a8ab26fe | 337 | { |
dda50e71 | 338 | if (notscsync || !cpu_has_tsc) |
a8ab26fe | 339 | return; |
349188f6 | 340 | sync_tsc(0); |
a8ab26fe | 341 | } |
1da177e4 | 342 | |
dda50e71 | 343 | static __init int notscsync_setup(char *s) |
a8ab26fe | 344 | { |
dda50e71 AK |
345 | notscsync = 1; |
346 | return 0; | |
1da177e4 | 347 | } |
dda50e71 | 348 | __setup("notscsync", notscsync_setup); |
1da177e4 | 349 | |
a8ab26fe | 350 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 351 | |
a8ab26fe AK |
352 | /* |
353 | * Report back to the Boot Processor. | |
354 | * Running on AP. | |
355 | */ | |
356 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
357 | { |
358 | int cpuid, phys_id; | |
359 | unsigned long timeout; | |
360 | ||
361 | /* | |
362 | * If waken up by an INIT in an 82489DX configuration | |
363 | * we may get here before an INIT-deassert IPI reaches | |
364 | * our local APIC. We have to wait for the IPI or we'll | |
365 | * lock up on an APIC access. | |
366 | */ | |
a8ab26fe AK |
367 | while (!atomic_read(&init_deasserted)) |
368 | cpu_relax(); | |
1da177e4 LT |
369 | |
370 | /* | |
371 | * (This works even if the APIC is not enabled.) | |
372 | */ | |
373 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
374 | cpuid = smp_processor_id(); | |
375 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
376 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
377 | phys_id, cpuid); | |
378 | } | |
379 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
380 | ||
381 | /* | |
382 | * STARTUP IPIs are fragile beasts as they might sometimes | |
383 | * trigger some glue motherboard logic. Complete APIC bus | |
384 | * silence for 1 second, this overestimates the time the | |
385 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
386 | * by a factor of two. This should be enough. | |
387 | */ | |
388 | ||
389 | /* | |
390 | * Waiting 2s total for startup (udelay is not yet working) | |
391 | */ | |
392 | timeout = jiffies + 2*HZ; | |
393 | while (time_before(jiffies, timeout)) { | |
394 | /* | |
395 | * Has the boot CPU finished it's STARTUP sequence? | |
396 | */ | |
397 | if (cpu_isset(cpuid, cpu_callout_map)) | |
398 | break; | |
a8ab26fe | 399 | cpu_relax(); |
1da177e4 LT |
400 | } |
401 | ||
402 | if (!time_before(jiffies, timeout)) { | |
403 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
404 | cpuid); | |
405 | } | |
406 | ||
407 | /* | |
408 | * the boot CPU has finished the init stage and is spinning | |
409 | * on callin_map until we finish. We are free to set up this | |
410 | * CPU, first the APIC. (this is probably redundant on most | |
411 | * boards) | |
412 | */ | |
413 | ||
414 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
415 | setup_local_APIC(); | |
416 | ||
1da177e4 LT |
417 | /* |
418 | * Get our bogomips. | |
b4452218 AK |
419 | * |
420 | * Need to enable IRQs because it can take longer and then | |
421 | * the NMI watchdog might kill us. | |
1da177e4 | 422 | */ |
b4452218 | 423 | local_irq_enable(); |
1da177e4 | 424 | calibrate_delay(); |
b4452218 | 425 | local_irq_disable(); |
1da177e4 LT |
426 | Dprintk("Stack at about %p\n",&cpuid); |
427 | ||
428 | disable_APIC_timer(); | |
429 | ||
430 | /* | |
431 | * Save our processor parameters | |
432 | */ | |
433 | smp_store_cpu_info(cpuid); | |
434 | ||
1da177e4 LT |
435 | /* |
436 | * Allow the master to continue. | |
437 | */ | |
438 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
439 | } |
440 | ||
94605eff SS |
441 | /* representing cpus for which sibling maps can be computed */ |
442 | static cpumask_t cpu_sibling_setup_map; | |
443 | ||
cb0cd8d4 AR |
444 | static inline void set_cpu_sibling_map(int cpu) |
445 | { | |
446 | int i; | |
94605eff SS |
447 | struct cpuinfo_x86 *c = cpu_data; |
448 | ||
449 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
450 | |
451 | if (smp_num_siblings > 1) { | |
94605eff SS |
452 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
453 | if (phys_proc_id[cpu] == phys_proc_id[i] && | |
454 | cpu_core_id[cpu] == cpu_core_id[i]) { | |
cb0cd8d4 AR |
455 | cpu_set(i, cpu_sibling_map[cpu]); |
456 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
457 | cpu_set(i, cpu_core_map[cpu]); |
458 | cpu_set(cpu, cpu_core_map[i]); | |
cb0cd8d4 AR |
459 | } |
460 | } | |
461 | } else { | |
462 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
463 | } | |
464 | ||
94605eff | 465 | if (current_cpu_data.x86_max_cores == 1) { |
cb0cd8d4 | 466 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
467 | c[cpu].booted_cores = 1; |
468 | return; | |
469 | } | |
470 | ||
471 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
472 | if (phys_proc_id[cpu] == phys_proc_id[i]) { | |
473 | cpu_set(i, cpu_core_map[cpu]); | |
474 | cpu_set(cpu, cpu_core_map[i]); | |
475 | /* | |
476 | * Does this new cpu bringup a new core? | |
477 | */ | |
478 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
479 | /* | |
480 | * for each core in package, increment | |
481 | * the booted_cores for this new cpu | |
482 | */ | |
483 | if (first_cpu(cpu_sibling_map[i]) == i) | |
484 | c[cpu].booted_cores++; | |
485 | /* | |
486 | * increment the core count for all | |
487 | * the other cpus in this package | |
488 | */ | |
489 | if (i != cpu) | |
490 | c[i].booted_cores++; | |
491 | } else if (i != cpu && !c[cpu].booted_cores) | |
492 | c[cpu].booted_cores = c[i].booted_cores; | |
493 | } | |
cb0cd8d4 AR |
494 | } |
495 | } | |
496 | ||
1da177e4 | 497 | /* |
a8ab26fe | 498 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 499 | */ |
a8ab26fe | 500 | void __cpuinit start_secondary(void) |
1da177e4 LT |
501 | { |
502 | /* | |
503 | * Dont put anything before smp_callin(), SMP | |
504 | * booting is too fragile that we want to limit the | |
505 | * things done here to the most necessary things. | |
506 | */ | |
507 | cpu_init(); | |
5bfb5d69 | 508 | preempt_disable(); |
1da177e4 LT |
509 | smp_callin(); |
510 | ||
511 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
512 | barrier(); | |
513 | ||
1da177e4 LT |
514 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
515 | setup_secondary_APIC_clock(); | |
516 | ||
a8ab26fe | 517 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
518 | |
519 | if (nmi_watchdog == NMI_IO_APIC) { | |
520 | disable_8259A_irq(0); | |
521 | enable_NMI_through_LVT0(NULL); | |
522 | enable_8259A_irq(0); | |
523 | } | |
524 | ||
a8ab26fe | 525 | enable_APIC_timer(); |
1da177e4 | 526 | |
cb0cd8d4 AR |
527 | /* |
528 | * The sibling maps must be set before turing the online map on for | |
529 | * this cpu | |
530 | */ | |
531 | set_cpu_sibling_map(smp_processor_id()); | |
532 | ||
1eecd73c AK |
533 | /* |
534 | * Wait for TSC sync to not schedule things before. | |
535 | * We still process interrupts, which could see an inconsistent | |
536 | * time in that window unfortunately. | |
537 | * Do this here because TSC sync has global unprotected state. | |
538 | */ | |
539 | tsc_sync_wait(); | |
540 | ||
884d9e40 AR |
541 | /* |
542 | * We need to hold call_lock, so there is no inconsistency | |
543 | * between the time smp_call_function() determines number of | |
544 | * IPI receipients, and the time when the determination is made | |
545 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
546 | * lock helps us to not include this cpu in a currently in progress | |
547 | * smp_call_function(). | |
548 | */ | |
549 | lock_ipi_call_lock(); | |
550 | ||
1da177e4 | 551 | /* |
a8ab26fe | 552 | * Allow the master to continue. |
1da177e4 | 553 | */ |
1da177e4 | 554 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 AR |
555 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
556 | unlock_ipi_call_lock(); | |
557 | ||
1da177e4 LT |
558 | cpu_idle(); |
559 | } | |
560 | ||
a8ab26fe | 561 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
562 | extern void (*initial_code)(void); |
563 | ||
44456d37 | 564 | #ifdef APIC_DEBUG |
a8ab26fe | 565 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
566 | { |
567 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
568 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
569 | int timeout, status; | |
570 | ||
571 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
572 | ||
573 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
574 | printk("... APIC #%d %s: ", apicid, names[i]); | |
575 | ||
576 | /* | |
577 | * Wait for idle. | |
578 | */ | |
579 | apic_wait_icr_idle(); | |
580 | ||
c1507eb2 AK |
581 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
582 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
583 | |
584 | timeout = 0; | |
585 | do { | |
586 | udelay(100); | |
587 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
588 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
589 | ||
590 | switch (status) { | |
591 | case APIC_ICR_RR_VALID: | |
592 | status = apic_read(APIC_RRR); | |
593 | printk("%08x\n", status); | |
594 | break; | |
595 | default: | |
596 | printk("failed\n"); | |
597 | } | |
598 | } | |
599 | } | |
600 | #endif | |
601 | ||
a8ab26fe AK |
602 | /* |
603 | * Kick the secondary to wake up. | |
604 | */ | |
605 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 LT |
606 | { |
607 | unsigned long send_status = 0, accept_status = 0; | |
608 | int maxlvt, timeout, num_starts, j; | |
609 | ||
610 | Dprintk("Asserting INIT.\n"); | |
611 | ||
612 | /* | |
613 | * Turn INIT on target chip | |
614 | */ | |
c1507eb2 | 615 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
616 | |
617 | /* | |
618 | * Send IPI | |
619 | */ | |
c1507eb2 | 620 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
621 | | APIC_DM_INIT); |
622 | ||
623 | Dprintk("Waiting for send to finish...\n"); | |
624 | timeout = 0; | |
625 | do { | |
626 | Dprintk("+"); | |
627 | udelay(100); | |
628 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
629 | } while (send_status && (timeout++ < 1000)); | |
630 | ||
631 | mdelay(10); | |
632 | ||
633 | Dprintk("Deasserting INIT.\n"); | |
634 | ||
635 | /* Target chip */ | |
c1507eb2 | 636 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
637 | |
638 | /* Send IPI */ | |
c1507eb2 | 639 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
640 | |
641 | Dprintk("Waiting for send to finish...\n"); | |
642 | timeout = 0; | |
643 | do { | |
644 | Dprintk("+"); | |
645 | udelay(100); | |
646 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
647 | } while (send_status && (timeout++ < 1000)); | |
648 | ||
f2ecfab9 | 649 | mb(); |
1da177e4 LT |
650 | atomic_set(&init_deasserted, 1); |
651 | ||
5a40b7c2 | 652 | num_starts = 2; |
1da177e4 LT |
653 | |
654 | /* | |
655 | * Run STARTUP IPI loop. | |
656 | */ | |
657 | Dprintk("#startup loops: %d.\n", num_starts); | |
658 | ||
659 | maxlvt = get_maxlvt(); | |
660 | ||
661 | for (j = 1; j <= num_starts; j++) { | |
662 | Dprintk("Sending STARTUP #%d.\n",j); | |
663 | apic_read_around(APIC_SPIV); | |
664 | apic_write(APIC_ESR, 0); | |
665 | apic_read(APIC_ESR); | |
666 | Dprintk("After apic_write.\n"); | |
667 | ||
668 | /* | |
669 | * STARTUP IPI | |
670 | */ | |
671 | ||
672 | /* Target chip */ | |
c1507eb2 | 673 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
674 | |
675 | /* Boot on the stack */ | |
676 | /* Kick the second */ | |
c1507eb2 | 677 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
678 | |
679 | /* | |
680 | * Give the other CPU some time to accept the IPI. | |
681 | */ | |
682 | udelay(300); | |
683 | ||
684 | Dprintk("Startup point 1.\n"); | |
685 | ||
686 | Dprintk("Waiting for send to finish...\n"); | |
687 | timeout = 0; | |
688 | do { | |
689 | Dprintk("+"); | |
690 | udelay(100); | |
691 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
692 | } while (send_status && (timeout++ < 1000)); | |
693 | ||
694 | /* | |
695 | * Give the other CPU some time to accept the IPI. | |
696 | */ | |
697 | udelay(200); | |
698 | /* | |
699 | * Due to the Pentium erratum 3AP. | |
700 | */ | |
701 | if (maxlvt > 3) { | |
702 | apic_read_around(APIC_SPIV); | |
703 | apic_write(APIC_ESR, 0); | |
704 | } | |
705 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
706 | if (send_status || accept_status) | |
707 | break; | |
708 | } | |
709 | Dprintk("After Startup.\n"); | |
710 | ||
711 | if (send_status) | |
712 | printk(KERN_ERR "APIC never delivered???\n"); | |
713 | if (accept_status) | |
714 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
715 | ||
716 | return (send_status | accept_status); | |
717 | } | |
718 | ||
76e4f660 AR |
719 | struct create_idle { |
720 | struct task_struct *idle; | |
721 | struct completion done; | |
722 | int cpu; | |
723 | }; | |
724 | ||
725 | void do_fork_idle(void *_c_idle) | |
726 | { | |
727 | struct create_idle *c_idle = _c_idle; | |
728 | ||
729 | c_idle->idle = fork_idle(c_idle->cpu); | |
730 | complete(&c_idle->done); | |
731 | } | |
732 | ||
a8ab26fe AK |
733 | /* |
734 | * Boot one CPU. | |
735 | */ | |
736 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 737 | { |
1da177e4 | 738 | unsigned long boot_error; |
a8ab26fe | 739 | int timeout; |
1da177e4 | 740 | unsigned long start_rip; |
76e4f660 AR |
741 | struct create_idle c_idle = { |
742 | .cpu = cpu, | |
743 | .done = COMPLETION_INITIALIZER(c_idle.done), | |
744 | }; | |
745 | DECLARE_WORK(work, do_fork_idle, &c_idle); | |
746 | ||
747 | c_idle.idle = get_idle_for_cpu(cpu); | |
748 | ||
749 | if (c_idle.idle) { | |
750 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
751 | (THREAD_SIZE + (unsigned long) c_idle.idle->thread_info)) - 1); | |
752 | init_idle(c_idle.idle, cpu); | |
753 | goto do_rest; | |
754 | } | |
755 | ||
1da177e4 | 756 | /* |
76e4f660 AR |
757 | * During cold boot process, keventd thread is not spun up yet. |
758 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
759 | * not acquire any attributes from the calling context. Hence the clean | |
760 | * way to create kernel_threads() is to do that from keventd(). | |
761 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
762 | * was also queuing to keventd() and when the caller is already running | |
763 | * in context of keventd(), we would end up with locking up the keventd | |
764 | * thread. | |
1da177e4 | 765 | */ |
76e4f660 AR |
766 | if (!keventd_up() || current_is_keventd()) |
767 | work.func(work.data); | |
768 | else { | |
769 | schedule_work(&work); | |
770 | wait_for_completion(&c_idle.done); | |
771 | } | |
772 | ||
773 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 774 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 775 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 776 | } |
1da177e4 | 777 | |
76e4f660 AR |
778 | set_idle_for_cpu(cpu, c_idle.idle); |
779 | ||
780 | do_rest: | |
781 | ||
782 | cpu_pda[cpu].pcurrent = c_idle.idle; | |
1da177e4 LT |
783 | |
784 | start_rip = setup_trampoline(); | |
785 | ||
76e4f660 | 786 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
787 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
788 | initial_code = start_secondary; | |
76e4f660 | 789 | clear_ti_thread_flag(c_idle.idle->thread_info, TIF_FORK); |
1da177e4 | 790 | |
de04f322 AK |
791 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
792 | cpus_weight(cpu_present_map), | |
793 | apicid); | |
1da177e4 LT |
794 | |
795 | /* | |
796 | * This grunge runs the startup process for | |
797 | * the targeted processor. | |
798 | */ | |
799 | ||
800 | atomic_set(&init_deasserted, 0); | |
801 | ||
802 | Dprintk("Setting warm reset code and vector.\n"); | |
803 | ||
804 | CMOS_WRITE(0xa, 0xf); | |
805 | local_flush_tlb(); | |
806 | Dprintk("1.\n"); | |
807 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
808 | Dprintk("2.\n"); | |
809 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
810 | Dprintk("3.\n"); | |
811 | ||
812 | /* | |
813 | * Be paranoid about clearing APIC errors. | |
814 | */ | |
815 | if (APIC_INTEGRATED(apic_version[apicid])) { | |
816 | apic_read_around(APIC_SPIV); | |
817 | apic_write(APIC_ESR, 0); | |
818 | apic_read(APIC_ESR); | |
819 | } | |
820 | ||
821 | /* | |
822 | * Status is now clean | |
823 | */ | |
824 | boot_error = 0; | |
825 | ||
826 | /* | |
827 | * Starting actual IPI sequence... | |
828 | */ | |
a8ab26fe | 829 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
830 | |
831 | if (!boot_error) { | |
832 | /* | |
833 | * allow APs to start initializing. | |
834 | */ | |
835 | Dprintk("Before Callout %d.\n", cpu); | |
836 | cpu_set(cpu, cpu_callout_map); | |
837 | Dprintk("After Callout %d.\n", cpu); | |
838 | ||
839 | /* | |
840 | * Wait 5s total for a response | |
841 | */ | |
842 | for (timeout = 0; timeout < 50000; timeout++) { | |
843 | if (cpu_isset(cpu, cpu_callin_map)) | |
844 | break; /* It has booted */ | |
845 | udelay(100); | |
846 | } | |
847 | ||
848 | if (cpu_isset(cpu, cpu_callin_map)) { | |
849 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
850 | Dprintk("CPU has booted.\n"); |
851 | } else { | |
852 | boot_error = 1; | |
853 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
854 | == 0xA5) | |
855 | /* trampoline started but...? */ | |
856 | printk("Stuck ??\n"); | |
857 | else | |
858 | /* trampoline code not run */ | |
859 | printk("Not responding.\n"); | |
44456d37 | 860 | #ifdef APIC_DEBUG |
1da177e4 LT |
861 | inquire_remote_apic(apicid); |
862 | #endif | |
863 | } | |
864 | } | |
865 | if (boot_error) { | |
866 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
867 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
a8ab26fe AK |
868 | cpu_clear(cpu, cpu_present_map); |
869 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
870 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
871 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 872 | return -EIO; |
1da177e4 | 873 | } |
a8ab26fe AK |
874 | |
875 | return 0; | |
1da177e4 LT |
876 | } |
877 | ||
a8ab26fe AK |
878 | cycles_t cacheflush_time; |
879 | unsigned long cache_decay_ticks; | |
880 | ||
1da177e4 | 881 | /* |
a8ab26fe | 882 | * Cleanup possible dangling ends... |
1da177e4 | 883 | */ |
a8ab26fe | 884 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 885 | { |
a8ab26fe AK |
886 | /* |
887 | * Paranoid: Set warm reset code and vector here back | |
888 | * to default values. | |
889 | */ | |
890 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 891 | |
a8ab26fe AK |
892 | /* |
893 | * Reset trampoline flag | |
894 | */ | |
895 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
896 | } |
897 | ||
898 | /* | |
899 | * Fall back to non SMP mode after errors. | |
900 | * | |
901 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
902 | */ | |
e6982c67 | 903 | static __init void disable_smp(void) |
a8ab26fe AK |
904 | { |
905 | cpu_present_map = cpumask_of_cpu(0); | |
906 | cpu_possible_map = cpumask_of_cpu(0); | |
907 | if (smp_found_config) | |
908 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
909 | else | |
910 | phys_cpu_present_map = physid_mask_of_physid(0); | |
911 | cpu_set(0, cpu_sibling_map[0]); | |
912 | cpu_set(0, cpu_core_map[0]); | |
913 | } | |
914 | ||
61b1b2d0 | 915 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
916 | |
917 | int additional_cpus __initdata = -1; | |
918 | ||
61b1b2d0 AK |
919 | /* |
920 | * cpu_possible_map should be static, it cannot change as cpu's | |
921 | * are onlined, or offlined. The reason is per-cpu data-structures | |
922 | * are allocated by some modules at init time, and dont expect to | |
923 | * do this dynamically on cpu arrival/departure. | |
924 | * cpu_present_map on the other hand can change dynamically. | |
925 | * In case when cpu_hotplug is not compiled, then we resort to current | |
926 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 927 | * - Ashok Raj |
420f8f68 AK |
928 | * |
929 | * Three ways to find out the number of additional hotplug CPUs: | |
930 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 931 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 932 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
933 | * We do this because additional CPUs waste a lot of memory. |
934 | * -AK | |
61b1b2d0 | 935 | */ |
421c7ce6 | 936 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
937 | { |
938 | int i; | |
420f8f68 AK |
939 | int possible; |
940 | ||
941 | if (additional_cpus == -1) { | |
f62a91f6 | 942 | if (disabled_cpus > 0) |
420f8f68 | 943 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
944 | else |
945 | additional_cpus = 0; | |
420f8f68 AK |
946 | } |
947 | possible = num_processors + additional_cpus; | |
948 | if (possible > NR_CPUS) | |
949 | possible = NR_CPUS; | |
950 | ||
951 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
952 | possible, | |
953 | max_t(int, possible - num_processors, 0)); | |
954 | ||
955 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
956 | cpu_set(i, cpu_possible_map); |
957 | } | |
958 | #endif | |
959 | ||
a8ab26fe AK |
960 | /* |
961 | * Various sanity checks. | |
962 | */ | |
e6982c67 | 963 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 964 | { |
1da177e4 LT |
965 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
966 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
967 | hard_smp_processor_id()); | |
968 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
969 | } | |
970 | ||
971 | /* | |
972 | * If we couldn't find an SMP configuration at boot time, | |
973 | * get out of here now! | |
974 | */ | |
975 | if (!smp_found_config) { | |
976 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 977 | disable_smp(); |
1da177e4 LT |
978 | if (APIC_init_uniprocessor()) |
979 | printk(KERN_NOTICE "Local APIC not detected." | |
980 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 981 | return -1; |
1da177e4 LT |
982 | } |
983 | ||
984 | /* | |
985 | * Should not be necessary because the MP table should list the boot | |
986 | * CPU too, but we do it for the sake of robustness anyway. | |
987 | */ | |
988 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
989 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
990 | boot_cpu_id); | |
991 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
992 | } | |
993 | ||
994 | /* | |
995 | * If we couldn't find a local APIC, then get out of here now! | |
996 | */ | |
997 | if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) { | |
998 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
999 | boot_cpu_id); | |
1000 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
1001 | nr_ioapics = 0; |
1002 | return -1; | |
1da177e4 LT |
1003 | } |
1004 | ||
1da177e4 LT |
1005 | /* |
1006 | * If SMP should be disabled, then really disable it! | |
1007 | */ | |
1008 | if (!max_cpus) { | |
1da177e4 | 1009 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
1010 | nr_ioapics = 0; |
1011 | return -1; | |
1da177e4 LT |
1012 | } |
1013 | ||
a8ab26fe AK |
1014 | return 0; |
1015 | } | |
1da177e4 | 1016 | |
a8ab26fe AK |
1017 | /* |
1018 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1019 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1020 | */ | |
e6982c67 | 1021 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 1022 | { |
a8ab26fe AK |
1023 | nmi_watchdog_default(); |
1024 | current_cpu_data = boot_cpu_data; | |
1025 | current_thread_info()->cpu = 0; /* needed? */ | |
94605eff | 1026 | set_cpu_sibling_map(0); |
1da177e4 | 1027 | |
a8ab26fe AK |
1028 | if (smp_sanity_check(max_cpus) < 0) { |
1029 | printk(KERN_INFO "SMP disabled\n"); | |
1030 | disable_smp(); | |
1031 | return; | |
1da177e4 LT |
1032 | } |
1033 | ||
a8ab26fe | 1034 | |
1da177e4 | 1035 | /* |
a8ab26fe | 1036 | * Switch from PIC to APIC mode. |
1da177e4 | 1037 | */ |
a8ab26fe AK |
1038 | connect_bsp_APIC(); |
1039 | setup_local_APIC(); | |
1da177e4 | 1040 | |
a8ab26fe AK |
1041 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
1042 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1043 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
1044 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 1045 | } |
1da177e4 LT |
1046 | |
1047 | /* | |
a8ab26fe | 1048 | * Now start the IO-APICs |
1da177e4 LT |
1049 | */ |
1050 | if (!skip_ioapic_setup && nr_ioapics) | |
1051 | setup_IO_APIC(); | |
1052 | else | |
1053 | nr_ioapics = 0; | |
1054 | ||
1da177e4 | 1055 | /* |
a8ab26fe | 1056 | * Set up local APIC timer on boot CPU. |
1da177e4 | 1057 | */ |
1da177e4 | 1058 | |
a8ab26fe | 1059 | setup_boot_APIC_clock(); |
1da177e4 LT |
1060 | } |
1061 | ||
a8ab26fe AK |
1062 | /* |
1063 | * Early setup to make printk work. | |
1064 | */ | |
1065 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 1066 | { |
a8ab26fe AK |
1067 | int me = smp_processor_id(); |
1068 | cpu_set(me, cpu_online_map); | |
1069 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 1070 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
1071 | } |
1072 | ||
a8ab26fe AK |
1073 | /* |
1074 | * Entry point to boot a CPU. | |
a8ab26fe AK |
1075 | */ |
1076 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 1077 | { |
a8ab26fe AK |
1078 | int err; |
1079 | int apicid = cpu_present_to_apicid(cpu); | |
1da177e4 | 1080 | |
a8ab26fe | 1081 | WARN_ON(irqs_disabled()); |
1da177e4 | 1082 | |
a8ab26fe AK |
1083 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
1084 | ||
1085 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
1086 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1087 | printk("__cpu_up: bad cpu %d\n", cpu); | |
1088 | return -EINVAL; | |
1089 | } | |
a8ab26fe | 1090 | |
76e4f660 AR |
1091 | /* |
1092 | * Already booted CPU? | |
1093 | */ | |
1094 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1095 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1096 | return -ENOSYS; | |
1097 | } | |
1098 | ||
884d9e40 | 1099 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
1100 | /* Boot it! */ |
1101 | err = do_boot_cpu(cpu, apicid); | |
1102 | if (err < 0) { | |
a8ab26fe AK |
1103 | Dprintk("do_boot_cpu failed %d\n", err); |
1104 | return err; | |
1da177e4 | 1105 | } |
a8ab26fe | 1106 | |
1da177e4 LT |
1107 | /* Unleash the CPU! */ |
1108 | Dprintk("waiting for cpu %d\n", cpu); | |
1109 | ||
1da177e4 | 1110 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1111 | cpu_relax(); |
76e4f660 AR |
1112 | err = 0; |
1113 | ||
1114 | return err; | |
1da177e4 LT |
1115 | } |
1116 | ||
a8ab26fe AK |
1117 | /* |
1118 | * Finish the SMP boot. | |
1119 | */ | |
e6982c67 | 1120 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1121 | { |
a8ab26fe AK |
1122 | smp_cleanup_boot(); |
1123 | ||
1da177e4 LT |
1124 | #ifdef CONFIG_X86_IO_APIC |
1125 | setup_ioapic_dest(); | |
1126 | #endif | |
1da177e4 | 1127 | |
a8ab26fe | 1128 | time_init_gtod(); |
75152114 AK |
1129 | |
1130 | check_nmi_watchdog(); | |
a8ab26fe | 1131 | } |
76e4f660 AR |
1132 | |
1133 | #ifdef CONFIG_HOTPLUG_CPU | |
1134 | ||
cb0cd8d4 | 1135 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1136 | { |
1137 | int sibling; | |
94605eff | 1138 | struct cpuinfo_x86 *c = cpu_data; |
76e4f660 | 1139 | |
94605eff SS |
1140 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1141 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1142 | /* | |
1143 | * last thread sibling in this cpu core going down | |
1144 | */ | |
1145 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1146 | c[sibling].booted_cores--; | |
1147 | } | |
1148 | ||
76e4f660 AR |
1149 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1150 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
76e4f660 AR |
1151 | cpus_clear(cpu_sibling_map[cpu]); |
1152 | cpus_clear(cpu_core_map[cpu]); | |
1153 | phys_proc_id[cpu] = BAD_APICID; | |
1154 | cpu_core_id[cpu] = BAD_APICID; | |
94605eff | 1155 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1156 | } |
1157 | ||
1158 | void remove_cpu_from_maps(void) | |
1159 | { | |
1160 | int cpu = smp_processor_id(); | |
1161 | ||
1162 | cpu_clear(cpu, cpu_callout_map); | |
1163 | cpu_clear(cpu, cpu_callin_map); | |
1164 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
1165 | } | |
1166 | ||
1167 | int __cpu_disable(void) | |
1168 | { | |
1169 | int cpu = smp_processor_id(); | |
1170 | ||
1171 | /* | |
1172 | * Perhaps use cpufreq to drop frequency, but that could go | |
1173 | * into generic code. | |
1174 | * | |
1175 | * We won't take down the boot processor on i386 due to some | |
1176 | * interrupts only being able to be serviced by the BSP. | |
1177 | * Especially so if we're not using an IOAPIC -zwane | |
1178 | */ | |
1179 | if (cpu == 0) | |
1180 | return -EBUSY; | |
1181 | ||
5e9ef02e | 1182 | clear_local_APIC(); |
76e4f660 AR |
1183 | |
1184 | /* | |
1185 | * HACK: | |
1186 | * Allow any queued timer interrupts to get serviced | |
1187 | * This is only a temporary solution until we cleanup | |
1188 | * fixup_irqs as we do for IA64. | |
1189 | */ | |
1190 | local_irq_enable(); | |
1191 | mdelay(1); | |
1192 | ||
1193 | local_irq_disable(); | |
1194 | remove_siblinginfo(cpu); | |
1195 | ||
1196 | /* It's now safe to remove this processor from the online map */ | |
1197 | cpu_clear(cpu, cpu_online_map); | |
1198 | remove_cpu_from_maps(); | |
1199 | fixup_irqs(cpu_online_map); | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | void __cpu_die(unsigned int cpu) | |
1204 | { | |
1205 | /* We don't do anything here: idle task is faking death itself. */ | |
1206 | unsigned int i; | |
1207 | ||
1208 | for (i = 0; i < 10; i++) { | |
1209 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1210 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1211 | printk ("CPU %d is now offline\n", cpu); | |
76e4f660 | 1212 | return; |
884d9e40 | 1213 | } |
ef6e5253 | 1214 | msleep(100); |
76e4f660 AR |
1215 | } |
1216 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1217 | } | |
1218 | ||
420f8f68 AK |
1219 | static __init int setup_additional_cpus(char *s) |
1220 | { | |
1221 | return get_option(&s, &additional_cpus); | |
1222 | } | |
1223 | __setup("additional_cpus=", setup_additional_cpus); | |
1224 | ||
76e4f660 AR |
1225 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1226 | ||
1227 | int __cpu_disable(void) | |
1228 | { | |
1229 | return -ENOSYS; | |
1230 | } | |
1231 | ||
1232 | void __cpu_die(unsigned int cpu) | |
1233 | { | |
1234 | /* We said "no" in __cpu_disable */ | |
1235 | BUG(); | |
1236 | } | |
1237 | #endif /* CONFIG_HOTPLUG_CPU */ |