Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/init.h> |
42 | ||
43 | #include <linux/mm.h> | |
44 | #include <linux/kernel_stat.h> | |
45 | #include <linux/smp_lock.h> | |
1da177e4 LT |
46 | #include <linux/bootmem.h> |
47 | #include <linux/thread_info.h> | |
48 | #include <linux/module.h> | |
1da177e4 LT |
49 | #include <linux/delay.h> |
50 | #include <linux/mc146818rtc.h> | |
a3bc0dbc AM |
51 | #include <linux/smp.h> |
52 | ||
1da177e4 LT |
53 | #include <asm/mtrr.h> |
54 | #include <asm/pgalloc.h> | |
55 | #include <asm/desc.h> | |
56 | #include <asm/kdebug.h> | |
57 | #include <asm/tlbflush.h> | |
58 | #include <asm/proto.h> | |
75152114 | 59 | #include <asm/nmi.h> |
9cdd304b AV |
60 | #include <asm/irq.h> |
61 | #include <asm/hw_irq.h> | |
488fc08d | 62 | #include <asm/numa.h> |
1da177e4 LT |
63 | |
64 | /* Number of siblings per CPU package */ | |
65 | int smp_num_siblings = 1; | |
2ee60e17 | 66 | EXPORT_SYMBOL(smp_num_siblings); |
1da177e4 | 67 | |
1e9f28fa SS |
68 | /* Last level cache ID of each logical CPU */ |
69 | u8 cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
2ee60e17 | 70 | EXPORT_SYMBOL(cpu_llc_id); |
1e9f28fa | 71 | |
1da177e4 | 72 | /* Bitmask of currently online CPUs */ |
6c231b7b | 73 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 74 | |
a8ab26fe AK |
75 | EXPORT_SYMBOL(cpu_online_map); |
76 | ||
77 | /* | |
78 | * Private maps to synchronize booting between AP and BP. | |
79 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
80 | */ | |
1da177e4 LT |
81 | cpumask_t cpu_callin_map; |
82 | cpumask_t cpu_callout_map; | |
2ee60e17 | 83 | EXPORT_SYMBOL(cpu_callout_map); |
a8ab26fe AK |
84 | |
85 | cpumask_t cpu_possible_map; | |
86 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
87 | |
88 | /* Per CPU bogomips and other parameters */ | |
89 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
2ee60e17 | 90 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 91 | |
a8ab26fe AK |
92 | /* Set when the idlers are all forked */ |
93 | int smp_threads_ready; | |
94 | ||
94605eff | 95 | /* representing HT siblings of each logical CPU */ |
6c231b7b | 96 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
2ee60e17 | 97 | EXPORT_SYMBOL(cpu_sibling_map); |
94605eff SS |
98 | |
99 | /* representing HT and core siblings of each logical CPU */ | |
6c231b7b | 100 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
2df9fa36 | 101 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
102 | |
103 | /* | |
104 | * Trampoline 80x86 program as an array. | |
105 | */ | |
106 | ||
a8ab26fe AK |
107 | extern unsigned char trampoline_data[]; |
108 | extern unsigned char trampoline_end[]; | |
1da177e4 | 109 | |
76e4f660 AR |
110 | /* State of each CPU */ |
111 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
112 | ||
113 | /* | |
114 | * Store all idle threads, this can be reused instead of creating | |
115 | * a new thread. Also avoids complicated thread destroy functionality | |
116 | * for idle threads. | |
117 | */ | |
118 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
119 | ||
120 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
121 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
122 | ||
1da177e4 LT |
123 | /* |
124 | * Currently trivial. Write the real->protected mode | |
125 | * bootstrap into the page concerned. The caller | |
126 | * has made sure it's suitably aligned. | |
127 | */ | |
128 | ||
a8ab26fe | 129 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
130 | { |
131 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
132 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
133 | return virt_to_phys(tramp); | |
134 | } | |
135 | ||
136 | /* | |
137 | * The bootstrap kernel entry code has set these up. Save them for | |
138 | * a given CPU | |
139 | */ | |
140 | ||
a8ab26fe | 141 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
142 | { |
143 | struct cpuinfo_x86 *c = cpu_data + id; | |
144 | ||
145 | *c = boot_cpu_data; | |
146 | identify_cpu(c); | |
dda50e71 | 147 | print_cpu_info(c); |
1da177e4 LT |
148 | } |
149 | ||
150 | /* | |
dda50e71 AK |
151 | * New Funky TSC sync algorithm borrowed from IA64. |
152 | * Main advantage is that it doesn't reset the TSCs fully and | |
153 | * in general looks more robust and it works better than my earlier | |
154 | * attempts. I believe it was written by David Mosberger. Some minor | |
155 | * adjustments for x86-64 by me -AK | |
1da177e4 | 156 | * |
dda50e71 AK |
157 | * Original comment reproduced below. |
158 | * | |
159 | * Synchronize TSC of the current (slave) CPU with the TSC of the | |
160 | * MASTER CPU (normally the time-keeper CPU). We use a closed loop to | |
161 | * eliminate the possibility of unaccounted-for errors (such as | |
162 | * getting a machine check in the middle of a calibration step). The | |
163 | * basic idea is for the slave to ask the master what itc value it has | |
164 | * and to read its own itc before and after the master responds. Each | |
165 | * iteration gives us three timestamps: | |
166 | * | |
167 | * slave master | |
168 | * | |
169 | * t0 ---\ | |
170 | * ---\ | |
171 | * ---> | |
172 | * tm | |
173 | * /--- | |
174 | * /--- | |
175 | * t1 <--- | |
176 | * | |
177 | * | |
178 | * The goal is to adjust the slave's TSC such that tm falls exactly | |
179 | * half-way between t0 and t1. If we achieve this, the clocks are | |
180 | * synchronized provided the interconnect between the slave and the | |
181 | * master is symmetric. Even if the interconnect were asymmetric, we | |
182 | * would still know that the synchronization error is smaller than the | |
183 | * roundtrip latency (t0 - t1). | |
184 | * | |
185 | * When the interconnect is quiet and symmetric, this lets us | |
186 | * synchronize the TSC to within one or two cycles. However, we can | |
187 | * only *guarantee* that the synchronization is accurate to within a | |
188 | * round-trip time, which is typically in the range of several hundred | |
189 | * cycles (e.g., ~500 cycles). In practice, this means that the TSCs | |
190 | * are usually almost perfectly synchronized, but we shouldn't assume | |
191 | * that the accuracy is much better than half a micro second or so. | |
192 | * | |
193 | * [there are other errors like the latency of RDTSC and of the | |
194 | * WRMSR. These can also account to hundreds of cycles. So it's | |
195 | * probably worse. It claims 153 cycles error on a dual Opteron, | |
196 | * but I suspect the numbers are actually somewhat worse -AK] | |
1da177e4 LT |
197 | */ |
198 | ||
dda50e71 AK |
199 | #define MASTER 0 |
200 | #define SLAVE (SMP_CACHE_BYTES/8) | |
201 | ||
202 | /* Intentionally don't use cpu_relax() while TSC synchronization | |
203 | because we don't want to go into funky power save modi or cause | |
204 | hypervisors to schedule us away. Going to sleep would likely affect | |
205 | latency and low latency is the primary objective here. -AK */ | |
206 | #define no_cpu_relax() barrier() | |
207 | ||
a8ab26fe | 208 | static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock); |
dda50e71 AK |
209 | static volatile __cpuinitdata unsigned long go[SLAVE + 1]; |
210 | static int notscsync __cpuinitdata; | |
211 | ||
212 | #undef DEBUG_TSC_SYNC | |
1da177e4 | 213 | |
dda50e71 AK |
214 | #define NUM_ROUNDS 64 /* magic value */ |
215 | #define NUM_ITERS 5 /* likewise */ | |
1da177e4 | 216 | |
dda50e71 AK |
217 | /* Callback on boot CPU */ |
218 | static __cpuinit void sync_master(void *arg) | |
1da177e4 | 219 | { |
dda50e71 AK |
220 | unsigned long flags, i; |
221 | ||
dda50e71 AK |
222 | go[MASTER] = 0; |
223 | ||
224 | local_irq_save(flags); | |
225 | { | |
226 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) { | |
227 | while (!go[MASTER]) | |
228 | no_cpu_relax(); | |
229 | go[MASTER] = 0; | |
230 | rdtscll(go[SLAVE]); | |
231 | } | |
232 | } | |
233 | local_irq_restore(flags); | |
a8ab26fe | 234 | } |
1da177e4 | 235 | |
a8ab26fe | 236 | /* |
dda50e71 AK |
237 | * Return the number of cycles by which our tsc differs from the tsc |
238 | * on the master (time-keeper) CPU. A positive number indicates our | |
239 | * tsc is ahead of the master, negative that it is behind. | |
a8ab26fe | 240 | */ |
dda50e71 AK |
241 | static inline long |
242 | get_delta(long *rt, long *master) | |
a8ab26fe | 243 | { |
dda50e71 AK |
244 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; |
245 | unsigned long tcenter, t0, t1, tm; | |
246 | int i; | |
a8ab26fe | 247 | |
dda50e71 AK |
248 | for (i = 0; i < NUM_ITERS; ++i) { |
249 | rdtscll(t0); | |
250 | go[MASTER] = 1; | |
251 | while (!(tm = go[SLAVE])) | |
252 | no_cpu_relax(); | |
253 | go[SLAVE] = 0; | |
254 | rdtscll(t1); | |
255 | ||
256 | if (t1 - t0 < best_t1 - best_t0) | |
257 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
258 | } | |
259 | ||
260 | *rt = best_t1 - best_t0; | |
261 | *master = best_tm - best_t0; | |
262 | ||
263 | /* average best_t0 and best_t1 without overflow: */ | |
264 | tcenter = (best_t0/2 + best_t1/2); | |
265 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
266 | ++tcenter; | |
267 | return tcenter - best_tm; | |
1da177e4 LT |
268 | } |
269 | ||
3d483f47 | 270 | static __cpuinit void sync_tsc(unsigned int master) |
1da177e4 | 271 | { |
dda50e71 AK |
272 | int i, done = 0; |
273 | long delta, adj, adjust_latency = 0; | |
274 | unsigned long flags, rt, master_time_stamp, bound; | |
44456d37 | 275 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
276 | static struct syncdebug { |
277 | long rt; /* roundtrip time */ | |
278 | long master; /* master's timestamp */ | |
279 | long diff; /* difference between midpoint and master's timestamp */ | |
280 | long lat; /* estimate of tsc adjustment latency */ | |
281 | } t[NUM_ROUNDS] __cpuinitdata; | |
282 | #endif | |
283 | ||
3d483f47 EB |
284 | printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", |
285 | smp_processor_id(), master); | |
286 | ||
dda50e71 AK |
287 | go[MASTER] = 1; |
288 | ||
3d483f47 EB |
289 | /* It is dangerous to broadcast IPI as cpus are coming up, |
290 | * as they may not be ready to accept them. So since | |
291 | * we only need to send the ipi to the boot cpu direct | |
292 | * the message, and avoid the race. | |
293 | */ | |
294 | smp_call_function_single(master, sync_master, NULL, 1, 0); | |
dda50e71 AK |
295 | |
296 | while (go[MASTER]) /* wait for master to be ready */ | |
297 | no_cpu_relax(); | |
298 | ||
299 | spin_lock_irqsave(&tsc_sync_lock, flags); | |
300 | { | |
301 | for (i = 0; i < NUM_ROUNDS; ++i) { | |
302 | delta = get_delta(&rt, &master_time_stamp); | |
303 | if (delta == 0) { | |
304 | done = 1; /* let's lock on to this... */ | |
305 | bound = rt; | |
306 | } | |
307 | ||
308 | if (!done) { | |
309 | unsigned long t; | |
310 | if (i > 0) { | |
311 | adjust_latency += -delta; | |
312 | adj = -delta + adjust_latency/4; | |
313 | } else | |
314 | adj = -delta; | |
315 | ||
316 | rdtscll(t); | |
317 | wrmsrl(MSR_IA32_TSC, t + adj); | |
318 | } | |
44456d37 | 319 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
320 | t[i].rt = rt; |
321 | t[i].master = master_time_stamp; | |
322 | t[i].diff = delta; | |
323 | t[i].lat = adjust_latency/4; | |
324 | #endif | |
325 | } | |
326 | } | |
327 | spin_unlock_irqrestore(&tsc_sync_lock, flags); | |
328 | ||
44456d37 | 329 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
330 | for (i = 0; i < NUM_ROUNDS; ++i) |
331 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
332 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
333 | #endif | |
334 | ||
335 | printk(KERN_INFO | |
336 | "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, " | |
337 | "maxerr %lu cycles)\n", | |
3d483f47 | 338 | smp_processor_id(), master, delta, rt); |
a8ab26fe | 339 | } |
1da177e4 | 340 | |
dda50e71 | 341 | static void __cpuinit tsc_sync_wait(void) |
a8ab26fe | 342 | { |
737c5c3b AK |
343 | /* |
344 | * When the CPU has synchronized TSCs assume the BIOS | |
345 | * or the hardware already synced. Otherwise we could | |
346 | * mess up a possible perfect synchronization with a | |
347 | * not-quite-perfect algorithm. | |
348 | */ | |
349 | if (notscsync || !cpu_has_tsc || !unsynchronized_tsc()) | |
a8ab26fe | 350 | return; |
349188f6 | 351 | sync_tsc(0); |
a8ab26fe | 352 | } |
1da177e4 | 353 | |
dda50e71 | 354 | static __init int notscsync_setup(char *s) |
a8ab26fe | 355 | { |
dda50e71 | 356 | notscsync = 1; |
9b41046c | 357 | return 1; |
1da177e4 | 358 | } |
dda50e71 | 359 | __setup("notscsync", notscsync_setup); |
1da177e4 | 360 | |
a8ab26fe | 361 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 362 | |
a8ab26fe AK |
363 | /* |
364 | * Report back to the Boot Processor. | |
365 | * Running on AP. | |
366 | */ | |
367 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
368 | { |
369 | int cpuid, phys_id; | |
370 | unsigned long timeout; | |
371 | ||
372 | /* | |
373 | * If waken up by an INIT in an 82489DX configuration | |
374 | * we may get here before an INIT-deassert IPI reaches | |
375 | * our local APIC. We have to wait for the IPI or we'll | |
376 | * lock up on an APIC access. | |
377 | */ | |
a8ab26fe AK |
378 | while (!atomic_read(&init_deasserted)) |
379 | cpu_relax(); | |
1da177e4 LT |
380 | |
381 | /* | |
382 | * (This works even if the APIC is not enabled.) | |
383 | */ | |
384 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
385 | cpuid = smp_processor_id(); | |
386 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
387 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
388 | phys_id, cpuid); | |
389 | } | |
390 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
391 | ||
392 | /* | |
393 | * STARTUP IPIs are fragile beasts as they might sometimes | |
394 | * trigger some glue motherboard logic. Complete APIC bus | |
395 | * silence for 1 second, this overestimates the time the | |
396 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
397 | * by a factor of two. This should be enough. | |
398 | */ | |
399 | ||
400 | /* | |
401 | * Waiting 2s total for startup (udelay is not yet working) | |
402 | */ | |
403 | timeout = jiffies + 2*HZ; | |
404 | while (time_before(jiffies, timeout)) { | |
405 | /* | |
406 | * Has the boot CPU finished it's STARTUP sequence? | |
407 | */ | |
408 | if (cpu_isset(cpuid, cpu_callout_map)) | |
409 | break; | |
a8ab26fe | 410 | cpu_relax(); |
1da177e4 LT |
411 | } |
412 | ||
413 | if (!time_before(jiffies, timeout)) { | |
414 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
415 | cpuid); | |
416 | } | |
417 | ||
418 | /* | |
419 | * the boot CPU has finished the init stage and is spinning | |
420 | * on callin_map until we finish. We are free to set up this | |
421 | * CPU, first the APIC. (this is probably redundant on most | |
422 | * boards) | |
423 | */ | |
424 | ||
425 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
426 | setup_local_APIC(); | |
427 | ||
1da177e4 LT |
428 | /* |
429 | * Get our bogomips. | |
b4452218 AK |
430 | * |
431 | * Need to enable IRQs because it can take longer and then | |
432 | * the NMI watchdog might kill us. | |
1da177e4 | 433 | */ |
b4452218 | 434 | local_irq_enable(); |
1da177e4 | 435 | calibrate_delay(); |
b4452218 | 436 | local_irq_disable(); |
1da177e4 LT |
437 | Dprintk("Stack at about %p\n",&cpuid); |
438 | ||
439 | disable_APIC_timer(); | |
440 | ||
441 | /* | |
442 | * Save our processor parameters | |
443 | */ | |
444 | smp_store_cpu_info(cpuid); | |
445 | ||
1da177e4 LT |
446 | /* |
447 | * Allow the master to continue. | |
448 | */ | |
449 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
450 | } |
451 | ||
1e9f28fa SS |
452 | /* maps the cpu to the sched domain representing multi-core */ |
453 | cpumask_t cpu_coregroup_map(int cpu) | |
454 | { | |
455 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
456 | /* | |
457 | * For perf, we return last level cache shared map. | |
5c45bf27 | 458 | * And for power savings, we return cpu_core_map |
1e9f28fa | 459 | */ |
5c45bf27 SS |
460 | if (sched_mc_power_savings || sched_smt_power_savings) |
461 | return cpu_core_map[cpu]; | |
462 | else | |
463 | return c->llc_shared_map; | |
1e9f28fa SS |
464 | } |
465 | ||
94605eff SS |
466 | /* representing cpus for which sibling maps can be computed */ |
467 | static cpumask_t cpu_sibling_setup_map; | |
468 | ||
cb0cd8d4 AR |
469 | static inline void set_cpu_sibling_map(int cpu) |
470 | { | |
471 | int i; | |
94605eff SS |
472 | struct cpuinfo_x86 *c = cpu_data; |
473 | ||
474 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
475 | |
476 | if (smp_num_siblings > 1) { | |
94605eff | 477 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
f3fa8ebc RS |
478 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
479 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
cb0cd8d4 AR |
480 | cpu_set(i, cpu_sibling_map[cpu]); |
481 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
482 | cpu_set(i, cpu_core_map[cpu]); |
483 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
484 | cpu_set(i, c[cpu].llc_shared_map); |
485 | cpu_set(cpu, c[i].llc_shared_map); | |
cb0cd8d4 AR |
486 | } |
487 | } | |
488 | } else { | |
489 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
490 | } | |
491 | ||
1e9f28fa SS |
492 | cpu_set(cpu, c[cpu].llc_shared_map); |
493 | ||
94605eff | 494 | if (current_cpu_data.x86_max_cores == 1) { |
cb0cd8d4 | 495 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
496 | c[cpu].booted_cores = 1; |
497 | return; | |
498 | } | |
499 | ||
500 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
501 | if (cpu_llc_id[cpu] != BAD_APICID && |
502 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
503 | cpu_set(i, c[cpu].llc_shared_map); | |
504 | cpu_set(cpu, c[i].llc_shared_map); | |
505 | } | |
f3fa8ebc | 506 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
507 | cpu_set(i, cpu_core_map[cpu]); |
508 | cpu_set(cpu, cpu_core_map[i]); | |
509 | /* | |
510 | * Does this new cpu bringup a new core? | |
511 | */ | |
512 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
513 | /* | |
514 | * for each core in package, increment | |
515 | * the booted_cores for this new cpu | |
516 | */ | |
517 | if (first_cpu(cpu_sibling_map[i]) == i) | |
518 | c[cpu].booted_cores++; | |
519 | /* | |
520 | * increment the core count for all | |
521 | * the other cpus in this package | |
522 | */ | |
523 | if (i != cpu) | |
524 | c[i].booted_cores++; | |
525 | } else if (i != cpu && !c[cpu].booted_cores) | |
526 | c[cpu].booted_cores = c[i].booted_cores; | |
527 | } | |
cb0cd8d4 AR |
528 | } |
529 | } | |
530 | ||
1da177e4 | 531 | /* |
a8ab26fe | 532 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 533 | */ |
a8ab26fe | 534 | void __cpuinit start_secondary(void) |
1da177e4 LT |
535 | { |
536 | /* | |
537 | * Dont put anything before smp_callin(), SMP | |
538 | * booting is too fragile that we want to limit the | |
539 | * things done here to the most necessary things. | |
540 | */ | |
541 | cpu_init(); | |
5bfb5d69 | 542 | preempt_disable(); |
1da177e4 LT |
543 | smp_callin(); |
544 | ||
545 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
546 | barrier(); | |
547 | ||
1da177e4 LT |
548 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
549 | setup_secondary_APIC_clock(); | |
550 | ||
a8ab26fe | 551 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
552 | |
553 | if (nmi_watchdog == NMI_IO_APIC) { | |
554 | disable_8259A_irq(0); | |
555 | enable_NMI_through_LVT0(NULL); | |
556 | enable_8259A_irq(0); | |
557 | } | |
558 | ||
a8ab26fe | 559 | enable_APIC_timer(); |
1da177e4 | 560 | |
cb0cd8d4 AR |
561 | /* |
562 | * The sibling maps must be set before turing the online map on for | |
563 | * this cpu | |
564 | */ | |
565 | set_cpu_sibling_map(smp_processor_id()); | |
566 | ||
1eecd73c AK |
567 | /* |
568 | * Wait for TSC sync to not schedule things before. | |
569 | * We still process interrupts, which could see an inconsistent | |
570 | * time in that window unfortunately. | |
571 | * Do this here because TSC sync has global unprotected state. | |
572 | */ | |
573 | tsc_sync_wait(); | |
574 | ||
884d9e40 AR |
575 | /* |
576 | * We need to hold call_lock, so there is no inconsistency | |
577 | * between the time smp_call_function() determines number of | |
578 | * IPI receipients, and the time when the determination is made | |
579 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
580 | * lock helps us to not include this cpu in a currently in progress | |
581 | * smp_call_function(). | |
582 | */ | |
583 | lock_ipi_call_lock(); | |
70a0a535 | 584 | spin_lock(&vector_lock); |
884d9e40 | 585 | |
70a0a535 EB |
586 | /* Setup the per cpu irq handling data structures */ |
587 | __setup_vector_irq(smp_processor_id()); | |
1da177e4 | 588 | /* |
a8ab26fe | 589 | * Allow the master to continue. |
1da177e4 | 590 | */ |
1da177e4 | 591 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 | 592 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
70a0a535 | 593 | spin_unlock(&vector_lock); |
884d9e40 AR |
594 | unlock_ipi_call_lock(); |
595 | ||
1da177e4 LT |
596 | cpu_idle(); |
597 | } | |
598 | ||
a8ab26fe | 599 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
600 | extern void (*initial_code)(void); |
601 | ||
44456d37 | 602 | #ifdef APIC_DEBUG |
a8ab26fe | 603 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
604 | { |
605 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
606 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
607 | int timeout, status; | |
608 | ||
609 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
610 | ||
611 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
612 | printk("... APIC #%d %s: ", apicid, names[i]); | |
613 | ||
614 | /* | |
615 | * Wait for idle. | |
616 | */ | |
617 | apic_wait_icr_idle(); | |
618 | ||
c1507eb2 AK |
619 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
620 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
621 | |
622 | timeout = 0; | |
623 | do { | |
624 | udelay(100); | |
625 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
626 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
627 | ||
628 | switch (status) { | |
629 | case APIC_ICR_RR_VALID: | |
630 | status = apic_read(APIC_RRR); | |
631 | printk("%08x\n", status); | |
632 | break; | |
633 | default: | |
634 | printk("failed\n"); | |
635 | } | |
636 | } | |
637 | } | |
638 | #endif | |
639 | ||
a8ab26fe AK |
640 | /* |
641 | * Kick the secondary to wake up. | |
642 | */ | |
643 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 LT |
644 | { |
645 | unsigned long send_status = 0, accept_status = 0; | |
646 | int maxlvt, timeout, num_starts, j; | |
647 | ||
648 | Dprintk("Asserting INIT.\n"); | |
649 | ||
650 | /* | |
651 | * Turn INIT on target chip | |
652 | */ | |
c1507eb2 | 653 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
654 | |
655 | /* | |
656 | * Send IPI | |
657 | */ | |
c1507eb2 | 658 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
659 | | APIC_DM_INIT); |
660 | ||
661 | Dprintk("Waiting for send to finish...\n"); | |
662 | timeout = 0; | |
663 | do { | |
664 | Dprintk("+"); | |
665 | udelay(100); | |
666 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
667 | } while (send_status && (timeout++ < 1000)); | |
668 | ||
669 | mdelay(10); | |
670 | ||
671 | Dprintk("Deasserting INIT.\n"); | |
672 | ||
673 | /* Target chip */ | |
c1507eb2 | 674 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
675 | |
676 | /* Send IPI */ | |
c1507eb2 | 677 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
678 | |
679 | Dprintk("Waiting for send to finish...\n"); | |
680 | timeout = 0; | |
681 | do { | |
682 | Dprintk("+"); | |
683 | udelay(100); | |
684 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
685 | } while (send_status && (timeout++ < 1000)); | |
686 | ||
f2ecfab9 | 687 | mb(); |
1da177e4 LT |
688 | atomic_set(&init_deasserted, 1); |
689 | ||
5a40b7c2 | 690 | num_starts = 2; |
1da177e4 LT |
691 | |
692 | /* | |
693 | * Run STARTUP IPI loop. | |
694 | */ | |
695 | Dprintk("#startup loops: %d.\n", num_starts); | |
696 | ||
697 | maxlvt = get_maxlvt(); | |
698 | ||
699 | for (j = 1; j <= num_starts; j++) { | |
700 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
701 | apic_write(APIC_ESR, 0); |
702 | apic_read(APIC_ESR); | |
703 | Dprintk("After apic_write.\n"); | |
704 | ||
705 | /* | |
706 | * STARTUP IPI | |
707 | */ | |
708 | ||
709 | /* Target chip */ | |
c1507eb2 | 710 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
711 | |
712 | /* Boot on the stack */ | |
713 | /* Kick the second */ | |
c1507eb2 | 714 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
715 | |
716 | /* | |
717 | * Give the other CPU some time to accept the IPI. | |
718 | */ | |
719 | udelay(300); | |
720 | ||
721 | Dprintk("Startup point 1.\n"); | |
722 | ||
723 | Dprintk("Waiting for send to finish...\n"); | |
724 | timeout = 0; | |
725 | do { | |
726 | Dprintk("+"); | |
727 | udelay(100); | |
728 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
729 | } while (send_status && (timeout++ < 1000)); | |
730 | ||
731 | /* | |
732 | * Give the other CPU some time to accept the IPI. | |
733 | */ | |
734 | udelay(200); | |
735 | /* | |
736 | * Due to the Pentium erratum 3AP. | |
737 | */ | |
738 | if (maxlvt > 3) { | |
1da177e4 LT |
739 | apic_write(APIC_ESR, 0); |
740 | } | |
741 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
742 | if (send_status || accept_status) | |
743 | break; | |
744 | } | |
745 | Dprintk("After Startup.\n"); | |
746 | ||
747 | if (send_status) | |
748 | printk(KERN_ERR "APIC never delivered???\n"); | |
749 | if (accept_status) | |
750 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
751 | ||
752 | return (send_status | accept_status); | |
753 | } | |
754 | ||
76e4f660 | 755 | struct create_idle { |
65f27f38 | 756 | struct work_struct work; |
76e4f660 AR |
757 | struct task_struct *idle; |
758 | struct completion done; | |
759 | int cpu; | |
760 | }; | |
761 | ||
65f27f38 | 762 | void do_fork_idle(struct work_struct *work) |
76e4f660 | 763 | { |
65f27f38 DH |
764 | struct create_idle *c_idle = |
765 | container_of(work, struct create_idle, work); | |
76e4f660 AR |
766 | |
767 | c_idle->idle = fork_idle(c_idle->cpu); | |
768 | complete(&c_idle->done); | |
769 | } | |
770 | ||
a8ab26fe AK |
771 | /* |
772 | * Boot one CPU. | |
773 | */ | |
774 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 775 | { |
1da177e4 | 776 | unsigned long boot_error; |
a8ab26fe | 777 | int timeout; |
1da177e4 | 778 | unsigned long start_rip; |
76e4f660 | 779 | struct create_idle c_idle = { |
65f27f38 | 780 | .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle), |
76e4f660 | 781 | .cpu = cpu, |
f86bf9b7 | 782 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), |
76e4f660 | 783 | }; |
76e4f660 | 784 | |
c11efdf9 RT |
785 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
786 | if (!cpu_gdt_descr[cpu].address && | |
787 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
788 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
789 | return -1; | |
790 | } | |
791 | ||
365ba917 RT |
792 | /* Allocate node local memory for AP pdas */ |
793 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
794 | struct x8664_pda *newpda, *pda; | |
795 | int node = cpu_to_node(cpu); | |
796 | pda = cpu_pda(cpu); | |
797 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
798 | node); | |
799 | if (newpda) { | |
800 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
801 | cpu_pda(cpu) = newpda; | |
802 | } else | |
803 | printk(KERN_ERR | |
804 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
805 | cpu, node); | |
806 | } | |
807 | ||
d167a518 GH |
808 | alternatives_smp_switch(1); |
809 | ||
76e4f660 AR |
810 | c_idle.idle = get_idle_for_cpu(cpu); |
811 | ||
812 | if (c_idle.idle) { | |
813 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
57eafdc2 | 814 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
815 | init_idle(c_idle.idle, cpu); |
816 | goto do_rest; | |
817 | } | |
818 | ||
1da177e4 | 819 | /* |
76e4f660 AR |
820 | * During cold boot process, keventd thread is not spun up yet. |
821 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
822 | * not acquire any attributes from the calling context. Hence the clean | |
823 | * way to create kernel_threads() is to do that from keventd(). | |
824 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
825 | * was also queuing to keventd() and when the caller is already running | |
826 | * in context of keventd(), we would end up with locking up the keventd | |
827 | * thread. | |
1da177e4 | 828 | */ |
76e4f660 | 829 | if (!keventd_up() || current_is_keventd()) |
65f27f38 | 830 | c_idle.work.func(&c_idle.work); |
76e4f660 | 831 | else { |
65f27f38 | 832 | schedule_work(&c_idle.work); |
76e4f660 AR |
833 | wait_for_completion(&c_idle.done); |
834 | } | |
835 | ||
836 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 837 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 838 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 839 | } |
1da177e4 | 840 | |
76e4f660 AR |
841 | set_idle_for_cpu(cpu, c_idle.idle); |
842 | ||
843 | do_rest: | |
844 | ||
df79efde | 845 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
846 | |
847 | start_rip = setup_trampoline(); | |
848 | ||
76e4f660 | 849 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
850 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
851 | initial_code = start_secondary; | |
e4f17c43 | 852 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 853 | |
de04f322 AK |
854 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
855 | cpus_weight(cpu_present_map), | |
856 | apicid); | |
1da177e4 LT |
857 | |
858 | /* | |
859 | * This grunge runs the startup process for | |
860 | * the targeted processor. | |
861 | */ | |
862 | ||
863 | atomic_set(&init_deasserted, 0); | |
864 | ||
865 | Dprintk("Setting warm reset code and vector.\n"); | |
866 | ||
867 | CMOS_WRITE(0xa, 0xf); | |
868 | local_flush_tlb(); | |
869 | Dprintk("1.\n"); | |
870 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
871 | Dprintk("2.\n"); | |
872 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
873 | Dprintk("3.\n"); | |
874 | ||
875 | /* | |
876 | * Be paranoid about clearing APIC errors. | |
877 | */ | |
11a8e778 AK |
878 | apic_write(APIC_ESR, 0); |
879 | apic_read(APIC_ESR); | |
1da177e4 LT |
880 | |
881 | /* | |
882 | * Status is now clean | |
883 | */ | |
884 | boot_error = 0; | |
885 | ||
886 | /* | |
887 | * Starting actual IPI sequence... | |
888 | */ | |
a8ab26fe | 889 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
890 | |
891 | if (!boot_error) { | |
892 | /* | |
893 | * allow APs to start initializing. | |
894 | */ | |
895 | Dprintk("Before Callout %d.\n", cpu); | |
896 | cpu_set(cpu, cpu_callout_map); | |
897 | Dprintk("After Callout %d.\n", cpu); | |
898 | ||
899 | /* | |
900 | * Wait 5s total for a response | |
901 | */ | |
902 | for (timeout = 0; timeout < 50000; timeout++) { | |
903 | if (cpu_isset(cpu, cpu_callin_map)) | |
904 | break; /* It has booted */ | |
905 | udelay(100); | |
906 | } | |
907 | ||
908 | if (cpu_isset(cpu, cpu_callin_map)) { | |
909 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
910 | Dprintk("CPU has booted.\n"); |
911 | } else { | |
912 | boot_error = 1; | |
913 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
914 | == 0xA5) | |
915 | /* trampoline started but...? */ | |
916 | printk("Stuck ??\n"); | |
917 | else | |
918 | /* trampoline code not run */ | |
919 | printk("Not responding.\n"); | |
44456d37 | 920 | #ifdef APIC_DEBUG |
1da177e4 LT |
921 | inquire_remote_apic(apicid); |
922 | #endif | |
923 | } | |
924 | } | |
925 | if (boot_error) { | |
926 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
927 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 928 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
929 | cpu_clear(cpu, cpu_present_map); |
930 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
931 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
932 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 933 | return -EIO; |
1da177e4 | 934 | } |
a8ab26fe AK |
935 | |
936 | return 0; | |
1da177e4 LT |
937 | } |
938 | ||
a8ab26fe AK |
939 | cycles_t cacheflush_time; |
940 | unsigned long cache_decay_ticks; | |
941 | ||
1da177e4 | 942 | /* |
a8ab26fe | 943 | * Cleanup possible dangling ends... |
1da177e4 | 944 | */ |
a8ab26fe | 945 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 946 | { |
a8ab26fe AK |
947 | /* |
948 | * Paranoid: Set warm reset code and vector here back | |
949 | * to default values. | |
950 | */ | |
951 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 952 | |
a8ab26fe AK |
953 | /* |
954 | * Reset trampoline flag | |
955 | */ | |
956 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
957 | } |
958 | ||
959 | /* | |
960 | * Fall back to non SMP mode after errors. | |
961 | * | |
962 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
963 | */ | |
e6982c67 | 964 | static __init void disable_smp(void) |
a8ab26fe AK |
965 | { |
966 | cpu_present_map = cpumask_of_cpu(0); | |
967 | cpu_possible_map = cpumask_of_cpu(0); | |
968 | if (smp_found_config) | |
969 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
970 | else | |
971 | phys_cpu_present_map = physid_mask_of_physid(0); | |
972 | cpu_set(0, cpu_sibling_map[0]); | |
973 | cpu_set(0, cpu_core_map[0]); | |
974 | } | |
975 | ||
61b1b2d0 | 976 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
977 | |
978 | int additional_cpus __initdata = -1; | |
979 | ||
61b1b2d0 AK |
980 | /* |
981 | * cpu_possible_map should be static, it cannot change as cpu's | |
982 | * are onlined, or offlined. The reason is per-cpu data-structures | |
983 | * are allocated by some modules at init time, and dont expect to | |
984 | * do this dynamically on cpu arrival/departure. | |
985 | * cpu_present_map on the other hand can change dynamically. | |
986 | * In case when cpu_hotplug is not compiled, then we resort to current | |
987 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 988 | * - Ashok Raj |
420f8f68 AK |
989 | * |
990 | * Three ways to find out the number of additional hotplug CPUs: | |
991 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 992 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 993 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
994 | * We do this because additional CPUs waste a lot of memory. |
995 | * -AK | |
61b1b2d0 | 996 | */ |
421c7ce6 | 997 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
998 | { |
999 | int i; | |
420f8f68 AK |
1000 | int possible; |
1001 | ||
1002 | if (additional_cpus == -1) { | |
f62a91f6 | 1003 | if (disabled_cpus > 0) |
420f8f68 | 1004 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
1005 | else |
1006 | additional_cpus = 0; | |
420f8f68 AK |
1007 | } |
1008 | possible = num_processors + additional_cpus; | |
1009 | if (possible > NR_CPUS) | |
1010 | possible = NR_CPUS; | |
1011 | ||
1012 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1013 | possible, | |
1014 | max_t(int, possible - num_processors, 0)); | |
1015 | ||
1016 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
1017 | cpu_set(i, cpu_possible_map); |
1018 | } | |
1019 | #endif | |
1020 | ||
a8ab26fe AK |
1021 | /* |
1022 | * Various sanity checks. | |
1023 | */ | |
e6982c67 | 1024 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 1025 | { |
1da177e4 LT |
1026 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1027 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1028 | hard_smp_processor_id()); | |
1029 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * If we couldn't find an SMP configuration at boot time, | |
1034 | * get out of here now! | |
1035 | */ | |
1036 | if (!smp_found_config) { | |
1037 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 1038 | disable_smp(); |
1da177e4 LT |
1039 | if (APIC_init_uniprocessor()) |
1040 | printk(KERN_NOTICE "Local APIC not detected." | |
1041 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 1042 | return -1; |
1da177e4 LT |
1043 | } |
1044 | ||
1045 | /* | |
1046 | * Should not be necessary because the MP table should list the boot | |
1047 | * CPU too, but we do it for the sake of robustness anyway. | |
1048 | */ | |
1049 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
1050 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1051 | boot_cpu_id); | |
1052 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * If we couldn't find a local APIC, then get out of here now! | |
1057 | */ | |
11a8e778 | 1058 | if (!cpu_has_apic) { |
1da177e4 LT |
1059 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
1060 | boot_cpu_id); | |
1061 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
1062 | nr_ioapics = 0; |
1063 | return -1; | |
1da177e4 LT |
1064 | } |
1065 | ||
1da177e4 LT |
1066 | /* |
1067 | * If SMP should be disabled, then really disable it! | |
1068 | */ | |
1069 | if (!max_cpus) { | |
1da177e4 | 1070 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
1071 | nr_ioapics = 0; |
1072 | return -1; | |
1da177e4 LT |
1073 | } |
1074 | ||
a8ab26fe AK |
1075 | return 0; |
1076 | } | |
1da177e4 | 1077 | |
a8ab26fe AK |
1078 | /* |
1079 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1080 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1081 | */ | |
e6982c67 | 1082 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 1083 | { |
a8ab26fe AK |
1084 | nmi_watchdog_default(); |
1085 | current_cpu_data = boot_cpu_data; | |
1086 | current_thread_info()->cpu = 0; /* needed? */ | |
94605eff | 1087 | set_cpu_sibling_map(0); |
1da177e4 | 1088 | |
a8ab26fe AK |
1089 | if (smp_sanity_check(max_cpus) < 0) { |
1090 | printk(KERN_INFO "SMP disabled\n"); | |
1091 | disable_smp(); | |
1092 | return; | |
1da177e4 LT |
1093 | } |
1094 | ||
a8ab26fe | 1095 | |
1da177e4 | 1096 | /* |
a8ab26fe | 1097 | * Switch from PIC to APIC mode. |
1da177e4 | 1098 | */ |
a8ab26fe | 1099 | setup_local_APIC(); |
1da177e4 | 1100 | |
a8ab26fe AK |
1101 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
1102 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1103 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
1104 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 1105 | } |
1da177e4 LT |
1106 | |
1107 | /* | |
a8ab26fe | 1108 | * Now start the IO-APICs |
1da177e4 LT |
1109 | */ |
1110 | if (!skip_ioapic_setup && nr_ioapics) | |
1111 | setup_IO_APIC(); | |
1112 | else | |
1113 | nr_ioapics = 0; | |
1114 | ||
1da177e4 | 1115 | /* |
a8ab26fe | 1116 | * Set up local APIC timer on boot CPU. |
1da177e4 | 1117 | */ |
1da177e4 | 1118 | |
a8ab26fe | 1119 | setup_boot_APIC_clock(); |
1da177e4 LT |
1120 | } |
1121 | ||
a8ab26fe AK |
1122 | /* |
1123 | * Early setup to make printk work. | |
1124 | */ | |
1125 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 1126 | { |
a8ab26fe AK |
1127 | int me = smp_processor_id(); |
1128 | cpu_set(me, cpu_online_map); | |
1129 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 1130 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
1131 | } |
1132 | ||
a8ab26fe AK |
1133 | /* |
1134 | * Entry point to boot a CPU. | |
a8ab26fe AK |
1135 | */ |
1136 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 1137 | { |
a8ab26fe AK |
1138 | int err; |
1139 | int apicid = cpu_present_to_apicid(cpu); | |
1da177e4 | 1140 | |
a8ab26fe | 1141 | WARN_ON(irqs_disabled()); |
1da177e4 | 1142 | |
a8ab26fe AK |
1143 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
1144 | ||
1145 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
1146 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1147 | printk("__cpu_up: bad cpu %d\n", cpu); | |
1148 | return -EINVAL; | |
1149 | } | |
a8ab26fe | 1150 | |
76e4f660 AR |
1151 | /* |
1152 | * Already booted CPU? | |
1153 | */ | |
1154 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1155 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1156 | return -ENOSYS; | |
1157 | } | |
1158 | ||
884d9e40 | 1159 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
1160 | /* Boot it! */ |
1161 | err = do_boot_cpu(cpu, apicid); | |
1162 | if (err < 0) { | |
a8ab26fe AK |
1163 | Dprintk("do_boot_cpu failed %d\n", err); |
1164 | return err; | |
1da177e4 | 1165 | } |
a8ab26fe | 1166 | |
1da177e4 LT |
1167 | /* Unleash the CPU! */ |
1168 | Dprintk("waiting for cpu %d\n", cpu); | |
1169 | ||
1da177e4 | 1170 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1171 | cpu_relax(); |
76e4f660 AR |
1172 | err = 0; |
1173 | ||
1174 | return err; | |
1da177e4 LT |
1175 | } |
1176 | ||
a8ab26fe AK |
1177 | /* |
1178 | * Finish the SMP boot. | |
1179 | */ | |
e6982c67 | 1180 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1181 | { |
a8ab26fe | 1182 | smp_cleanup_boot(); |
1da177e4 | 1183 | setup_ioapic_dest(); |
75152114 | 1184 | check_nmi_watchdog(); |
a670fad0 | 1185 | time_init_gtod(); |
a8ab26fe | 1186 | } |
76e4f660 AR |
1187 | |
1188 | #ifdef CONFIG_HOTPLUG_CPU | |
1189 | ||
cb0cd8d4 | 1190 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1191 | { |
1192 | int sibling; | |
94605eff | 1193 | struct cpuinfo_x86 *c = cpu_data; |
76e4f660 | 1194 | |
94605eff SS |
1195 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1196 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1197 | /* | |
1198 | * last thread sibling in this cpu core going down | |
1199 | */ | |
1200 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1201 | c[sibling].booted_cores--; | |
1202 | } | |
1203 | ||
76e4f660 AR |
1204 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1205 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
76e4f660 AR |
1206 | cpus_clear(cpu_sibling_map[cpu]); |
1207 | cpus_clear(cpu_core_map[cpu]); | |
f3fa8ebc RS |
1208 | c[cpu].phys_proc_id = 0; |
1209 | c[cpu].cpu_core_id = 0; | |
94605eff | 1210 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1211 | } |
1212 | ||
1213 | void remove_cpu_from_maps(void) | |
1214 | { | |
1215 | int cpu = smp_processor_id(); | |
1216 | ||
1217 | cpu_clear(cpu, cpu_callout_map); | |
1218 | cpu_clear(cpu, cpu_callin_map); | |
1219 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 1220 | clear_node_cpumask(cpu); |
76e4f660 AR |
1221 | } |
1222 | ||
1223 | int __cpu_disable(void) | |
1224 | { | |
1225 | int cpu = smp_processor_id(); | |
1226 | ||
1227 | /* | |
1228 | * Perhaps use cpufreq to drop frequency, but that could go | |
1229 | * into generic code. | |
1230 | * | |
1231 | * We won't take down the boot processor on i386 due to some | |
1232 | * interrupts only being able to be serviced by the BSP. | |
1233 | * Especially so if we're not using an IOAPIC -zwane | |
1234 | */ | |
1235 | if (cpu == 0) | |
1236 | return -EBUSY; | |
1237 | ||
4038f901 SL |
1238 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1239 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1240 | clear_local_APIC(); |
76e4f660 AR |
1241 | |
1242 | /* | |
1243 | * HACK: | |
1244 | * Allow any queued timer interrupts to get serviced | |
1245 | * This is only a temporary solution until we cleanup | |
1246 | * fixup_irqs as we do for IA64. | |
1247 | */ | |
1248 | local_irq_enable(); | |
1249 | mdelay(1); | |
1250 | ||
1251 | local_irq_disable(); | |
1252 | remove_siblinginfo(cpu); | |
1253 | ||
70a0a535 | 1254 | spin_lock(&vector_lock); |
76e4f660 AR |
1255 | /* It's now safe to remove this processor from the online map */ |
1256 | cpu_clear(cpu, cpu_online_map); | |
70a0a535 | 1257 | spin_unlock(&vector_lock); |
76e4f660 AR |
1258 | remove_cpu_from_maps(); |
1259 | fixup_irqs(cpu_online_map); | |
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | void __cpu_die(unsigned int cpu) | |
1264 | { | |
1265 | /* We don't do anything here: idle task is faking death itself. */ | |
1266 | unsigned int i; | |
1267 | ||
1268 | for (i = 0; i < 10; i++) { | |
1269 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1270 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1271 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1272 | if (1 == num_online_cpus()) |
1273 | alternatives_smp_switch(0); | |
76e4f660 | 1274 | return; |
884d9e40 | 1275 | } |
ef6e5253 | 1276 | msleep(100); |
76e4f660 AR |
1277 | } |
1278 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1279 | } | |
1280 | ||
2c8c0e6b | 1281 | static __init int setup_additional_cpus(char *s) |
420f8f68 | 1282 | { |
2c8c0e6b | 1283 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; |
420f8f68 | 1284 | } |
2c8c0e6b | 1285 | early_param("additional_cpus", setup_additional_cpus); |
420f8f68 | 1286 | |
76e4f660 AR |
1287 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1288 | ||
1289 | int __cpu_disable(void) | |
1290 | { | |
1291 | return -ENOSYS; | |
1292 | } | |
1293 | ||
1294 | void __cpu_die(unsigned int cpu) | |
1295 | { | |
1296 | /* We said "no" in __cpu_disable */ | |
1297 | BUG(); | |
1298 | } | |
1299 | #endif /* CONFIG_HOTPLUG_CPU */ |