Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/init.h> |
42 | ||
43 | #include <linux/mm.h> | |
44 | #include <linux/kernel_stat.h> | |
45 | #include <linux/smp_lock.h> | |
1da177e4 LT |
46 | #include <linux/bootmem.h> |
47 | #include <linux/thread_info.h> | |
48 | #include <linux/module.h> | |
1da177e4 LT |
49 | #include <linux/delay.h> |
50 | #include <linux/mc146818rtc.h> | |
a3bc0dbc | 51 | #include <linux/smp.h> |
1eeb66a1 | 52 | #include <linux/kdebug.h> |
a3bc0dbc | 53 | |
1da177e4 LT |
54 | #include <asm/mtrr.h> |
55 | #include <asm/pgalloc.h> | |
56 | #include <asm/desc.h> | |
1da177e4 LT |
57 | #include <asm/tlbflush.h> |
58 | #include <asm/proto.h> | |
75152114 | 59 | #include <asm/nmi.h> |
9cdd304b AV |
60 | #include <asm/irq.h> |
61 | #include <asm/hw_irq.h> | |
488fc08d | 62 | #include <asm/numa.h> |
1da177e4 LT |
63 | |
64 | /* Number of siblings per CPU package */ | |
65 | int smp_num_siblings = 1; | |
2ee60e17 | 66 | EXPORT_SYMBOL(smp_num_siblings); |
1da177e4 | 67 | |
1e9f28fa SS |
68 | /* Last level cache ID of each logical CPU */ |
69 | u8 cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
70 | ||
1da177e4 | 71 | /* Bitmask of currently online CPUs */ |
6c231b7b | 72 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 73 | |
a8ab26fe AK |
74 | EXPORT_SYMBOL(cpu_online_map); |
75 | ||
76 | /* | |
77 | * Private maps to synchronize booting between AP and BP. | |
78 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
79 | */ | |
1da177e4 LT |
80 | cpumask_t cpu_callin_map; |
81 | cpumask_t cpu_callout_map; | |
2ee60e17 | 82 | EXPORT_SYMBOL(cpu_callout_map); |
a8ab26fe AK |
83 | |
84 | cpumask_t cpu_possible_map; | |
85 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
86 | |
87 | /* Per CPU bogomips and other parameters */ | |
88 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
2ee60e17 | 89 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 90 | |
a8ab26fe AK |
91 | /* Set when the idlers are all forked */ |
92 | int smp_threads_ready; | |
93 | ||
94605eff | 94 | /* representing HT siblings of each logical CPU */ |
6c231b7b | 95 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
2ee60e17 | 96 | EXPORT_SYMBOL(cpu_sibling_map); |
94605eff SS |
97 | |
98 | /* representing HT and core siblings of each logical CPU */ | |
6c231b7b | 99 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
2df9fa36 | 100 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
101 | |
102 | /* | |
103 | * Trampoline 80x86 program as an array. | |
104 | */ | |
105 | ||
a8ab26fe AK |
106 | extern unsigned char trampoline_data[]; |
107 | extern unsigned char trampoline_end[]; | |
1da177e4 | 108 | |
76e4f660 AR |
109 | /* State of each CPU */ |
110 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
111 | ||
112 | /* | |
113 | * Store all idle threads, this can be reused instead of creating | |
114 | * a new thread. Also avoids complicated thread destroy functionality | |
115 | * for idle threads. | |
116 | */ | |
117 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
118 | ||
119 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
120 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
121 | ||
1da177e4 LT |
122 | /* |
123 | * Currently trivial. Write the real->protected mode | |
124 | * bootstrap into the page concerned. The caller | |
125 | * has made sure it's suitably aligned. | |
126 | */ | |
127 | ||
a8ab26fe | 128 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
129 | { |
130 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
131 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
132 | return virt_to_phys(tramp); | |
133 | } | |
134 | ||
135 | /* | |
136 | * The bootstrap kernel entry code has set these up. Save them for | |
137 | * a given CPU | |
138 | */ | |
139 | ||
a8ab26fe | 140 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
141 | { |
142 | struct cpuinfo_x86 *c = cpu_data + id; | |
143 | ||
144 | *c = boot_cpu_data; | |
145 | identify_cpu(c); | |
dda50e71 | 146 | print_cpu_info(c); |
1da177e4 LT |
147 | } |
148 | ||
a8ab26fe | 149 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 150 | |
a8ab26fe AK |
151 | /* |
152 | * Report back to the Boot Processor. | |
153 | * Running on AP. | |
154 | */ | |
155 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
156 | { |
157 | int cpuid, phys_id; | |
158 | unsigned long timeout; | |
159 | ||
160 | /* | |
161 | * If waken up by an INIT in an 82489DX configuration | |
162 | * we may get here before an INIT-deassert IPI reaches | |
163 | * our local APIC. We have to wait for the IPI or we'll | |
164 | * lock up on an APIC access. | |
165 | */ | |
a8ab26fe AK |
166 | while (!atomic_read(&init_deasserted)) |
167 | cpu_relax(); | |
1da177e4 LT |
168 | |
169 | /* | |
170 | * (This works even if the APIC is not enabled.) | |
171 | */ | |
172 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
173 | cpuid = smp_processor_id(); | |
174 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
175 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
176 | phys_id, cpuid); | |
177 | } | |
178 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
179 | ||
180 | /* | |
181 | * STARTUP IPIs are fragile beasts as they might sometimes | |
182 | * trigger some glue motherboard logic. Complete APIC bus | |
183 | * silence for 1 second, this overestimates the time the | |
184 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
185 | * by a factor of two. This should be enough. | |
186 | */ | |
187 | ||
188 | /* | |
189 | * Waiting 2s total for startup (udelay is not yet working) | |
190 | */ | |
191 | timeout = jiffies + 2*HZ; | |
192 | while (time_before(jiffies, timeout)) { | |
193 | /* | |
194 | * Has the boot CPU finished it's STARTUP sequence? | |
195 | */ | |
196 | if (cpu_isset(cpuid, cpu_callout_map)) | |
197 | break; | |
a8ab26fe | 198 | cpu_relax(); |
1da177e4 LT |
199 | } |
200 | ||
201 | if (!time_before(jiffies, timeout)) { | |
202 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
203 | cpuid); | |
204 | } | |
205 | ||
206 | /* | |
207 | * the boot CPU has finished the init stage and is spinning | |
208 | * on callin_map until we finish. We are free to set up this | |
209 | * CPU, first the APIC. (this is probably redundant on most | |
210 | * boards) | |
211 | */ | |
212 | ||
213 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
214 | setup_local_APIC(); | |
215 | ||
1da177e4 LT |
216 | /* |
217 | * Get our bogomips. | |
b4452218 AK |
218 | * |
219 | * Need to enable IRQs because it can take longer and then | |
220 | * the NMI watchdog might kill us. | |
1da177e4 | 221 | */ |
b4452218 | 222 | local_irq_enable(); |
1da177e4 | 223 | calibrate_delay(); |
b4452218 | 224 | local_irq_disable(); |
1da177e4 LT |
225 | Dprintk("Stack at about %p\n",&cpuid); |
226 | ||
227 | disable_APIC_timer(); | |
228 | ||
229 | /* | |
230 | * Save our processor parameters | |
231 | */ | |
232 | smp_store_cpu_info(cpuid); | |
233 | ||
1da177e4 LT |
234 | /* |
235 | * Allow the master to continue. | |
236 | */ | |
237 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
238 | } |
239 | ||
1e9f28fa SS |
240 | /* maps the cpu to the sched domain representing multi-core */ |
241 | cpumask_t cpu_coregroup_map(int cpu) | |
242 | { | |
243 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
244 | /* | |
245 | * For perf, we return last level cache shared map. | |
5c45bf27 | 246 | * And for power savings, we return cpu_core_map |
1e9f28fa | 247 | */ |
5c45bf27 SS |
248 | if (sched_mc_power_savings || sched_smt_power_savings) |
249 | return cpu_core_map[cpu]; | |
250 | else | |
251 | return c->llc_shared_map; | |
1e9f28fa SS |
252 | } |
253 | ||
94605eff SS |
254 | /* representing cpus for which sibling maps can be computed */ |
255 | static cpumask_t cpu_sibling_setup_map; | |
256 | ||
cb0cd8d4 AR |
257 | static inline void set_cpu_sibling_map(int cpu) |
258 | { | |
259 | int i; | |
94605eff SS |
260 | struct cpuinfo_x86 *c = cpu_data; |
261 | ||
262 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
263 | |
264 | if (smp_num_siblings > 1) { | |
94605eff | 265 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
f3fa8ebc RS |
266 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
267 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
cb0cd8d4 AR |
268 | cpu_set(i, cpu_sibling_map[cpu]); |
269 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
270 | cpu_set(i, cpu_core_map[cpu]); |
271 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
272 | cpu_set(i, c[cpu].llc_shared_map); |
273 | cpu_set(cpu, c[i].llc_shared_map); | |
cb0cd8d4 AR |
274 | } |
275 | } | |
276 | } else { | |
277 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
278 | } | |
279 | ||
1e9f28fa SS |
280 | cpu_set(cpu, c[cpu].llc_shared_map); |
281 | ||
94605eff | 282 | if (current_cpu_data.x86_max_cores == 1) { |
cb0cd8d4 | 283 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
284 | c[cpu].booted_cores = 1; |
285 | return; | |
286 | } | |
287 | ||
288 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
289 | if (cpu_llc_id[cpu] != BAD_APICID && |
290 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
291 | cpu_set(i, c[cpu].llc_shared_map); | |
292 | cpu_set(cpu, c[i].llc_shared_map); | |
293 | } | |
f3fa8ebc | 294 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
295 | cpu_set(i, cpu_core_map[cpu]); |
296 | cpu_set(cpu, cpu_core_map[i]); | |
297 | /* | |
298 | * Does this new cpu bringup a new core? | |
299 | */ | |
300 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
301 | /* | |
302 | * for each core in package, increment | |
303 | * the booted_cores for this new cpu | |
304 | */ | |
305 | if (first_cpu(cpu_sibling_map[i]) == i) | |
306 | c[cpu].booted_cores++; | |
307 | /* | |
308 | * increment the core count for all | |
309 | * the other cpus in this package | |
310 | */ | |
311 | if (i != cpu) | |
312 | c[i].booted_cores++; | |
313 | } else if (i != cpu && !c[cpu].booted_cores) | |
314 | c[cpu].booted_cores = c[i].booted_cores; | |
315 | } | |
cb0cd8d4 AR |
316 | } |
317 | } | |
318 | ||
1da177e4 | 319 | /* |
a8ab26fe | 320 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 321 | */ |
a8ab26fe | 322 | void __cpuinit start_secondary(void) |
1da177e4 LT |
323 | { |
324 | /* | |
325 | * Dont put anything before smp_callin(), SMP | |
326 | * booting is too fragile that we want to limit the | |
327 | * things done here to the most necessary things. | |
328 | */ | |
329 | cpu_init(); | |
5bfb5d69 | 330 | preempt_disable(); |
1da177e4 LT |
331 | smp_callin(); |
332 | ||
333 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
334 | barrier(); | |
335 | ||
95492e46 IM |
336 | /* |
337 | * Check TSC sync first: | |
338 | */ | |
339 | check_tsc_sync_target(); | |
340 | ||
1da177e4 LT |
341 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
342 | setup_secondary_APIC_clock(); | |
343 | ||
a8ab26fe | 344 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
345 | |
346 | if (nmi_watchdog == NMI_IO_APIC) { | |
347 | disable_8259A_irq(0); | |
348 | enable_NMI_through_LVT0(NULL); | |
349 | enable_8259A_irq(0); | |
350 | } | |
351 | ||
a8ab26fe | 352 | enable_APIC_timer(); |
1da177e4 | 353 | |
cb0cd8d4 AR |
354 | /* |
355 | * The sibling maps must be set before turing the online map on for | |
356 | * this cpu | |
357 | */ | |
358 | set_cpu_sibling_map(smp_processor_id()); | |
359 | ||
884d9e40 AR |
360 | /* |
361 | * We need to hold call_lock, so there is no inconsistency | |
362 | * between the time smp_call_function() determines number of | |
363 | * IPI receipients, and the time when the determination is made | |
364 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
365 | * lock helps us to not include this cpu in a currently in progress | |
366 | * smp_call_function(). | |
367 | */ | |
368 | lock_ipi_call_lock(); | |
70a0a535 | 369 | spin_lock(&vector_lock); |
884d9e40 | 370 | |
70a0a535 EB |
371 | /* Setup the per cpu irq handling data structures */ |
372 | __setup_vector_irq(smp_processor_id()); | |
1da177e4 | 373 | /* |
a8ab26fe | 374 | * Allow the master to continue. |
1da177e4 | 375 | */ |
1da177e4 | 376 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 | 377 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
70a0a535 | 378 | spin_unlock(&vector_lock); |
95492e46 | 379 | |
884d9e40 AR |
380 | unlock_ipi_call_lock(); |
381 | ||
1da177e4 LT |
382 | cpu_idle(); |
383 | } | |
384 | ||
a8ab26fe | 385 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
386 | extern void (*initial_code)(void); |
387 | ||
44456d37 | 388 | #ifdef APIC_DEBUG |
a8ab26fe | 389 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
390 | { |
391 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
392 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
3144c332 FLV |
393 | int timeout; |
394 | unsigned int status; | |
1da177e4 LT |
395 | |
396 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
397 | ||
398 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
399 | printk("... APIC #%d %s: ", apicid, names[i]); | |
400 | ||
401 | /* | |
402 | * Wait for idle. | |
403 | */ | |
3144c332 FLV |
404 | status = safe_apic_wait_icr_idle(); |
405 | if (status) | |
406 | printk("a previous APIC delivery may have failed\n"); | |
1da177e4 | 407 | |
c1507eb2 AK |
408 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
409 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
410 | |
411 | timeout = 0; | |
412 | do { | |
413 | udelay(100); | |
414 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
415 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
416 | ||
417 | switch (status) { | |
418 | case APIC_ICR_RR_VALID: | |
419 | status = apic_read(APIC_RRR); | |
420 | printk("%08x\n", status); | |
421 | break; | |
422 | default: | |
423 | printk("failed\n"); | |
424 | } | |
425 | } | |
426 | } | |
427 | #endif | |
428 | ||
a8ab26fe AK |
429 | /* |
430 | * Kick the secondary to wake up. | |
431 | */ | |
432 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 | 433 | { |
ea8c733b FLV |
434 | unsigned long send_status, accept_status = 0; |
435 | int maxlvt, num_starts, j; | |
1da177e4 LT |
436 | |
437 | Dprintk("Asserting INIT.\n"); | |
438 | ||
439 | /* | |
440 | * Turn INIT on target chip | |
441 | */ | |
c1507eb2 | 442 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
443 | |
444 | /* | |
445 | * Send IPI | |
446 | */ | |
c1507eb2 | 447 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
448 | | APIC_DM_INIT); |
449 | ||
450 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 451 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
452 | |
453 | mdelay(10); | |
454 | ||
455 | Dprintk("Deasserting INIT.\n"); | |
456 | ||
457 | /* Target chip */ | |
c1507eb2 | 458 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
459 | |
460 | /* Send IPI */ | |
c1507eb2 | 461 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
462 | |
463 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 464 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 | 465 | |
f2ecfab9 | 466 | mb(); |
1da177e4 LT |
467 | atomic_set(&init_deasserted, 1); |
468 | ||
5a40b7c2 | 469 | num_starts = 2; |
1da177e4 LT |
470 | |
471 | /* | |
472 | * Run STARTUP IPI loop. | |
473 | */ | |
474 | Dprintk("#startup loops: %d.\n", num_starts); | |
475 | ||
476 | maxlvt = get_maxlvt(); | |
477 | ||
478 | for (j = 1; j <= num_starts; j++) { | |
479 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
480 | apic_write(APIC_ESR, 0); |
481 | apic_read(APIC_ESR); | |
482 | Dprintk("After apic_write.\n"); | |
483 | ||
484 | /* | |
485 | * STARTUP IPI | |
486 | */ | |
487 | ||
488 | /* Target chip */ | |
c1507eb2 | 489 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
490 | |
491 | /* Boot on the stack */ | |
492 | /* Kick the second */ | |
c1507eb2 | 493 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
494 | |
495 | /* | |
496 | * Give the other CPU some time to accept the IPI. | |
497 | */ | |
498 | udelay(300); | |
499 | ||
500 | Dprintk("Startup point 1.\n"); | |
501 | ||
502 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 503 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
504 | |
505 | /* | |
506 | * Give the other CPU some time to accept the IPI. | |
507 | */ | |
508 | udelay(200); | |
509 | /* | |
510 | * Due to the Pentium erratum 3AP. | |
511 | */ | |
512 | if (maxlvt > 3) { | |
1da177e4 LT |
513 | apic_write(APIC_ESR, 0); |
514 | } | |
515 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
516 | if (send_status || accept_status) | |
517 | break; | |
518 | } | |
519 | Dprintk("After Startup.\n"); | |
520 | ||
521 | if (send_status) | |
522 | printk(KERN_ERR "APIC never delivered???\n"); | |
523 | if (accept_status) | |
524 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
525 | ||
526 | return (send_status | accept_status); | |
527 | } | |
528 | ||
76e4f660 | 529 | struct create_idle { |
65f27f38 | 530 | struct work_struct work; |
76e4f660 AR |
531 | struct task_struct *idle; |
532 | struct completion done; | |
533 | int cpu; | |
534 | }; | |
535 | ||
65f27f38 | 536 | void do_fork_idle(struct work_struct *work) |
76e4f660 | 537 | { |
65f27f38 DH |
538 | struct create_idle *c_idle = |
539 | container_of(work, struct create_idle, work); | |
76e4f660 AR |
540 | |
541 | c_idle->idle = fork_idle(c_idle->cpu); | |
542 | complete(&c_idle->done); | |
543 | } | |
544 | ||
a8ab26fe AK |
545 | /* |
546 | * Boot one CPU. | |
547 | */ | |
548 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 549 | { |
1da177e4 | 550 | unsigned long boot_error; |
a8ab26fe | 551 | int timeout; |
1da177e4 | 552 | unsigned long start_rip; |
76e4f660 | 553 | struct create_idle c_idle = { |
65f27f38 | 554 | .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle), |
76e4f660 | 555 | .cpu = cpu, |
f86bf9b7 | 556 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), |
76e4f660 | 557 | }; |
76e4f660 | 558 | |
c11efdf9 RT |
559 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
560 | if (!cpu_gdt_descr[cpu].address && | |
561 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
562 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
563 | return -1; | |
564 | } | |
565 | ||
365ba917 RT |
566 | /* Allocate node local memory for AP pdas */ |
567 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
568 | struct x8664_pda *newpda, *pda; | |
569 | int node = cpu_to_node(cpu); | |
570 | pda = cpu_pda(cpu); | |
571 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
572 | node); | |
573 | if (newpda) { | |
574 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
575 | cpu_pda(cpu) = newpda; | |
576 | } else | |
577 | printk(KERN_ERR | |
578 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
579 | cpu, node); | |
580 | } | |
581 | ||
d167a518 GH |
582 | alternatives_smp_switch(1); |
583 | ||
76e4f660 AR |
584 | c_idle.idle = get_idle_for_cpu(cpu); |
585 | ||
586 | if (c_idle.idle) { | |
587 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
57eafdc2 | 588 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
589 | init_idle(c_idle.idle, cpu); |
590 | goto do_rest; | |
591 | } | |
592 | ||
1da177e4 | 593 | /* |
76e4f660 AR |
594 | * During cold boot process, keventd thread is not spun up yet. |
595 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
596 | * not acquire any attributes from the calling context. Hence the clean | |
597 | * way to create kernel_threads() is to do that from keventd(). | |
598 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
599 | * was also queuing to keventd() and when the caller is already running | |
600 | * in context of keventd(), we would end up with locking up the keventd | |
601 | * thread. | |
1da177e4 | 602 | */ |
76e4f660 | 603 | if (!keventd_up() || current_is_keventd()) |
65f27f38 | 604 | c_idle.work.func(&c_idle.work); |
76e4f660 | 605 | else { |
65f27f38 | 606 | schedule_work(&c_idle.work); |
76e4f660 AR |
607 | wait_for_completion(&c_idle.done); |
608 | } | |
609 | ||
610 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 611 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 612 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 613 | } |
1da177e4 | 614 | |
76e4f660 AR |
615 | set_idle_for_cpu(cpu, c_idle.idle); |
616 | ||
617 | do_rest: | |
618 | ||
df79efde | 619 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
620 | |
621 | start_rip = setup_trampoline(); | |
622 | ||
76e4f660 | 623 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
624 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
625 | initial_code = start_secondary; | |
e4f17c43 | 626 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 627 | |
de04f322 AK |
628 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
629 | cpus_weight(cpu_present_map), | |
630 | apicid); | |
1da177e4 LT |
631 | |
632 | /* | |
633 | * This grunge runs the startup process for | |
634 | * the targeted processor. | |
635 | */ | |
636 | ||
637 | atomic_set(&init_deasserted, 0); | |
638 | ||
639 | Dprintk("Setting warm reset code and vector.\n"); | |
640 | ||
641 | CMOS_WRITE(0xa, 0xf); | |
642 | local_flush_tlb(); | |
643 | Dprintk("1.\n"); | |
644 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
645 | Dprintk("2.\n"); | |
646 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
647 | Dprintk("3.\n"); | |
648 | ||
649 | /* | |
650 | * Be paranoid about clearing APIC errors. | |
651 | */ | |
11a8e778 AK |
652 | apic_write(APIC_ESR, 0); |
653 | apic_read(APIC_ESR); | |
1da177e4 LT |
654 | |
655 | /* | |
656 | * Status is now clean | |
657 | */ | |
658 | boot_error = 0; | |
659 | ||
660 | /* | |
661 | * Starting actual IPI sequence... | |
662 | */ | |
a8ab26fe | 663 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
664 | |
665 | if (!boot_error) { | |
666 | /* | |
667 | * allow APs to start initializing. | |
668 | */ | |
669 | Dprintk("Before Callout %d.\n", cpu); | |
670 | cpu_set(cpu, cpu_callout_map); | |
671 | Dprintk("After Callout %d.\n", cpu); | |
672 | ||
673 | /* | |
674 | * Wait 5s total for a response | |
675 | */ | |
676 | for (timeout = 0; timeout < 50000; timeout++) { | |
677 | if (cpu_isset(cpu, cpu_callin_map)) | |
678 | break; /* It has booted */ | |
679 | udelay(100); | |
680 | } | |
681 | ||
682 | if (cpu_isset(cpu, cpu_callin_map)) { | |
683 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
684 | Dprintk("CPU has booted.\n"); |
685 | } else { | |
686 | boot_error = 1; | |
687 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
688 | == 0xA5) | |
689 | /* trampoline started but...? */ | |
690 | printk("Stuck ??\n"); | |
691 | else | |
692 | /* trampoline code not run */ | |
693 | printk("Not responding.\n"); | |
44456d37 | 694 | #ifdef APIC_DEBUG |
1da177e4 LT |
695 | inquire_remote_apic(apicid); |
696 | #endif | |
697 | } | |
698 | } | |
699 | if (boot_error) { | |
700 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
701 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 702 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
703 | cpu_clear(cpu, cpu_present_map); |
704 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
705 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
706 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 707 | return -EIO; |
1da177e4 | 708 | } |
a8ab26fe AK |
709 | |
710 | return 0; | |
1da177e4 LT |
711 | } |
712 | ||
a8ab26fe AK |
713 | cycles_t cacheflush_time; |
714 | unsigned long cache_decay_ticks; | |
715 | ||
1da177e4 | 716 | /* |
a8ab26fe | 717 | * Cleanup possible dangling ends... |
1da177e4 | 718 | */ |
a8ab26fe | 719 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 720 | { |
a8ab26fe AK |
721 | /* |
722 | * Paranoid: Set warm reset code and vector here back | |
723 | * to default values. | |
724 | */ | |
725 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 726 | |
a8ab26fe AK |
727 | /* |
728 | * Reset trampoline flag | |
729 | */ | |
730 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
731 | } |
732 | ||
733 | /* | |
734 | * Fall back to non SMP mode after errors. | |
735 | * | |
736 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
737 | */ | |
e6982c67 | 738 | static __init void disable_smp(void) |
a8ab26fe AK |
739 | { |
740 | cpu_present_map = cpumask_of_cpu(0); | |
741 | cpu_possible_map = cpumask_of_cpu(0); | |
742 | if (smp_found_config) | |
743 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
744 | else | |
745 | phys_cpu_present_map = physid_mask_of_physid(0); | |
746 | cpu_set(0, cpu_sibling_map[0]); | |
747 | cpu_set(0, cpu_core_map[0]); | |
748 | } | |
749 | ||
61b1b2d0 | 750 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
751 | |
752 | int additional_cpus __initdata = -1; | |
753 | ||
61b1b2d0 AK |
754 | /* |
755 | * cpu_possible_map should be static, it cannot change as cpu's | |
756 | * are onlined, or offlined. The reason is per-cpu data-structures | |
757 | * are allocated by some modules at init time, and dont expect to | |
758 | * do this dynamically on cpu arrival/departure. | |
759 | * cpu_present_map on the other hand can change dynamically. | |
760 | * In case when cpu_hotplug is not compiled, then we resort to current | |
761 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 762 | * - Ashok Raj |
420f8f68 AK |
763 | * |
764 | * Three ways to find out the number of additional hotplug CPUs: | |
765 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 766 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 767 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
768 | * We do this because additional CPUs waste a lot of memory. |
769 | * -AK | |
61b1b2d0 | 770 | */ |
421c7ce6 | 771 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
772 | { |
773 | int i; | |
420f8f68 AK |
774 | int possible; |
775 | ||
776 | if (additional_cpus == -1) { | |
f62a91f6 | 777 | if (disabled_cpus > 0) |
420f8f68 | 778 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
779 | else |
780 | additional_cpus = 0; | |
420f8f68 AK |
781 | } |
782 | possible = num_processors + additional_cpus; | |
783 | if (possible > NR_CPUS) | |
784 | possible = NR_CPUS; | |
785 | ||
786 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
787 | possible, | |
788 | max_t(int, possible - num_processors, 0)); | |
789 | ||
790 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
791 | cpu_set(i, cpu_possible_map); |
792 | } | |
793 | #endif | |
794 | ||
a8ab26fe AK |
795 | /* |
796 | * Various sanity checks. | |
797 | */ | |
e6982c67 | 798 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 799 | { |
1da177e4 LT |
800 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
801 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
802 | hard_smp_processor_id()); | |
803 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
804 | } | |
805 | ||
806 | /* | |
807 | * If we couldn't find an SMP configuration at boot time, | |
808 | * get out of here now! | |
809 | */ | |
810 | if (!smp_found_config) { | |
811 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 812 | disable_smp(); |
1da177e4 LT |
813 | if (APIC_init_uniprocessor()) |
814 | printk(KERN_NOTICE "Local APIC not detected." | |
815 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 816 | return -1; |
1da177e4 LT |
817 | } |
818 | ||
819 | /* | |
820 | * Should not be necessary because the MP table should list the boot | |
821 | * CPU too, but we do it for the sake of robustness anyway. | |
822 | */ | |
823 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
824 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
825 | boot_cpu_id); | |
826 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
827 | } | |
828 | ||
829 | /* | |
830 | * If we couldn't find a local APIC, then get out of here now! | |
831 | */ | |
11a8e778 | 832 | if (!cpu_has_apic) { |
1da177e4 LT |
833 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
834 | boot_cpu_id); | |
835 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
836 | nr_ioapics = 0; |
837 | return -1; | |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 LT |
840 | /* |
841 | * If SMP should be disabled, then really disable it! | |
842 | */ | |
843 | if (!max_cpus) { | |
1da177e4 | 844 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
845 | nr_ioapics = 0; |
846 | return -1; | |
1da177e4 LT |
847 | } |
848 | ||
a8ab26fe AK |
849 | return 0; |
850 | } | |
1da177e4 | 851 | |
a8ab26fe AK |
852 | /* |
853 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
854 | * earlier. Just do some sanity checking here and enable APIC mode. | |
855 | */ | |
e6982c67 | 856 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 857 | { |
a8ab26fe AK |
858 | nmi_watchdog_default(); |
859 | current_cpu_data = boot_cpu_data; | |
860 | current_thread_info()->cpu = 0; /* needed? */ | |
94605eff | 861 | set_cpu_sibling_map(0); |
1da177e4 | 862 | |
a8ab26fe AK |
863 | if (smp_sanity_check(max_cpus) < 0) { |
864 | printk(KERN_INFO "SMP disabled\n"); | |
865 | disable_smp(); | |
866 | return; | |
1da177e4 LT |
867 | } |
868 | ||
a8ab26fe | 869 | |
1da177e4 | 870 | /* |
a8ab26fe | 871 | * Switch from PIC to APIC mode. |
1da177e4 | 872 | */ |
a8ab26fe | 873 | setup_local_APIC(); |
1da177e4 | 874 | |
a8ab26fe AK |
875 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
876 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
877 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
878 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 879 | } |
1da177e4 LT |
880 | |
881 | /* | |
a8ab26fe | 882 | * Now start the IO-APICs |
1da177e4 LT |
883 | */ |
884 | if (!skip_ioapic_setup && nr_ioapics) | |
885 | setup_IO_APIC(); | |
886 | else | |
887 | nr_ioapics = 0; | |
888 | ||
1da177e4 | 889 | /* |
a8ab26fe | 890 | * Set up local APIC timer on boot CPU. |
1da177e4 | 891 | */ |
1da177e4 | 892 | |
a8ab26fe | 893 | setup_boot_APIC_clock(); |
1da177e4 LT |
894 | } |
895 | ||
a8ab26fe AK |
896 | /* |
897 | * Early setup to make printk work. | |
898 | */ | |
899 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 900 | { |
a8ab26fe AK |
901 | int me = smp_processor_id(); |
902 | cpu_set(me, cpu_online_map); | |
903 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 904 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
905 | } |
906 | ||
a8ab26fe AK |
907 | /* |
908 | * Entry point to boot a CPU. | |
a8ab26fe AK |
909 | */ |
910 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 911 | { |
a8ab26fe | 912 | int apicid = cpu_present_to_apicid(cpu); |
d04f41e3 IM |
913 | unsigned long flags; |
914 | int err; | |
1da177e4 | 915 | |
a8ab26fe | 916 | WARN_ON(irqs_disabled()); |
1da177e4 | 917 | |
a8ab26fe AK |
918 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
919 | ||
920 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
921 | !physid_isset(apicid, phys_cpu_present_map)) { | |
922 | printk("__cpu_up: bad cpu %d\n", cpu); | |
923 | return -EINVAL; | |
924 | } | |
a8ab26fe | 925 | |
76e4f660 AR |
926 | /* |
927 | * Already booted CPU? | |
928 | */ | |
929 | if (cpu_isset(cpu, cpu_callin_map)) { | |
930 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
931 | return -ENOSYS; | |
932 | } | |
933 | ||
2b1f6278 BK |
934 | /* |
935 | * Save current MTRR state in case it was changed since early boot | |
936 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
937 | */ | |
938 | mtrr_save_state(); | |
939 | ||
884d9e40 | 940 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
941 | /* Boot it! */ |
942 | err = do_boot_cpu(cpu, apicid); | |
943 | if (err < 0) { | |
a8ab26fe AK |
944 | Dprintk("do_boot_cpu failed %d\n", err); |
945 | return err; | |
1da177e4 | 946 | } |
a8ab26fe | 947 | |
1da177e4 LT |
948 | /* Unleash the CPU! */ |
949 | Dprintk("waiting for cpu %d\n", cpu); | |
950 | ||
95492e46 IM |
951 | /* |
952 | * Make sure and check TSC sync: | |
953 | */ | |
d04f41e3 | 954 | local_irq_save(flags); |
95492e46 | 955 | check_tsc_sync_source(cpu); |
d04f41e3 | 956 | local_irq_restore(flags); |
95492e46 | 957 | |
1da177e4 | 958 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 959 | cpu_relax(); |
76e4f660 AR |
960 | err = 0; |
961 | ||
962 | return err; | |
1da177e4 LT |
963 | } |
964 | ||
a8ab26fe AK |
965 | /* |
966 | * Finish the SMP boot. | |
967 | */ | |
e6982c67 | 968 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 969 | { |
a8ab26fe | 970 | smp_cleanup_boot(); |
1da177e4 | 971 | setup_ioapic_dest(); |
75152114 | 972 | check_nmi_watchdog(); |
a8ab26fe | 973 | } |
76e4f660 AR |
974 | |
975 | #ifdef CONFIG_HOTPLUG_CPU | |
976 | ||
cb0cd8d4 | 977 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
978 | { |
979 | int sibling; | |
94605eff | 980 | struct cpuinfo_x86 *c = cpu_data; |
76e4f660 | 981 | |
94605eff SS |
982 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
983 | cpu_clear(cpu, cpu_core_map[sibling]); | |
984 | /* | |
985 | * last thread sibling in this cpu core going down | |
986 | */ | |
987 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
988 | c[sibling].booted_cores--; | |
989 | } | |
990 | ||
76e4f660 AR |
991 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
992 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
76e4f660 AR |
993 | cpus_clear(cpu_sibling_map[cpu]); |
994 | cpus_clear(cpu_core_map[cpu]); | |
f3fa8ebc RS |
995 | c[cpu].phys_proc_id = 0; |
996 | c[cpu].cpu_core_id = 0; | |
94605eff | 997 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
998 | } |
999 | ||
1000 | void remove_cpu_from_maps(void) | |
1001 | { | |
1002 | int cpu = smp_processor_id(); | |
1003 | ||
1004 | cpu_clear(cpu, cpu_callout_map); | |
1005 | cpu_clear(cpu, cpu_callin_map); | |
1006 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 1007 | clear_node_cpumask(cpu); |
76e4f660 AR |
1008 | } |
1009 | ||
1010 | int __cpu_disable(void) | |
1011 | { | |
1012 | int cpu = smp_processor_id(); | |
1013 | ||
1014 | /* | |
1015 | * Perhaps use cpufreq to drop frequency, but that could go | |
1016 | * into generic code. | |
1017 | * | |
1018 | * We won't take down the boot processor on i386 due to some | |
1019 | * interrupts only being able to be serviced by the BSP. | |
1020 | * Especially so if we're not using an IOAPIC -zwane | |
1021 | */ | |
1022 | if (cpu == 0) | |
1023 | return -EBUSY; | |
1024 | ||
4038f901 SL |
1025 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1026 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1027 | clear_local_APIC(); |
76e4f660 AR |
1028 | |
1029 | /* | |
1030 | * HACK: | |
1031 | * Allow any queued timer interrupts to get serviced | |
1032 | * This is only a temporary solution until we cleanup | |
1033 | * fixup_irqs as we do for IA64. | |
1034 | */ | |
1035 | local_irq_enable(); | |
1036 | mdelay(1); | |
1037 | ||
1038 | local_irq_disable(); | |
1039 | remove_siblinginfo(cpu); | |
1040 | ||
70a0a535 | 1041 | spin_lock(&vector_lock); |
76e4f660 AR |
1042 | /* It's now safe to remove this processor from the online map */ |
1043 | cpu_clear(cpu, cpu_online_map); | |
70a0a535 | 1044 | spin_unlock(&vector_lock); |
76e4f660 AR |
1045 | remove_cpu_from_maps(); |
1046 | fixup_irqs(cpu_online_map); | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | void __cpu_die(unsigned int cpu) | |
1051 | { | |
1052 | /* We don't do anything here: idle task is faking death itself. */ | |
1053 | unsigned int i; | |
1054 | ||
1055 | for (i = 0; i < 10; i++) { | |
1056 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1057 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1058 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1059 | if (1 == num_online_cpus()) |
1060 | alternatives_smp_switch(0); | |
76e4f660 | 1061 | return; |
884d9e40 | 1062 | } |
ef6e5253 | 1063 | msleep(100); |
76e4f660 AR |
1064 | } |
1065 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1066 | } | |
1067 | ||
2c8c0e6b | 1068 | static __init int setup_additional_cpus(char *s) |
420f8f68 | 1069 | { |
2c8c0e6b | 1070 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; |
420f8f68 | 1071 | } |
2c8c0e6b | 1072 | early_param("additional_cpus", setup_additional_cpus); |
420f8f68 | 1073 | |
76e4f660 AR |
1074 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1075 | ||
1076 | int __cpu_disable(void) | |
1077 | { | |
1078 | return -ENOSYS; | |
1079 | } | |
1080 | ||
1081 | void __cpu_die(unsigned int cpu) | |
1082 | { | |
1083 | /* We said "no" in __cpu_disable */ | |
1084 | BUG(); | |
1085 | } | |
1086 | #endif /* CONFIG_HOTPLUG_CPU */ |