Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * X86-64 specific CPU setup. | |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * Copyright 2001, 2002, 2003 SuSE Labs / Andi Kleen. | |
5 | * See setup.c for older changelog. | |
1da177e4 | 6 | */ |
1da177e4 LT |
7 | #include <linux/init.h> |
8 | #include <linux/kernel.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/string.h> | |
11 | #include <linux/bootmem.h> | |
12 | #include <linux/bitops.h> | |
a940199f | 13 | #include <linux/module.h> |
f9ba7053 | 14 | #include <asm/bootsetup.h> |
1da177e4 LT |
15 | #include <asm/pda.h> |
16 | #include <asm/pgtable.h> | |
17 | #include <asm/processor.h> | |
18 | #include <asm/desc.h> | |
19 | #include <asm/atomic.h> | |
20 | #include <asm/mmu_context.h> | |
21 | #include <asm/smp.h> | |
22 | #include <asm/i387.h> | |
23 | #include <asm/percpu.h> | |
1da177e4 | 24 | #include <asm/proto.h> |
a940199f | 25 | #include <asm/sections.h> |
1da177e4 | 26 | |
2717941c | 27 | char x86_boot_params[BOOT_PARAM_SIZE] __initdata; |
1da177e4 | 28 | |
e6982c67 | 29 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 30 | |
365ba917 | 31 | struct x8664_pda *_cpu_pda[NR_CPUS] __read_mostly; |
2ee60e17 | 32 | EXPORT_SYMBOL(_cpu_pda); |
365ba917 | 33 | struct x8664_pda boot_cpu_pda[NR_CPUS] __cacheline_aligned; |
1da177e4 | 34 | |
e57113bc | 35 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
1da177e4 LT |
36 | |
37 | char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned"))); | |
38 | ||
6c231b7b | 39 | unsigned long __supported_pte_mask __read_mostly = ~0UL; |
2ee60e17 | 40 | EXPORT_SYMBOL(__supported_pte_mask); |
142a64a6 | 41 | static int do_not_nx __cpuinitdata = 0; |
1da177e4 LT |
42 | |
43 | /* noexec=on|off | |
44 | Control non executable mappings for 64bit processes. | |
45 | ||
46 | on Enable(default) | |
47 | off Disable | |
48 | */ | |
2c8c0e6b | 49 | static int __init nonx_setup(char *str) |
1da177e4 | 50 | { |
2c8c0e6b AK |
51 | if (!str) |
52 | return -EINVAL; | |
1da177e4 LT |
53 | if (!strncmp(str, "on", 2)) { |
54 | __supported_pte_mask |= _PAGE_NX; | |
55 | do_not_nx = 0; | |
56 | } else if (!strncmp(str, "off", 3)) { | |
57 | do_not_nx = 1; | |
58 | __supported_pte_mask &= ~_PAGE_NX; | |
59 | } | |
2c8c0e6b | 60 | return 0; |
1da177e4 | 61 | } |
2c8c0e6b | 62 | early_param("noexec", nonx_setup); |
1da177e4 | 63 | |
7682968b | 64 | int force_personality32 = 0; |
1da177e4 LT |
65 | |
66 | /* noexec32=on|off | |
67 | Control non executable heap for 32bit processes. | |
68 | To control the stack too use noexec=off | |
69 | ||
70 | on PROT_READ does not imply PROT_EXEC for 32bit processes | |
71 | off PROT_READ implies PROT_EXEC (default) | |
72 | */ | |
73 | static int __init nonx32_setup(char *str) | |
74 | { | |
75 | if (!strcmp(str, "on")) | |
76 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
77 | else if (!strcmp(str, "off")) | |
78 | force_personality32 |= READ_IMPLIES_EXEC; | |
9b41046c | 79 | return 1; |
1da177e4 LT |
80 | } |
81 | __setup("noexec32=", nonx32_setup); | |
82 | ||
83 | /* | |
84 | * Great future plan: | |
85 | * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data. | |
86 | * Always point %gs to its beginning | |
87 | */ | |
88 | void __init setup_per_cpu_areas(void) | |
89 | { | |
90 | int i; | |
91 | unsigned long size; | |
92 | ||
421c7ce6 AK |
93 | #ifdef CONFIG_HOTPLUG_CPU |
94 | prefill_possible_map(); | |
95 | #endif | |
96 | ||
1da177e4 | 97 | /* Copy section for each CPU (we discard the original) */ |
ba4d40bb | 98 | size = PERCPU_ENOUGH_ROOM; |
1da177e4 | 99 | |
ba4d40bb | 100 | printk(KERN_INFO "PERCPU: Allocating %lu bytes of per cpu data\n", size); |
e99b861a | 101 | for_each_cpu_mask (i, cpu_possible_map) { |
a940199f | 102 | char *ptr; |
1da177e4 LT |
103 | |
104 | if (!NODE_DATA(cpu_to_node(i))) { | |
105 | printk("cpu with no node %d, num_online_nodes %d\n", | |
106 | i, num_online_nodes()); | |
107 | ptr = alloc_bootmem(size); | |
108 | } else { | |
109 | ptr = alloc_bootmem_node(NODE_DATA(cpu_to_node(i)), size); | |
110 | } | |
111 | if (!ptr) | |
112 | panic("Cannot allocate cpu data for CPU %d\n", i); | |
df79efde | 113 | cpu_pda(i)->data_offset = ptr - __per_cpu_start; |
1da177e4 LT |
114 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); |
115 | } | |
116 | } | |
117 | ||
118 | void pda_init(int cpu) | |
119 | { | |
df79efde | 120 | struct x8664_pda *pda = cpu_pda(cpu); |
1da177e4 LT |
121 | |
122 | /* Setup up data that may be needed in __get_free_pages early */ | |
123 | asm volatile("movl %0,%%fs ; movl %0,%%gs" :: "r" (0)); | |
53ee11ae AK |
124 | /* Memory clobbers used to order PDA accessed */ |
125 | mb(); | |
df79efde | 126 | wrmsrl(MSR_GS_BASE, pda); |
53ee11ae | 127 | mb(); |
1da177e4 | 128 | |
1da177e4 LT |
129 | pda->cpunumber = cpu; |
130 | pda->irqcount = -1; | |
131 | pda->kernelstack = | |
132 | (unsigned long)stack_thread_info() - PDA_STACKOFFSET + THREAD_SIZE; | |
133 | pda->active_mm = &init_mm; | |
134 | pda->mmu_state = 0; | |
135 | ||
136 | if (cpu == 0) { | |
137 | /* others are initialized in smpboot.c */ | |
138 | pda->pcurrent = &init_task; | |
139 | pda->irqstackptr = boot_cpu_stack; | |
140 | } else { | |
141 | pda->irqstackptr = (char *) | |
142 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
143 | if (!pda->irqstackptr) | |
144 | panic("cannot allocate irqstack for cpu %d", cpu); | |
145 | } | |
146 | ||
1da177e4 LT |
147 | |
148 | pda->irqstackptr += IRQSTACKSIZE-64; | |
149 | } | |
150 | ||
ab26a20b | 151 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ] |
1da177e4 LT |
152 | __attribute__((section(".bss.page_aligned"))); |
153 | ||
154 | /* May not be marked __init: used by software suspend */ | |
155 | void syscall_init(void) | |
156 | { | |
157 | /* | |
158 | * LSTAR and STAR live in a bit strange symbiosis. | |
159 | * They both write to the same internal register. STAR allows to set CS/DS | |
160 | * but only a 32bit target. LSTAR sets the 64bit rip. | |
161 | */ | |
162 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
163 | wrmsrl(MSR_LSTAR, system_call); | |
164 | ||
165 | #ifdef CONFIG_IA32_EMULATION | |
166 | syscall32_cpu_init (); | |
167 | #endif | |
168 | ||
169 | /* Flags to clear on syscall */ | |
170 | wrmsrl(MSR_SYSCALL_MASK, EF_TF|EF_DF|EF_IE|0x3000); | |
171 | } | |
172 | ||
e6982c67 | 173 | void __cpuinit check_efer(void) |
1da177e4 LT |
174 | { |
175 | unsigned long efer; | |
176 | ||
177 | rdmsrl(MSR_EFER, efer); | |
178 | if (!(efer & EFER_NX) || do_not_nx) { | |
179 | __supported_pte_mask &= ~_PAGE_NX; | |
180 | } | |
181 | } | |
182 | ||
183 | /* | |
184 | * cpu_init() initializes state that is per-CPU. Some data is already | |
185 | * initialized (naturally) in the bootstrap process, such as the GDT | |
186 | * and IDT. We reload them nevertheless, this function acts as a | |
187 | * 'CPU state barrier', nothing should get across. | |
188 | * A lot of state is already set up in PDA init. | |
189 | */ | |
e6982c67 | 190 | void __cpuinit cpu_init (void) |
1da177e4 | 191 | { |
1da177e4 | 192 | int cpu = stack_smp_processor_id(); |
1da177e4 | 193 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
01ebb77b | 194 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); |
1da177e4 LT |
195 | unsigned long v; |
196 | char *estacks = NULL; | |
197 | struct task_struct *me; | |
198 | int i; | |
199 | ||
200 | /* CPU 0 is initialised in head64.c */ | |
201 | if (cpu != 0) { | |
202 | pda_init(cpu); | |
f6c2e333 | 203 | zap_low_mappings(cpu); |
1da177e4 LT |
204 | } else |
205 | estacks = boot_exception_stacks; | |
206 | ||
207 | me = current; | |
208 | ||
209 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
210 | panic("CPU#%d already initialized!\n", cpu); | |
211 | ||
212 | printk("Initializing CPU#%d\n", cpu); | |
213 | ||
a940199f | 214 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1da177e4 LT |
215 | |
216 | /* | |
217 | * Initialize the per-CPU GDT with the boot GDT, | |
218 | * and set up the GDT descriptor: | |
219 | */ | |
c11efdf9 RT |
220 | if (cpu) |
221 | memcpy(cpu_gdt(cpu), cpu_gdt_table, GDT_SIZE); | |
1da177e4 LT |
222 | |
223 | cpu_gdt_descr[cpu].size = GDT_SIZE; | |
1da177e4 LT |
224 | asm volatile("lgdt %0" :: "m" (cpu_gdt_descr[cpu])); |
225 | asm volatile("lidt %0" :: "m" (idt_descr)); | |
226 | ||
c11efdf9 | 227 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); |
1da177e4 LT |
228 | syscall_init(); |
229 | ||
230 | wrmsrl(MSR_FS_BASE, 0); | |
231 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
232 | barrier(); | |
233 | ||
234 | check_efer(); | |
235 | ||
236 | /* | |
237 | * set up and load the per-CPU TSS | |
238 | */ | |
239 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
f5741644 KO |
240 | static const unsigned int order[N_EXCEPTION_STACKS] = { |
241 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
242 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
243 | }; | |
1da177e4 | 244 | if (cpu) { |
b556b35e | 245 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); |
1da177e4 LT |
246 | if (!estacks) |
247 | panic("Cannot allocate exception stack %ld %d\n", | |
248 | v, cpu); | |
249 | } | |
f5741644 | 250 | estacks += PAGE_SIZE << order[v]; |
01ebb77b | 251 | orig_ist->ist[v] = t->ist[v] = (unsigned long)estacks; |
1da177e4 LT |
252 | } |
253 | ||
254 | t->io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
255 | /* | |
256 | * <= is required because the CPU will access up to | |
257 | * 8 bits beyond the end of the IO permission bitmap. | |
258 | */ | |
259 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
260 | t->io_bitmap[i] = ~0UL; | |
261 | ||
262 | atomic_inc(&init_mm.mm_count); | |
263 | me->active_mm = &init_mm; | |
264 | if (me->mm) | |
265 | BUG(); | |
266 | enter_lazy_tlb(&init_mm, me); | |
267 | ||
268 | set_tss_desc(cpu, t); | |
269 | load_TR_desc(); | |
270 | load_LDT(&init_mm.context); | |
271 | ||
272 | /* | |
273 | * Clear all 6 debug registers: | |
274 | */ | |
275 | ||
2b514e74 JB |
276 | set_debugreg(0UL, 0); |
277 | set_debugreg(0UL, 1); | |
278 | set_debugreg(0UL, 2); | |
279 | set_debugreg(0UL, 3); | |
280 | set_debugreg(0UL, 6); | |
281 | set_debugreg(0UL, 7); | |
1da177e4 LT |
282 | |
283 | fpu_init(); | |
284 | } |