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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
aa0a9f37 | 4 | * Copyright (C) IBM Corporation, 2006 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/calgary.h> | |
40 | #include <asm/tce.h> | |
41 | #include <asm/pci-direct.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/dma.h> | |
44 | ||
45 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 | |
46 | #define PCI_VENDOR_DEVICE_ID_CALGARY \ | |
47 | (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16) | |
48 | ||
49 | /* we need these for register space address calculation */ | |
50 | #define START_ADDRESS 0xfe000000 | |
51 | #define CHASSIS_BASE 0 | |
52 | #define ONE_BASED_CHASSIS_NUM 1 | |
53 | ||
54 | /* register offsets inside the host bridge space */ | |
cb01fc72 MBY |
55 | #define CALGARY_CONFIG_REG 0x0108 |
56 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
57 | #define PHB_PLSSR_OFFSET 0x0120 |
58 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
59 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
60 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
61 | #define PHB_MEM_1_LOW 0x0190 | |
62 | #define PHB_MEM_1_HIGH 0x01A0 | |
63 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
64 | #define PHB_MEM_1_SIZE 0x01C0 | |
65 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
66 | #define PHB_AER_OFFSET 0x0200 | |
67 | #define PHB_CONFIG_0_HIGH 0x0220 | |
68 | #define PHB_CONFIG_0_LOW 0x0230 | |
69 | #define PHB_CONFIG_0_END 0x0240 | |
70 | #define PHB_MEM_2_LOW 0x02B0 | |
71 | #define PHB_MEM_2_HIGH 0x02C0 | |
72 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
73 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
74 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
75 | ||
76 | /* PHB_CONFIG_RW */ | |
77 | #define PHB_TCE_ENABLE 0x20000000 | |
78 | #define PHB_SLOT_DISABLE 0x1C000000 | |
79 | #define PHB_DAC_DISABLE 0x01000000 | |
80 | #define PHB_MEM2_ENABLE 0x00400000 | |
81 | #define PHB_MCSR_ENABLE 0x00100000 | |
82 | /* TAR (Table Address Register) */ | |
83 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
84 | #define TAR_VALID 0x0000000000000008UL | |
85 | /* CSR (Channel/DMA Status Register) */ | |
86 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 MBY |
87 | /* CCR (Calgary Configuration Register) */ |
88 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL | |
e465058d JM |
89 | |
90 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 91 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
92 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
93 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
94 | #define PHBS_PER_CALGARY 4 |
95 | ||
96 | /* register offsets in Calgary's internal register space */ | |
97 | static const unsigned long tar_offsets[] = { | |
98 | 0x0580 /* TAR0 */, | |
99 | 0x0588 /* TAR1 */, | |
100 | 0x0590 /* TAR2 */, | |
101 | 0x0598 /* TAR3 */ | |
102 | }; | |
103 | ||
104 | static const unsigned long split_queue_offsets[] = { | |
105 | 0x4870 /* SPLIT QUEUE 0 */, | |
106 | 0x5870 /* SPLIT QUEUE 1 */, | |
107 | 0x6870 /* SPLIT QUEUE 2 */, | |
108 | 0x7870 /* SPLIT QUEUE 3 */ | |
109 | }; | |
110 | ||
111 | static const unsigned long phb_offsets[] = { | |
112 | 0x8000 /* PHB0 */, | |
113 | 0x9000 /* PHB1 */, | |
114 | 0xA000 /* PHB2 */, | |
115 | 0xB000 /* PHB3 */ | |
116 | }; | |
117 | ||
e465058d JM |
118 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
119 | static int translate_empty_slots __read_mostly = 0; | |
120 | static int calgary_detected __read_mostly = 0; | |
121 | ||
f38db651 MBY |
122 | struct calgary_bus_info { |
123 | void *tce_space; | |
0577f148 | 124 | unsigned char translation_disabled; |
f38db651 MBY |
125 | signed char phbid; |
126 | }; | |
127 | ||
128 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; | |
e465058d JM |
129 | |
130 | static void tce_cache_blast(struct iommu_table *tbl); | |
131 | ||
132 | /* enable this to stress test the chip's TCE cache */ | |
133 | #ifdef CONFIG_IOMMU_DEBUG | |
de684652 MBY |
134 | int debugging __read_mostly = 1; |
135 | ||
796e4390 MBY |
136 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
137 | int expected, unsigned long start, unsigned long end) | |
138 | { | |
139 | unsigned long idx = start; | |
140 | ||
141 | BUG_ON(start >= end); | |
142 | ||
143 | while (idx < end) { | |
144 | if (!!test_bit(idx, bitmap) != expected) | |
145 | return idx; | |
146 | ++idx; | |
147 | } | |
148 | ||
149 | /* all bits have the expected value */ | |
150 | return ~0UL; | |
151 | } | |
de684652 MBY |
152 | #else /* debugging is disabled */ |
153 | int debugging __read_mostly = 0; | |
154 | ||
796e4390 MBY |
155 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
156 | int expected, unsigned long start, unsigned long end) | |
157 | { | |
158 | return ~0UL; | |
159 | } | |
de684652 | 160 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
161 | |
162 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
163 | { | |
164 | unsigned int npages; | |
165 | ||
166 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
167 | npages >>= PAGE_SHIFT; | |
168 | ||
169 | return npages; | |
170 | } | |
171 | ||
172 | static inline int translate_phb(struct pci_dev* dev) | |
173 | { | |
f38db651 | 174 | int disabled = bus_info[dev->bus->number].translation_disabled; |
e465058d JM |
175 | return !disabled; |
176 | } | |
177 | ||
178 | static void iommu_range_reserve(struct iommu_table *tbl, | |
179 | unsigned long start_addr, unsigned int npages) | |
180 | { | |
181 | unsigned long index; | |
182 | unsigned long end; | |
796e4390 | 183 | unsigned long badbit; |
e465058d JM |
184 | |
185 | index = start_addr >> PAGE_SHIFT; | |
186 | ||
187 | /* bail out if we're asked to reserve a region we don't cover */ | |
188 | if (index >= tbl->it_size) | |
189 | return; | |
190 | ||
191 | end = index + npages; | |
192 | if (end > tbl->it_size) /* don't go off the table */ | |
193 | end = tbl->it_size; | |
194 | ||
796e4390 MBY |
195 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
196 | if (badbit != ~0UL) { | |
197 | if (printk_ratelimit()) | |
e465058d JM |
198 | printk(KERN_ERR "Calgary: entry already allocated at " |
199 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 200 | badbit, tbl, start_addr, npages); |
e465058d | 201 | } |
796e4390 MBY |
202 | |
203 | set_bit_string(tbl->it_map, index, npages); | |
e465058d JM |
204 | } |
205 | ||
206 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
207 | unsigned int npages) | |
208 | { | |
209 | unsigned long offset; | |
210 | ||
211 | BUG_ON(npages == 0); | |
212 | ||
213 | offset = find_next_zero_string(tbl->it_map, tbl->it_hint, | |
214 | tbl->it_size, npages); | |
215 | if (offset == ~0UL) { | |
216 | tce_cache_blast(tbl); | |
217 | offset = find_next_zero_string(tbl->it_map, 0, | |
218 | tbl->it_size, npages); | |
219 | if (offset == ~0UL) { | |
220 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
221 | if (panic_on_overflow) | |
222 | panic("Calgary: fix the allocator.\n"); | |
223 | else | |
224 | return bad_dma_address; | |
225 | } | |
226 | } | |
227 | ||
228 | set_bit_string(tbl->it_map, offset, npages); | |
229 | tbl->it_hint = offset + npages; | |
230 | BUG_ON(tbl->it_hint > tbl->it_size); | |
231 | ||
232 | return offset; | |
233 | } | |
234 | ||
235 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr, | |
236 | unsigned int npages, int direction) | |
237 | { | |
238 | unsigned long entry, flags; | |
239 | dma_addr_t ret = bad_dma_address; | |
240 | ||
241 | spin_lock_irqsave(&tbl->it_lock, flags); | |
242 | ||
243 | entry = iommu_range_alloc(tbl, npages); | |
244 | ||
245 | if (unlikely(entry == bad_dma_address)) | |
246 | goto error; | |
247 | ||
248 | /* set the return dma address */ | |
249 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
250 | ||
251 | /* put the TCEs in the HW table */ | |
252 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
253 | direction); | |
254 | ||
255 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
256 | ||
257 | return ret; | |
258 | ||
259 | error: | |
260 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
261 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | |
262 | "iommu %p\n", npages, tbl); | |
263 | return bad_dma_address; | |
264 | } | |
265 | ||
266 | static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
267 | unsigned int npages) | |
268 | { | |
269 | unsigned long entry; | |
796e4390 | 270 | unsigned long badbit; |
e465058d JM |
271 | |
272 | entry = dma_addr >> PAGE_SHIFT; | |
273 | ||
274 | BUG_ON(entry + npages > tbl->it_size); | |
275 | ||
276 | tce_free(tbl, entry, npages); | |
277 | ||
796e4390 MBY |
278 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
279 | if (badbit != ~0UL) { | |
280 | if (printk_ratelimit()) | |
e465058d JM |
281 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
282 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 283 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
284 | } |
285 | ||
286 | __clear_bit_string(tbl->it_map, entry, npages); | |
e465058d JM |
287 | } |
288 | ||
289 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
290 | unsigned int npages) | |
291 | { | |
292 | unsigned long flags; | |
293 | ||
294 | spin_lock_irqsave(&tbl->it_lock, flags); | |
295 | ||
296 | __iommu_free(tbl, dma_addr, npages); | |
297 | ||
298 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
299 | } | |
300 | ||
301 | static void __calgary_unmap_sg(struct iommu_table *tbl, | |
302 | struct scatterlist *sglist, int nelems, int direction) | |
303 | { | |
304 | while (nelems--) { | |
305 | unsigned int npages; | |
306 | dma_addr_t dma = sglist->dma_address; | |
307 | unsigned int dmalen = sglist->dma_length; | |
308 | ||
309 | if (dmalen == 0) | |
310 | break; | |
311 | ||
312 | npages = num_dma_pages(dma, dmalen); | |
313 | __iommu_free(tbl, dma, npages); | |
314 | sglist++; | |
315 | } | |
316 | } | |
317 | ||
318 | void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, | |
319 | int nelems, int direction) | |
320 | { | |
321 | unsigned long flags; | |
322 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
323 | ||
324 | if (!translate_phb(to_pci_dev(dev))) | |
325 | return; | |
326 | ||
327 | spin_lock_irqsave(&tbl->it_lock, flags); | |
328 | ||
329 | __calgary_unmap_sg(tbl, sglist, nelems, direction); | |
330 | ||
331 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
332 | } | |
333 | ||
334 | static int calgary_nontranslate_map_sg(struct device* dev, | |
335 | struct scatterlist *sg, int nelems, int direction) | |
336 | { | |
337 | int i; | |
338 | ||
339 | for (i = 0; i < nelems; i++ ) { | |
340 | struct scatterlist *s = &sg[i]; | |
341 | BUG_ON(!s->page); | |
342 | s->dma_address = virt_to_bus(page_address(s->page) +s->offset); | |
343 | s->dma_length = s->length; | |
344 | } | |
345 | return nelems; | |
346 | } | |
347 | ||
348 | int calgary_map_sg(struct device *dev, struct scatterlist *sg, | |
349 | int nelems, int direction) | |
350 | { | |
351 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
352 | unsigned long flags; | |
353 | unsigned long vaddr; | |
354 | unsigned int npages; | |
355 | unsigned long entry; | |
356 | int i; | |
357 | ||
358 | if (!translate_phb(to_pci_dev(dev))) | |
359 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); | |
360 | ||
361 | spin_lock_irqsave(&tbl->it_lock, flags); | |
362 | ||
363 | for (i = 0; i < nelems; i++ ) { | |
364 | struct scatterlist *s = &sg[i]; | |
365 | BUG_ON(!s->page); | |
366 | ||
367 | vaddr = (unsigned long)page_address(s->page) + s->offset; | |
368 | npages = num_dma_pages(vaddr, s->length); | |
369 | ||
370 | entry = iommu_range_alloc(tbl, npages); | |
371 | if (entry == bad_dma_address) { | |
372 | /* makes sure unmap knows to stop */ | |
373 | s->dma_length = 0; | |
374 | goto error; | |
375 | } | |
376 | ||
377 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
378 | ||
379 | /* insert into HW table */ | |
380 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
381 | direction); | |
382 | ||
383 | s->dma_length = s->length; | |
384 | } | |
385 | ||
386 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
387 | ||
388 | return nelems; | |
389 | error: | |
390 | __calgary_unmap_sg(tbl, sg, nelems, direction); | |
391 | for (i = 0; i < nelems; i++) { | |
392 | sg[i].dma_address = bad_dma_address; | |
393 | sg[i].dma_length = 0; | |
394 | } | |
395 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
396 | return 0; | |
397 | } | |
398 | ||
399 | dma_addr_t calgary_map_single(struct device *dev, void *vaddr, | |
400 | size_t size, int direction) | |
401 | { | |
402 | dma_addr_t dma_handle = bad_dma_address; | |
403 | unsigned long uaddr; | |
404 | unsigned int npages; | |
405 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
406 | ||
407 | uaddr = (unsigned long)vaddr; | |
408 | npages = num_dma_pages(uaddr, size); | |
409 | ||
410 | if (translate_phb(to_pci_dev(dev))) | |
411 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction); | |
412 | else | |
413 | dma_handle = virt_to_bus(vaddr); | |
414 | ||
415 | return dma_handle; | |
416 | } | |
417 | ||
418 | void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, | |
419 | size_t size, int direction) | |
420 | { | |
421 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
422 | unsigned int npages; | |
423 | ||
424 | if (!translate_phb(to_pci_dev(dev))) | |
425 | return; | |
426 | ||
427 | npages = num_dma_pages(dma_handle, size); | |
428 | iommu_free(tbl, dma_handle, npages); | |
429 | } | |
430 | ||
431 | void* calgary_alloc_coherent(struct device *dev, size_t size, | |
432 | dma_addr_t *dma_handle, gfp_t flag) | |
433 | { | |
434 | void *ret = NULL; | |
435 | dma_addr_t mapping; | |
436 | unsigned int npages, order; | |
437 | struct iommu_table *tbl; | |
438 | ||
439 | tbl = to_pci_dev(dev)->bus->self->sysdata; | |
440 | ||
441 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
442 | npages = size >> PAGE_SHIFT; | |
443 | order = get_order(size); | |
444 | ||
445 | /* alloc enough pages (and possibly more) */ | |
446 | ret = (void *)__get_free_pages(flag, order); | |
447 | if (!ret) | |
448 | goto error; | |
449 | memset(ret, 0, size); | |
450 | ||
451 | if (translate_phb(to_pci_dev(dev))) { | |
452 | /* set up tces to cover the allocated range */ | |
453 | mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL); | |
454 | if (mapping == bad_dma_address) | |
455 | goto free; | |
456 | ||
457 | *dma_handle = mapping; | |
458 | } else /* non translated slot */ | |
459 | *dma_handle = virt_to_bus(ret); | |
460 | ||
461 | return ret; | |
462 | ||
463 | free: | |
464 | free_pages((unsigned long)ret, get_order(size)); | |
465 | ret = NULL; | |
466 | error: | |
467 | return ret; | |
468 | } | |
469 | ||
470 | static struct dma_mapping_ops calgary_dma_ops = { | |
471 | .alloc_coherent = calgary_alloc_coherent, | |
472 | .map_single = calgary_map_single, | |
473 | .unmap_single = calgary_unmap_single, | |
474 | .map_sg = calgary_map_sg, | |
475 | .unmap_sg = calgary_unmap_sg, | |
476 | }; | |
477 | ||
478 | static inline int busno_to_phbid(unsigned char num) | |
479 | { | |
f38db651 | 480 | return bus_info[num].phbid; |
e465058d JM |
481 | } |
482 | ||
483 | static inline unsigned long split_queue_offset(unsigned char num) | |
484 | { | |
485 | size_t idx = busno_to_phbid(num); | |
486 | ||
487 | return split_queue_offsets[idx]; | |
488 | } | |
489 | ||
490 | static inline unsigned long tar_offset(unsigned char num) | |
491 | { | |
492 | size_t idx = busno_to_phbid(num); | |
493 | ||
494 | return tar_offsets[idx]; | |
495 | } | |
496 | ||
497 | static inline unsigned long phb_offset(unsigned char num) | |
498 | { | |
499 | size_t idx = busno_to_phbid(num); | |
500 | ||
501 | return phb_offsets[idx]; | |
502 | } | |
503 | ||
504 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
505 | { | |
506 | unsigned long target = ((unsigned long)bar) | offset; | |
507 | return (void __iomem*)target; | |
508 | } | |
509 | ||
510 | static void tce_cache_blast(struct iommu_table *tbl) | |
511 | { | |
512 | u64 val; | |
513 | u32 aer; | |
514 | int i = 0; | |
515 | void __iomem *bbar = tbl->bbar; | |
516 | void __iomem *target; | |
517 | ||
518 | /* disable arbitration on the bus */ | |
519 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
520 | aer = readl(target); | |
521 | writel(0, target); | |
522 | ||
523 | /* read plssr to ensure it got there */ | |
524 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
525 | val = readl(target); | |
526 | ||
527 | /* poll split queues until all DMA activity is done */ | |
528 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
529 | do { | |
530 | val = readq(target); | |
531 | i++; | |
532 | } while ((val & 0xff) != 0xff && i < 100); | |
533 | if (i == 100) | |
534 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
535 | "continuing anyway\n"); | |
536 | ||
537 | /* invalidate TCE cache */ | |
538 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
539 | writeq(tbl->tar_val, target); | |
540 | ||
541 | /* enable arbitration */ | |
542 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
543 | writel(aer, target); | |
544 | (void)readl(target); /* flush */ | |
545 | } | |
546 | ||
547 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, | |
548 | u64 limit) | |
549 | { | |
550 | unsigned int numpages; | |
551 | ||
552 | limit = limit | 0xfffff; | |
553 | limit++; | |
554 | ||
555 | numpages = ((limit - start) >> PAGE_SHIFT); | |
556 | iommu_range_reserve(dev->sysdata, start, numpages); | |
557 | } | |
558 | ||
559 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
560 | { | |
561 | void __iomem *target; | |
562 | u64 low, high, sizelow; | |
563 | u64 start, limit; | |
564 | struct iommu_table *tbl = dev->sysdata; | |
565 | unsigned char busnum = dev->bus->number; | |
566 | void __iomem *bbar = tbl->bbar; | |
567 | ||
568 | /* peripheral MEM_1 region */ | |
569 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
570 | low = be32_to_cpu(readl(target)); | |
571 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
572 | high = be32_to_cpu(readl(target)); | |
573 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
574 | sizelow = be32_to_cpu(readl(target)); | |
575 | ||
576 | start = (high << 32) | low; | |
577 | limit = sizelow; | |
578 | ||
579 | calgary_reserve_mem_region(dev, start, limit); | |
580 | } | |
581 | ||
582 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
583 | { | |
584 | void __iomem *target; | |
585 | u32 val32; | |
586 | u64 low, high, sizelow, sizehigh; | |
587 | u64 start, limit; | |
588 | struct iommu_table *tbl = dev->sysdata; | |
589 | unsigned char busnum = dev->bus->number; | |
590 | void __iomem *bbar = tbl->bbar; | |
591 | ||
592 | /* is it enabled? */ | |
593 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
594 | val32 = be32_to_cpu(readl(target)); | |
595 | if (!(val32 & PHB_MEM2_ENABLE)) | |
596 | return; | |
597 | ||
598 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
599 | low = be32_to_cpu(readl(target)); | |
600 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
601 | high = be32_to_cpu(readl(target)); | |
602 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
603 | sizelow = be32_to_cpu(readl(target)); | |
604 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
605 | sizehigh = be32_to_cpu(readl(target)); | |
606 | ||
607 | start = (high << 32) | low; | |
608 | limit = (sizehigh << 32) | sizelow; | |
609 | ||
610 | calgary_reserve_mem_region(dev, start, limit); | |
611 | } | |
612 | ||
613 | /* | |
614 | * some regions of the IO address space do not get translated, so we | |
615 | * must not give devices IO addresses in those regions. The regions | |
616 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
617 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
618 | * later. | |
619 | */ | |
620 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
621 | { | |
622 | unsigned int npages; | |
623 | void __iomem *bbar; | |
624 | unsigned char busnum; | |
625 | u64 start; | |
626 | struct iommu_table *tbl = dev->sysdata; | |
627 | ||
628 | bbar = tbl->bbar; | |
629 | busnum = dev->bus->number; | |
630 | ||
631 | /* reserve bad_dma_address in case it's a legal address */ | |
632 | iommu_range_reserve(tbl, bad_dma_address, 1); | |
633 | ||
634 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
635 | start = (640 * 1024); | |
636 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
637 | iommu_range_reserve(tbl, start, npages); | |
638 | ||
639 | /* reserve the two PCI peripheral memory regions in IO space */ | |
640 | calgary_reserve_peripheral_mem_1(dev); | |
641 | calgary_reserve_peripheral_mem_2(dev); | |
642 | } | |
643 | ||
644 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
645 | { | |
646 | u64 val64; | |
647 | u64 table_phys; | |
648 | void __iomem *target; | |
649 | int ret; | |
650 | struct iommu_table *tbl; | |
651 | ||
652 | /* build TCE tables for each PHB */ | |
653 | ret = build_tce_table(dev, bbar); | |
654 | if (ret) | |
655 | return ret; | |
656 | ||
f38db651 MBY |
657 | tbl = dev->sysdata; |
658 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; | |
659 | tce_free(tbl, 0, tbl->it_size); | |
660 | ||
e465058d JM |
661 | calgary_reserve_regions(dev); |
662 | ||
663 | /* set TARs for each PHB */ | |
664 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
665 | val64 = be64_to_cpu(readq(target)); | |
666 | ||
667 | /* zero out all TAR bits under sw control */ | |
668 | val64 &= ~TAR_SW_BITS; | |
669 | ||
670 | tbl = dev->sysdata; | |
671 | table_phys = (u64)__pa(tbl->it_base); | |
672 | val64 |= table_phys; | |
673 | ||
674 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
675 | val64 |= (u64) specified_table_size; | |
676 | ||
677 | tbl->tar_val = cpu_to_be64(val64); | |
678 | writeq(tbl->tar_val, target); | |
679 | readq(target); /* flush */ | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
b8f4fe66 | 684 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
685 | { |
686 | u64 val64; | |
687 | struct iommu_table *tbl = dev->sysdata; | |
688 | void __iomem *target; | |
b8f4fe66 | 689 | unsigned int bitmapsz; |
e465058d JM |
690 | |
691 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
692 | val64 = be64_to_cpu(readq(target)); | |
693 | val64 &= ~TAR_SW_BITS; | |
694 | writeq(cpu_to_be64(val64), target); | |
695 | readq(target); /* flush */ | |
696 | ||
b8f4fe66 MBY |
697 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
698 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
699 | tbl->it_map = NULL; | |
700 | ||
e465058d JM |
701 | kfree(tbl); |
702 | dev->sysdata = NULL; | |
b8f4fe66 MBY |
703 | |
704 | /* Can't free bootmem allocated memory after system is up :-( */ | |
705 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
706 | } |
707 | ||
708 | static void calgary_watchdog(unsigned long data) | |
709 | { | |
710 | struct pci_dev *dev = (struct pci_dev *)data; | |
711 | struct iommu_table *tbl = dev->sysdata; | |
712 | void __iomem *bbar = tbl->bbar; | |
713 | u32 val32; | |
714 | void __iomem *target; | |
715 | ||
716 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
717 | val32 = be32_to_cpu(readl(target)); | |
718 | ||
719 | /* If no error, the agent ID in the CSR is not valid */ | |
720 | if (val32 & CSR_AGENT_MASK) { | |
70d666d6 | 721 | printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, " |
e465058d JM |
722 | "CSR = %#x\n", dev->bus->number, val32); |
723 | writel(0, target); | |
724 | ||
725 | /* Disable bus that caused the error */ | |
726 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
727 | PHB_CONFIG_RW_OFFSET); | |
728 | val32 = be32_to_cpu(readl(target)); | |
729 | val32 |= PHB_SLOT_DISABLE; | |
730 | writel(cpu_to_be32(val32), target); | |
731 | readl(target); /* flush */ | |
732 | } else { | |
733 | /* Reset the timer */ | |
734 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
735 | } | |
736 | } | |
737 | ||
cb01fc72 MBY |
738 | static void __init calgary_increase_split_completion_timeout(void __iomem *bbar, |
739 | unsigned char busnum) | |
740 | { | |
741 | u64 val64; | |
742 | void __iomem *target; | |
58db8548 | 743 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
744 | u64 mask; |
745 | ||
746 | switch (busno_to_phbid(busnum)) { | |
747 | case 0: phb_shift = (63 - 19); | |
748 | break; | |
749 | case 1: phb_shift = (63 - 23); | |
750 | break; | |
751 | case 2: phb_shift = (63 - 27); | |
752 | break; | |
753 | case 3: phb_shift = (63 - 35); | |
754 | break; | |
755 | default: | |
756 | BUG_ON(busno_to_phbid(busnum)); | |
757 | } | |
758 | ||
759 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
760 | val64 = be64_to_cpu(readq(target)); | |
761 | ||
762 | /* zero out this PHB's timer bits */ | |
763 | mask = ~(0xFUL << phb_shift); | |
764 | val64 &= mask; | |
765 | val64 |= (CCR_2SEC_TIMEOUT << phb_shift); | |
766 | writeq(cpu_to_be64(val64), target); | |
767 | readq(target); /* flush */ | |
768 | } | |
769 | ||
e465058d JM |
770 | static void __init calgary_enable_translation(struct pci_dev *dev) |
771 | { | |
772 | u32 val32; | |
773 | unsigned char busnum; | |
774 | void __iomem *target; | |
775 | void __iomem *bbar; | |
776 | struct iommu_table *tbl; | |
777 | ||
778 | busnum = dev->bus->number; | |
779 | tbl = dev->sysdata; | |
780 | bbar = tbl->bbar; | |
781 | ||
782 | /* enable TCE in PHB Config Register */ | |
783 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
784 | val32 = be32_to_cpu(readl(target)); | |
785 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
786 | ||
70d666d6 | 787 | printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum); |
e465058d JM |
788 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
789 | "bus.\n"); | |
790 | ||
791 | writel(cpu_to_be32(val32), target); | |
792 | readl(target); /* flush */ | |
793 | ||
cb01fc72 MBY |
794 | /* |
795 | * Give split completion a longer timeout on bus 1 for aic94xx | |
796 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
797 | */ | |
798 | if (busnum == 1) | |
799 | calgary_increase_split_completion_timeout(bbar, busnum); | |
800 | ||
e465058d JM |
801 | init_timer(&tbl->watchdog_timer); |
802 | tbl->watchdog_timer.function = &calgary_watchdog; | |
803 | tbl->watchdog_timer.data = (unsigned long)dev; | |
804 | mod_timer(&tbl->watchdog_timer, jiffies); | |
805 | } | |
806 | ||
807 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
808 | { | |
809 | u32 val32; | |
810 | unsigned char busnum; | |
811 | void __iomem *target; | |
812 | void __iomem *bbar; | |
813 | struct iommu_table *tbl; | |
814 | ||
815 | busnum = dev->bus->number; | |
816 | tbl = dev->sysdata; | |
817 | bbar = tbl->bbar; | |
818 | ||
819 | /* disable TCE in PHB Config Register */ | |
820 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
821 | val32 = be32_to_cpu(readl(target)); | |
822 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
823 | ||
70d666d6 | 824 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
825 | writel(cpu_to_be32(val32), target); |
826 | readl(target); /* flush */ | |
827 | ||
828 | del_timer_sync(&tbl->watchdog_timer); | |
829 | } | |
830 | ||
831 | static inline unsigned int __init locate_register_space(struct pci_dev *dev) | |
832 | { | |
833 | int rionodeid; | |
834 | u32 address; | |
835 | ||
76fd2317 JM |
836 | /* |
837 | * Each Calgary has four busses. The first four busses (first Calgary) | |
838 | * have RIO node ID 2, then the next four (second Calgary) have RIO | |
839 | * node ID 3, the next four (third Calgary) have node ID 2 again, etc. | |
840 | * We use a gross hack - relying on the dev->bus->number ordering, | |
841 | * modulo 14 - to decide which Calgary a given bus is on. Busses 0, 1, | |
842 | * 2 and 4 are on the first Calgary (id 2), 6, 8, a and c are on the | |
843 | * second (id 3), and then it repeats modulo 14. | |
844 | */ | |
845 | rionodeid = (dev->bus->number % 14 > 4) ? 3 : 2; | |
e465058d JM |
846 | /* |
847 | * register space address calculation as follows: | |
848 | * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase) | |
849 | * ChassisBase is always zero for x366/x260/x460 | |
850 | * RioNodeId is 2 for first Calgary, 3 for second Calgary | |
851 | */ | |
852 | address = START_ADDRESS - | |
76fd2317 | 853 | (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 14)) + |
e465058d JM |
854 | (0x100000) * (rionodeid - CHASSIS_BASE); |
855 | return address; | |
856 | } | |
857 | ||
a4fc520a | 858 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 859 | { |
871b1700 | 860 | pci_dev_get(dev); |
e465058d JM |
861 | dev->sysdata = NULL; |
862 | dev->bus->self = dev; | |
e465058d JM |
863 | } |
864 | ||
865 | static int __init calgary_init_one(struct pci_dev *dev) | |
866 | { | |
867 | u32 address; | |
868 | void __iomem *bbar; | |
869 | int ret; | |
870 | ||
dedc9937 JM |
871 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
872 | ||
e465058d JM |
873 | address = locate_register_space(dev); |
874 | /* map entire 1MB of Calgary config space */ | |
875 | bbar = ioremap_nocache(address, 1024 * 1024); | |
876 | if (!bbar) { | |
877 | ret = -ENODATA; | |
878 | goto done; | |
879 | } | |
880 | ||
881 | ret = calgary_setup_tar(dev, bbar); | |
882 | if (ret) | |
883 | goto iounmap; | |
884 | ||
871b1700 | 885 | pci_dev_get(dev); |
e465058d JM |
886 | dev->bus->self = dev; |
887 | calgary_enable_translation(dev); | |
888 | ||
889 | return 0; | |
890 | ||
891 | iounmap: | |
892 | iounmap(bbar); | |
893 | done: | |
894 | return ret; | |
895 | } | |
896 | ||
897 | static int __init calgary_init(void) | |
898 | { | |
dedc9937 | 899 | int ret = -ENODEV; |
e465058d JM |
900 | struct pci_dev *dev = NULL; |
901 | ||
dedc9937 | 902 | do { |
e465058d JM |
903 | dev = pci_get_device(PCI_VENDOR_ID_IBM, |
904 | PCI_DEVICE_ID_IBM_CALGARY, | |
905 | dev); | |
906 | if (!dev) | |
907 | break; | |
908 | if (!translate_phb(dev)) { | |
909 | calgary_init_one_nontraslated(dev); | |
910 | continue; | |
911 | } | |
871b1700 | 912 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 913 | continue; |
871b1700 | 914 | |
e465058d JM |
915 | ret = calgary_init_one(dev); |
916 | if (ret) | |
917 | goto error; | |
dedc9937 | 918 | } while (1); |
e465058d JM |
919 | |
920 | return ret; | |
921 | ||
922 | error: | |
dedc9937 | 923 | do { |
7cd8b686 | 924 | dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM, |
e465058d JM |
925 | PCI_DEVICE_ID_IBM_CALGARY, |
926 | dev); | |
9f2dc46d MBY |
927 | if (!dev) |
928 | break; | |
e465058d JM |
929 | if (!translate_phb(dev)) { |
930 | pci_dev_put(dev); | |
931 | continue; | |
932 | } | |
f38db651 | 933 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 934 | continue; |
871b1700 | 935 | |
e465058d | 936 | calgary_disable_translation(dev); |
b8f4fe66 | 937 | calgary_free_bus(dev); |
871b1700 | 938 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 939 | } while (1); |
e465058d JM |
940 | |
941 | return ret; | |
942 | } | |
943 | ||
944 | static inline int __init determine_tce_table_size(u64 ram) | |
945 | { | |
946 | int ret; | |
947 | ||
948 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
949 | return specified_table_size; | |
950 | ||
951 | /* | |
952 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
953 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
954 | * larger table size has twice as many entries, so shift the | |
955 | * max ram address by 13 to divide by 8K and then look at the | |
956 | * order of the result to choose between 0-7. | |
957 | */ | |
958 | ret = get_order(ram >> 13); | |
959 | if (ret > TCE_TABLE_SIZE_8M) | |
960 | ret = TCE_TABLE_SIZE_8M; | |
961 | ||
962 | return ret; | |
963 | } | |
964 | ||
965 | void __init detect_calgary(void) | |
966 | { | |
967 | u32 val; | |
d2105b10 | 968 | int bus; |
e465058d | 969 | void *tbl; |
d2105b10 JM |
970 | int calgary_found = 0; |
971 | int phb = -1; | |
e465058d JM |
972 | |
973 | /* | |
974 | * if the user specified iommu=off or iommu=soft or we found | |
975 | * another HW IOMMU already, bail out. | |
976 | */ | |
977 | if (swiotlb || no_iommu || iommu_detected) | |
978 | return; | |
979 | ||
0637a70a AK |
980 | if (!early_pci_allowed()) |
981 | return; | |
982 | ||
e465058d JM |
983 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
984 | ||
d2105b10 JM |
985 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
986 | int dev; | |
f38db651 MBY |
987 | struct calgary_bus_info *info = &bus_info[bus]; |
988 | info->phbid = -1; | |
d2105b10 | 989 | |
e465058d JM |
990 | if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY) |
991 | continue; | |
d2105b10 JM |
992 | |
993 | /* | |
994 | * There are 4 PHBs per Calgary chip. Set phb to which phb (0-3) | |
995 | * it is connected to releative to the clagary chip. | |
996 | */ | |
997 | phb = (phb + 1) % PHBS_PER_CALGARY; | |
998 | ||
f38db651 | 999 | if (info->translation_disabled) |
e465058d | 1000 | continue; |
f38db651 | 1001 | |
e465058d | 1002 | /* |
d2105b10 JM |
1003 | * Scan the slots of the PCI bus to see if there is a device present. |
1004 | * The parent bus will be the zero-ith device, so start at 1. | |
e465058d | 1005 | */ |
d2105b10 JM |
1006 | for (dev = 1; dev < 8; dev++) { |
1007 | val = read_pci_config(bus, dev, 0, 0); | |
1008 | if (val != 0xffffffff || translate_empty_slots) { | |
1009 | tbl = alloc_tce_table(); | |
1010 | if (!tbl) | |
1011 | goto cleanup; | |
f38db651 MBY |
1012 | info->tce_space = tbl; |
1013 | info->phbid = phb; | |
d2105b10 JM |
1014 | calgary_found = 1; |
1015 | break; | |
1016 | } | |
1017 | } | |
e465058d JM |
1018 | } |
1019 | ||
d2105b10 | 1020 | if (calgary_found) { |
e465058d JM |
1021 | iommu_detected = 1; |
1022 | calgary_detected = 1; | |
de684652 MBY |
1023 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1024 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1025 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1026 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1027 | } |
1028 | return; | |
1029 | ||
1030 | cleanup: | |
f38db651 MBY |
1031 | for (--bus; bus >= 0; --bus) { |
1032 | struct calgary_bus_info *info = &bus_info[bus]; | |
1033 | ||
1034 | if (info->tce_space) | |
1035 | free_tce_table(info->tce_space); | |
1036 | } | |
e465058d JM |
1037 | } |
1038 | ||
1039 | int __init calgary_iommu_init(void) | |
1040 | { | |
1041 | int ret; | |
1042 | ||
1043 | if (no_iommu || swiotlb) | |
1044 | return -ENODEV; | |
1045 | ||
1046 | if (!calgary_detected) | |
1047 | return -ENODEV; | |
1048 | ||
1049 | /* ok, we're trying to use Calgary - let's roll */ | |
1050 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1051 | ||
1052 | ret = calgary_init(); | |
1053 | if (ret) { | |
1054 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1055 | "falling back to no_iommu\n", ret); | |
1056 | if (end_pfn > MAX_DMA32_PFN) | |
1057 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1058 | "32bit PCI may malfunction.\n"); | |
1059 | return ret; | |
1060 | } | |
1061 | ||
1062 | force_iommu = 1; | |
1063 | dma_ops = &calgary_dma_ops; | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static int __init calgary_parse_options(char *p) | |
1069 | { | |
1070 | unsigned int bridge; | |
1071 | size_t len; | |
1072 | char* endp; | |
1073 | ||
1074 | while (*p) { | |
1075 | if (!strncmp(p, "64k", 3)) | |
1076 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1077 | else if (!strncmp(p, "128k", 4)) | |
1078 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1079 | else if (!strncmp(p, "256k", 4)) | |
1080 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1081 | else if (!strncmp(p, "512k", 4)) | |
1082 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1083 | else if (!strncmp(p, "1M", 2)) | |
1084 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1085 | else if (!strncmp(p, "2M", 2)) | |
1086 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1087 | else if (!strncmp(p, "4M", 2)) | |
1088 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1089 | else if (!strncmp(p, "8M", 2)) | |
1090 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1091 | ||
1092 | len = strlen("translate_empty_slots"); | |
1093 | if (!strncmp(p, "translate_empty_slots", len)) | |
1094 | translate_empty_slots = 1; | |
1095 | ||
1096 | len = strlen("disable"); | |
1097 | if (!strncmp(p, "disable", len)) { | |
1098 | p += len; | |
1099 | if (*p == '=') | |
1100 | ++p; | |
1101 | if (*p == '\0') | |
1102 | break; | |
1103 | bridge = simple_strtol(p, &endp, 0); | |
1104 | if (p == endp) | |
1105 | break; | |
1106 | ||
d2105b10 | 1107 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1108 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1109 | "translation for PHB %#x\n", bridge); |
f38db651 | 1110 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1111 | } |
1112 | } | |
1113 | ||
1114 | p = strpbrk(p, ","); | |
1115 | if (!p) | |
1116 | break; | |
1117 | ||
1118 | p++; /* skip ',' */ | |
1119 | } | |
1120 | return 1; | |
1121 | } | |
1122 | __setup("calgary=", calgary_parse_options); |