[PATCH] x86: Don't use MWAIT on AMD Family 10
[linux-2.6-block.git] / arch / x86_64 / kernel / irq.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/x86_64/kernel/irq.c
3 *
4 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
5 *
6 * This file contains the lowest level x86_64-specific interrupt
7 * entry and irq statistics code. All the remaining irq logic is
8 * done by the generic kernel/irq/ code and in the
9 * x86_64-specific irq controller code. (e.g. i8259.c and
10 * io_apic.c.)
11 */
12
13#include <linux/kernel_stat.h>
14#include <linux/interrupt.h>
15#include <linux/seq_file.h>
16#include <linux/module.h>
76e4f660 17#include <linux/delay.h>
1da177e4
LT
18#include <asm/uaccess.h>
19#include <asm/io_apic.h>
95833c83 20#include <asm/idle.h>
2fb12a9b 21#include <asm/smp.h>
1da177e4
LT
22
23atomic_t irq_err_count;
1da177e4 24
4961f10e
ES
25#ifdef CONFIG_DEBUG_STACKOVERFLOW
26/*
27 * Probabilistic stack overflow check:
28 *
29 * Only check the stack in process context, because everything else
30 * runs on the big interrupt stacks. Checking reliably is too expensive,
31 * so we just check from interrupts.
32 */
33static inline void stack_overflow_check(struct pt_regs *regs)
34{
35 u64 curbase = (u64) current->thread_info;
36 static unsigned long warned = -60*HZ;
37
38 if (regs->rsp >= curbase && regs->rsp <= curbase + THREAD_SIZE &&
39 regs->rsp < curbase + sizeof(struct thread_info) + 128 &&
40 time_after(jiffies, warned + 60*HZ)) {
41 printk("do_IRQ: %s near stack overflow (cur:%Lx,rsp:%lx)\n",
42 current->comm, curbase, regs->rsp);
43 show_stack(NULL,NULL);
44 warned = jiffies;
45 }
46}
47#endif
48
1da177e4
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49/*
50 * Generic, controller-independent functions:
51 */
52
53int show_interrupts(struct seq_file *p, void *v)
54{
55 int i = *(loff_t *) v, j;
56 struct irqaction * action;
57 unsigned long flags;
58
59 if (i == 0) {
60 seq_printf(p, " ");
394e3902 61 for_each_online_cpu(j)
bdbdaa79 62 seq_printf(p, "CPU%-8d",j);
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LT
63 seq_putc(p, '\n');
64 }
65
66 if (i < NR_IRQS) {
67 spin_lock_irqsave(&irq_desc[i].lock, flags);
68 action = irq_desc[i].action;
69 if (!action)
70 goto skip;
71 seq_printf(p, "%3d: ",i);
72#ifndef CONFIG_SMP
73 seq_printf(p, "%10u ", kstat_irqs(i));
74#else
394e3902
AM
75 for_each_online_cpu(j)
76 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
1da177e4 77#endif
f29bd1ba 78 seq_printf(p, " %8s", irq_desc[i].chip->name);
a460e745 79 seq_printf(p, "-%-8s", irq_desc[i].name);
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80
81 seq_printf(p, " %s", action->name);
82 for (action=action->next; action; action = action->next)
83 seq_printf(p, ", %s", action->name);
84 seq_putc(p, '\n');
85skip:
86 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
87 } else if (i == NR_IRQS) {
88 seq_printf(p, "NMI: ");
394e3902
AM
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", cpu_pda(j)->__nmi_count);
1da177e4 91 seq_putc(p, '\n');
1da177e4 92 seq_printf(p, "LOC: ");
394e3902
AM
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", cpu_pda(j)->apic_timer_irqs);
1da177e4 95 seq_putc(p, '\n');
1da177e4 96 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
1da177e4
LT
97 }
98 return 0;
99}
100
101/*
102 * do_IRQ handles all normal device IRQ's (the special
103 * SMP cross-CPU interrupts have their own specific
104 * handlers).
105 */
106asmlinkage unsigned int do_IRQ(struct pt_regs *regs)
7d12e780
DH
107{
108 struct pt_regs *old_regs = set_irq_regs(regs);
109
19eadf98 110 /* high bit used in ret_from_ code */
e500f574
EB
111 unsigned vector = ~regs->orig_rax;
112 unsigned irq;
113
114 exit_idle();
115 irq_enter();
550f2299 116 irq = __get_cpu_var(vector_irq)[vector];
1da177e4 117
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ES
118#ifdef CONFIG_DEBUG_STACKOVERFLOW
119 stack_overflow_check(regs);
120#endif
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EB
121
122 if (likely(irq < NR_IRQS))
123 generic_handle_irq(irq);
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EB
124 else {
125 if (!disable_apic)
126 ack_APIC_irq();
127
128 if (printk_ratelimit())
129 printk(KERN_EMERG "%s: %d.%d No irq handler for vector\n",
130 __func__, smp_processor_id(), vector);
131 }
d3696cf7 132
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133 irq_exit();
134
7d12e780 135 set_irq_regs(old_regs);
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136 return 1;
137}
138
76e4f660
AR
139#ifdef CONFIG_HOTPLUG_CPU
140void fixup_irqs(cpumask_t map)
141{
142 unsigned int irq;
143 static int warned;
144
145 for (irq = 0; irq < NR_IRQS; irq++) {
146 cpumask_t mask;
147 if (irq == 2)
148 continue;
149
a53da52f 150 cpus_and(mask, irq_desc[irq].affinity, map);
76e4f660
AR
151 if (any_online_cpu(mask) == NR_CPUS) {
152 printk("Breaking affinity for irq %i\n", irq);
153 mask = map;
154 }
d1bef4ed
IM
155 if (irq_desc[irq].chip->set_affinity)
156 irq_desc[irq].chip->set_affinity(irq, mask);
76e4f660
AR
157 else if (irq_desc[irq].action && !(warned++))
158 printk("Cannot set affinity for irq %i\n", irq);
159 }
160
161 /* That doesn't seem sufficient. Give it 1ms. */
162 local_irq_enable();
163 mdelay(1);
164 local_irq_disable();
165}
166#endif
ed6b676c
AK
167
168extern void call_softirq(void);
169
170asmlinkage void do_softirq(void)
171{
172 __u32 pending;
173 unsigned long flags;
174
175 if (in_interrupt())
176 return;
177
178 local_irq_save(flags);
179 pending = local_softirq_pending();
180 /* Switch to interrupt stack */
2601e64d 181 if (pending) {
ed6b676c 182 call_softirq();
2601e64d
IM
183 WARN_ON_ONCE(softirq_count());
184 }
ed6b676c
AK
185 local_irq_restore(flags);
186}
187EXPORT_SYMBOL(do_softirq);