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Fix misspellings collected by members of KJ list.
[linux-2.6-block.git] / arch / x86_64 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
ab688059
AK		 34#ifdef CONFIG_ACPI
35#include <acpi/acpi_bus.h>
36#endif
1da177e4 37
61014292 38#include <asm/idle.h>
1da177e4
LT		 39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/proto.h>
43#include <asm/mach_apic.h>
8d916406 44#include <asm/acpi.h>
ca8642f6 45#include <asm/dma.h>
3e4ff115 46#include <asm/nmi.h>
589e367f 47#include <asm/msidef.h>
8b955b0d 48#include <asm/hypertransport.h>
1da177e4 49
13a79503
EB		 50struct irq_cfg {
51 cpumask_t domain;
61014292
EB		 52 cpumask_t old_domain;
53 unsigned move_cleanup_count;
13a79503 54 u8 vector;
61014292 55 u8 move_in_progress : 1;
13a79503
EB		 56};
57
58/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
59struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
bc5e81a1
EB		 60 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
61 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
62 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
63 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
64 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
65 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
66 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
67 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
68 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
69 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
70 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
71 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
72 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
73 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
74 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
75 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 76};
77
dfbffdd8 78static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 79
1da177e4
LT		 80#define __apicdebuginit __init
81
82int sis_apic_bug; /* not actually supported, dummy for compile */
83
14d98cad
AK		 84static int no_timer_check;
85
fea5f1e1
LT		 86static int disable_timer_pin_1 __initdata;
87
88int timer_over_8254 __initdata = 1;
89
1008fddc
EB		 90/* Where if anywhere is the i8259 connect in external int mode */
91static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92
1da177e4 93static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 94DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 95
96/*
97 * # of IRQ routing registers
98 */
99int nr_ioapic_registers[MAX_IO_APICS];
100
101/*
102 * Rough estimation of how many shared IRQs there are, can
103 * be changed anytime.
104 */
e273d140 105#define MAX_PLUS_SHARED_IRQS NR_IRQS
1da177e4
LT		 106#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
107
108/*
109 * This is performance-critical, we want to do it O(1)
110 *
111 * the indexing order of this array favors 1:1 mappings
112 * between pins and IRQs.
113 */
114
115static struct irq_pin_list {
116 short apic, pin, next;
117} irq_2_pin[PIN_MAP_SIZE];
118
6c0ffb9d
LT		 119struct io_apic {
120 unsigned int index;
121 unsigned int unused[3];
122 unsigned int data;
123};
124
125static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
126{
127 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
128 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
129}
130
131static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132{
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 writel(reg, &io_apic->index);
135 return readl(&io_apic->data);
136}
137
138static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
139{
140 struct io_apic __iomem *io_apic = io_apic_base(apic);
141 writel(reg, &io_apic->index);
142 writel(value, &io_apic->data);
143}
144
145/*
146 * Re-write a value: to be used for read-modify-write
147 * cycles where the read already set up the index register.
148 */
149static inline void io_apic_modify(unsigned int apic, unsigned int value)
150{
151 struct io_apic __iomem *io_apic = io_apic_base(apic);
152 writel(value, &io_apic->data);
153}
154
155/*
156 * Synchronize the IO-APIC and the CPU by doing
157 * a dummy read from the IO-APIC
158 */
159static inline void io_apic_sync(unsigned int apic)
160{
161 struct io_apic __iomem *io_apic = io_apic_base(apic);
162 readl(&io_apic->data);
163}
164
54d5d424
AR		 165#define __DO_ACTION(R, ACTION, FINAL) \
166 \
167{ \
168 int pin; \
169 struct irq_pin_list *entry = irq_2_pin + irq; \
170 \
6004e1b7 171 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 172 for (;;) { \
173 unsigned int reg; \
174 pin = entry->pin; \
175 if (pin == -1) \
176 break; \
177 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
178 reg ACTION; \
179 io_apic_modify(entry->apic, reg); \
f45bcd70 180 FINAL; \
54d5d424
AR		 181 if (!entry->next) \
182 break; \
183 entry = irq_2_pin + entry->next; \
184 } \
54d5d424
AR		 185}
186
eea0e11c
AK		 187union entry_union {
188 struct { u32 w1, w2; };
189 struct IO_APIC_route_entry entry;
190};
191
192static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
193{
194 union entry_union eu;
195 unsigned long flags;
196 spin_lock_irqsave(&ioapic_lock, flags);
197 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
198 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
199 spin_unlock_irqrestore(&ioapic_lock, flags);
200 return eu.entry;
201}
202
48797ebd
LT		 203/*
204 * When we write a new IO APIC routing entry, we need to write the high
205 * word first! If the mask bit in the low word is clear, we will enable
206 * the interrupt, and we need to make sure the entry is fully populated
207 * before that happens.
208 */
516d2836
AK		 209static void
210__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 211{
eea0e11c
AK		 212 union entry_union eu;
213 eu.entry = e;
48797ebd
LT		 214 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
215 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 216}
217
218static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
219{
220 unsigned long flags;
221 spin_lock_irqsave(&ioapic_lock, flags);
222 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 223 spin_unlock_irqrestore(&ioapic_lock, flags);
224}
225
226/*
227 * When we mask an IO APIC routing entry, we need to write the low
228 * word first, in order to set the mask bit before we change the
229 * high bits!
230 */
231static void ioapic_mask_entry(int apic, int pin)
232{
233 unsigned long flags;
234 union entry_union eu = { .entry.mask = 1 };
235
eea0e11c
AK		 236 spin_lock_irqsave(&ioapic_lock, flags);
237 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
238 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
239 spin_unlock_irqrestore(&ioapic_lock, flags);
240}
241
54d5d424 242#ifdef CONFIG_SMP
550f2299
EB		 243static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
244{
245 int apic, pin;
246 struct irq_pin_list *entry = irq_2_pin + irq;
247
248 BUG_ON(irq >= NR_IRQS);
249 for (;;) {
250 unsigned int reg;
251 apic = entry->apic;
252 pin = entry->pin;
253 if (pin == -1)
254 break;
255 io_apic_write(apic, 0x11 + pin*2, dest);
256 reg = io_apic_read(apic, 0x10 + pin*2);
257 reg &= ~0x000000ff;
258 reg |= vector;
259 io_apic_modify(apic, reg);
260 if (!entry->next)
261 break;
262 entry = irq_2_pin + entry->next;
263 }
264}
265
54d5d424
AR		 266static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
267{
dfbffdd8 268 struct irq_cfg *cfg = irq_cfg + irq;
54d5d424
AR		 269 unsigned long flags;
270 unsigned int dest;
271 cpumask_t tmp;
272
273 cpus_and(tmp, mask, cpu_online_map);
274 if (cpus_empty(tmp))
5ff5115e 275 return;
54d5d424 276
dfbffdd8 277 if (assign_irq_vector(irq, mask))
550f2299
EB		 278 return;
279
dfbffdd8 280 cpus_and(tmp, cfg->domain, mask);
550f2299 281 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 282
283 /*
284 * Only the high 8 bits are valid.
285 */
286 dest = SET_APIC_LOGICAL_ID(dest);
287
288 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 289 __target_IO_APIC_irq(irq, dest, cfg->vector);
9f0a5ba5 290 irq_desc[irq].affinity = mask;
54d5d424
AR		 291 spin_unlock_irqrestore(&ioapic_lock, flags);
292}
293#endif
294
1da177e4
LT		 295/*
296 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
297 * shared ISA-space IRQs, so we have to support them. We are super
298 * fast in the common case, and fast for shared ISA-space IRQs.
299 */
300static void add_pin_to_irq(unsigned int irq, int apic, int pin)
301{
302 static int first_free_entry = NR_IRQS;
303 struct irq_pin_list *entry = irq_2_pin + irq;
304
6004e1b7 305 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 306 while (entry->next)
307 entry = irq_2_pin + entry->next;
308
309 if (entry->pin != -1) {
310 entry->next = first_free_entry;
311 entry = irq_2_pin + entry->next;
312 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 313 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 314 }
315 entry->apic = apic;
316 entry->pin = pin;
317}
318
1da177e4
LT		 319
320#define DO_ACTION(name,R,ACTION, FINAL) \
321 \
322 static void name##_IO_APIC_irq (unsigned int irq) \
323 __DO_ACTION(R, ACTION, FINAL)
324
325DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
326 /* mask = 1 */
327DO_ACTION( __unmask, 0, &= 0xfffeffff, )
328 /* mask = 0 */
329
330static void mask_IO_APIC_irq (unsigned int irq)
331{
332 unsigned long flags;
333
334 spin_lock_irqsave(&ioapic_lock, flags);
335 __mask_IO_APIC_irq(irq);
336 spin_unlock_irqrestore(&ioapic_lock, flags);
337}
338
339static void unmask_IO_APIC_irq (unsigned int irq)
340{
341 unsigned long flags;
342
343 spin_lock_irqsave(&ioapic_lock, flags);
344 __unmask_IO_APIC_irq(irq);
345 spin_unlock_irqrestore(&ioapic_lock, flags);
346}
347
348static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
349{
350 struct IO_APIC_route_entry entry;
1da177e4
LT		 351
352 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 353 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 354 if (entry.delivery_mode == dest_SMI)
355 return;
356 /*
357 * Disable it in the IO-APIC irq-routing table:
358 */
48797ebd 359 ioapic_mask_entry(apic, pin);
1da177e4
LT		 360}
361
362static void clear_IO_APIC (void)
363{
364 int apic, pin;
365
366 for (apic = 0; apic < nr_ioapics; apic++)
367 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
368 clear_IO_APIC_pin(apic, pin);
369}
370
1da177e4
LT		 371int skip_ioapic_setup;
372int ioapic_force;
373
374/* dummy parsing: see setup.c */
375
376static int __init disable_ioapic_setup(char *str)
377{
378 skip_ioapic_setup = 1;
2c8c0e6b 379 return 0;
1da177e4 380}
2c8c0e6b 381early_param("noapic", disable_ioapic_setup);
1da177e4 382
fea5f1e1
LT		 383/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
384static int __init disable_timer_pin_setup(char *arg)
385{
386 disable_timer_pin_1 = 1;
387 return 1;
388}
389__setup("disable_timer_pin_1", disable_timer_pin_setup);
390
391static int __init setup_disable_8254_timer(char *s)
392{
393 timer_over_8254 = -1;
394 return 1;
395}
396static int __init setup_enable_8254_timer(char *s)
397{
398 timer_over_8254 = 2;
399 return 1;
400}
401
402__setup("disable_8254_timer", setup_disable_8254_timer);
403__setup("enable_8254_timer", setup_enable_8254_timer);
404
405
1da177e4
LT		 406/*
407 * Find the IRQ entry number of a certain pin.
408 */
409static int find_irq_entry(int apic, int pin, int type)
410{
411 int i;
412
413 for (i = 0; i < mp_irq_entries; i++)
414 if (mp_irqs[i].mpc_irqtype == type &&
415 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
416 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
417 mp_irqs[i].mpc_dstirq == pin)
418 return i;
419
420 return -1;
421}
422
423/*
424 * Find the pin to which IRQ[irq] (ISA) is connected
425 */
1008fddc 426static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 427{
428 int i;
429
430 for (i = 0; i < mp_irq_entries; i++) {
431 int lbus = mp_irqs[i].mpc_srcbus;
432
55f05ffa 433 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 434 (mp_irqs[i].mpc_irqtype == type) &&
435 (mp_irqs[i].mpc_srcbusirq == irq))
436
437 return mp_irqs[i].mpc_dstirq;
438 }
439 return -1;
440}
441
1008fddc
EB		 442static int __init find_isa_irq_apic(int irq, int type)
443{
444 int i;
445
446 for (i = 0; i < mp_irq_entries; i++) {
447 int lbus = mp_irqs[i].mpc_srcbus;
448
55f05ffa 449 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 450 (mp_irqs[i].mpc_irqtype == type) &&
451 (mp_irqs[i].mpc_srcbusirq == irq))
452 break;
453 }
454 if (i < mp_irq_entries) {
455 int apic;
456 for(apic = 0; apic < nr_ioapics; apic++) {
457 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
458 return apic;
459 }
460 }
461
462 return -1;
463}
464
1da177e4
LT		 465/*
466 * Find a specific PCI IRQ entry.
467 * Not an __init, possibly needed by modules
468 */
469static int pin_2_irq(int idx, int apic, int pin);
470
471int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
472{
473 int apic, i, best_guess = -1;
474
475 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
476 bus, slot, pin);
477 if (mp_bus_id_to_pci_bus[bus] == -1) {
478 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
479 return -1;
480 }
481 for (i = 0; i < mp_irq_entries; i++) {
482 int lbus = mp_irqs[i].mpc_srcbus;
483
484 for (apic = 0; apic < nr_ioapics; apic++)
485 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
486 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
487 break;
488
55f05ffa 489 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 490 !mp_irqs[i].mpc_irqtype &&
491 (bus == lbus) &&
492 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
493 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
494
495 if (!(apic || IO_APIC_IRQ(irq)))
496 continue;
497
498 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
499 return irq;
500 /*
501 * Use the first all-but-pin matching entry as a
502 * best-guess fuzzy result for broken mptables.
503 */
504 if (best_guess < 0)
505 best_guess = irq;
506 }
507 }
6004e1b7 508 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 509 return best_guess;
510}
511
1da177e4
LT		 512/* ISA interrupts are always polarity zero edge triggered,
513 * when listed as conforming in the MP table. */
514
515#define default_ISA_trigger(idx) (0)
516#define default_ISA_polarity(idx) (0)
517
518/* PCI interrupts are always polarity one level triggered,
519 * when listed as conforming in the MP table. */
520
521#define default_PCI_trigger(idx) (1)
522#define default_PCI_polarity(idx) (1)
523
1da177e4
LT		 524static int __init MPBIOS_polarity(int idx)
525{
526 int bus = mp_irqs[idx].mpc_srcbus;
527 int polarity;
528
529 /*
530 * Determine IRQ line polarity (high active or low active):
531 */
532 switch (mp_irqs[idx].mpc_irqflag & 3)
533 {
534 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 535 if (test_bit(bus, mp_bus_not_pci))
536 polarity = default_ISA_polarity(idx);
537 else
538 polarity = default_PCI_polarity(idx);
1da177e4 539 break;
1da177e4
LT		 540 case 1: /* high active */
541 {
542 polarity = 0;
543 break;
544 }
545 case 2: /* reserved */
546 {
547 printk(KERN_WARNING "broken BIOS!!\n");
548 polarity = 1;
549 break;
550 }
551 case 3: /* low active */
552 {
553 polarity = 1;
554 break;
555 }
556 default: /* invalid */
557 {
558 printk(KERN_WARNING "broken BIOS!!\n");
559 polarity = 1;
560 break;
561 }
562 }
563 return polarity;
564}
565
566static int MPBIOS_trigger(int idx)
567{
568 int bus = mp_irqs[idx].mpc_srcbus;
569 int trigger;
570
571 /*
572 * Determine IRQ trigger mode (edge or level sensitive):
573 */
574 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
575 {
576 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 577 if (test_bit(bus, mp_bus_not_pci))
578 trigger = default_ISA_trigger(idx);
579 else
580 trigger = default_PCI_trigger(idx);
1da177e4 581 break;
1da177e4
LT		 582 case 1: /* edge */
583 {
584 trigger = 0;
585 break;
586 }
587 case 2: /* reserved */
588 {
589 printk(KERN_WARNING "broken BIOS!!\n");
590 trigger = 1;
591 break;
592 }
593 case 3: /* level */
594 {
595 trigger = 1;
596 break;
597 }
598 default: /* invalid */
599 {
600 printk(KERN_WARNING "broken BIOS!!\n");
601 trigger = 0;
602 break;
603 }
604 }
605 return trigger;
606}
607
608static inline int irq_polarity(int idx)
609{
610 return MPBIOS_polarity(idx);
611}
612
613static inline int irq_trigger(int idx)
614{
615 return MPBIOS_trigger(idx);
616}
617
618static int pin_2_irq(int idx, int apic, int pin)
619{
620 int irq, i;
621 int bus = mp_irqs[idx].mpc_srcbus;
622
623 /*
624 * Debugging check, we are in big trouble if this message pops up!
625 */
626 if (mp_irqs[idx].mpc_dstirq != pin)
627 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
628
55f05ffa
AK		 629 if (test_bit(bus, mp_bus_not_pci)) {
630 irq = mp_irqs[idx].mpc_srcbusirq;
631 } else {
632 /*
633 * PCI IRQs are mapped in order
634 */
635 i = irq = 0;
636 while (i < apic)
637 irq += nr_ioapic_registers[i++];
638 irq += pin;
1da177e4 639 }
6004e1b7 640 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 641 return irq;
642}
643
dfbffdd8 644static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 645{
550f2299
EB		 646 /*
647 * NOTE! The local APIC isn't very good at handling
648 * multiple interrupts at the same interrupt level.
649 * As the interrupt level is determined by taking the
650 * vector number and shifting that right by 4, we
651 * want to spread these out a bit so that they don't
652 * all fall in the same interrupt level.
653 *
654 * Also, we've got to be careful not to trash gate
655 * 0x80, because int 0x80 is hm, kind of importantish. ;)
656 */
d1752aa8 657 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 658 unsigned int old_vector;
550f2299 659 int cpu;
13a79503 660 struct irq_cfg *cfg;
1da177e4 661
e273d140 662 BUG_ON((unsigned)irq >= NR_IRQS);
13a79503 663 cfg = &irq_cfg[irq];
0a1ad60d 664
70a0a535
EB		 665 /* Only try and allocate irqs on cpus that are present */
666 cpus_and(mask, mask, cpu_online_map);
667
61014292
EB		 668 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
669 return -EBUSY;
670
dfbffdd8
EB		 671 old_vector = cfg->vector;
672 if (old_vector) {
673 cpumask_t tmp;
674 cpus_and(tmp, cfg->domain, mask);
675 if (!cpus_empty(tmp))
676 return 0;
0a1ad60d 677 }
550f2299
EB		 678
679 for_each_cpu_mask(cpu, mask) {
70a0a535 680 cpumask_t domain, new_mask;
61014292 681 int new_cpu;
550f2299 682 int vector, offset;
c7111c13
EB		 683
684 domain = vector_allocation_domain(cpu);
70a0a535 685 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 686
d1752aa8
EB		 687 vector = current_vector;
688 offset = current_offset;
1da177e4 689next:
550f2299
EB		 690 vector += 8;
691 if (vector >= FIRST_SYSTEM_VECTOR) {
692 /* If we run out of vectors on large boxen, must share them. */
693 offset = (offset + 1) % 8;
694 vector = FIRST_DEVICE_VECTOR + offset;
695 }
d1752aa8 696 if (unlikely(current_vector == vector))
550f2299
EB		 697 continue;
698 if (vector == IA32_SYSCALL_VECTOR)
699 goto next;
70a0a535 700 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 701 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 702 goto next;
550f2299 703 /* Found one! */
d1752aa8
EB		 704 current_vector = vector;
705 current_offset = offset;
61014292
EB		 706 if (old_vector) {
707 cfg->move_in_progress = 1;
708 cfg->old_domain = cfg->domain;
709 }
70a0a535 710 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 711 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 712 cfg->vector = vector;
713 cfg->domain = domain;
dfbffdd8 714 return 0;
1da177e4 715 }
550f2299 716 return -ENOSPC;
04b9267b
EB		 717}
718
dfbffdd8 719static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 720{
dfbffdd8 721 int err;
04b9267b 722 unsigned long flags;
0a1ad60d 723
04b9267b 724 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 725 err = __assign_irq_vector(irq, mask);
26a3c49c 726 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 727 return err;
1da177e4
LT		 728}
729
5df0287e
YL		 730static void __clear_irq_vector(int irq)
731{
13a79503 732 struct irq_cfg *cfg;
5df0287e
YL		 733 cpumask_t mask;
734 int cpu, vector;
735
13a79503
EB		 736 BUG_ON((unsigned)irq >= NR_IRQS);
737 cfg = &irq_cfg[irq];
738 BUG_ON(!cfg->vector);
5df0287e 739
13a79503
EB		 740 vector = cfg->vector;
741 cpus_and(mask, cfg->domain, cpu_online_map);
5df0287e
YL		 742 for_each_cpu_mask(cpu, mask)
743 per_cpu(vector_irq, cpu)[vector] = -1;
744
13a79503
EB		 745 cfg->vector = 0;
746 cfg->domain = CPU_MASK_NONE;
5df0287e
YL		 747}
748
70a0a535
EB		 749void __setup_vector_irq(int cpu)
750{
751 /* Initialize vector_irq on a new cpu */
752 /* This function must be called with vector_lock held */
70a0a535
EB		 753 int irq, vector;
754
70a0a535 755 /* Mark the inuse vectors */
e273d140 756 for (irq = 0; irq < NR_IRQS; ++irq) {
13a79503 757 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535 758 continue;
13a79503 759 vector = irq_cfg[irq].vector;
70a0a535
EB		 760 per_cpu(vector_irq, cpu)[vector] = irq;
761 }
762 /* Mark the free vectors */
763 for (vector = 0; vector < NR_VECTORS; ++vector) {
764 irq = per_cpu(vector_irq, cpu)[vector];
765 if (irq < 0)
766 continue;
13a79503 767 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535
EB		 768 per_cpu(vector_irq, cpu)[vector] = -1;
769 }
770}
771
772
f29bd1ba 773static struct irq_chip ioapic_chip;
1da177e4 774
a27bc06d 775static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 776{
a8c8a367 777 if (trigger)
a460e745
IM		 778 set_irq_chip_and_handler_name(irq, &ioapic_chip,
779 handle_fasteoi_irq, "fasteoi");
d7e25f33 780 else
a460e745
IM		 781 set_irq_chip_and_handler_name(irq, &ioapic_chip,
782 handle_edge_irq, "edge");
1da177e4 783}
a8c8a367
EB		 784
785static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
786 int trigger, int polarity)
1da177e4 787{
dfbffdd8 788 struct irq_cfg *cfg = irq_cfg + irq;
1da177e4 789 struct IO_APIC_route_entry entry;
a8c8a367 790 cpumask_t mask;
1da177e4 791
a8c8a367
EB		 792 if (!IO_APIC_IRQ(irq))
793 return;
794
dfbffdd8
EB		 795 mask = TARGET_CPUS;
796 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 797 return;
798
dfbffdd8
EB		 799 cpus_and(mask, cfg->domain, mask);
800
a8c8a367
EB		 801 apic_printk(APIC_VERBOSE,KERN_DEBUG
802 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
803 "IRQ %d Mode:%i Active:%i)\n",
dfbffdd8 804 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
a8c8a367 805 irq, trigger, polarity);
1da177e4 806
ad892f5e
YL		 807 /*
808 * add it to the IO-APIC irq-routing table:
809 */
810 memset(&entry,0,sizeof(entry));
1da177e4 811
ad892f5e
YL		 812 entry.delivery_mode = INT_DELIVERY_MODE;
813 entry.dest_mode = INT_DEST_MODE;
a8c8a367 814 entry.dest = cpu_mask_to_apicid(mask);
ad892f5e 815 entry.mask = 0; /* enable IRQ */
a8c8a367
EB		 816 entry.trigger = trigger;
817 entry.polarity = polarity;
dfbffdd8 818 entry.vector = cfg->vector;
1da177e4 819
a8c8a367
EB		 820 /* Mask level triggered irqs.
821 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
822 */
823 if (trigger)
ad892f5e 824 entry.mask = 1;
ad892f5e 825
a8c8a367
EB		 826 ioapic_register_intr(irq, trigger);
827 if (irq < 16)
828 disable_8259A_irq(irq);
ad892f5e
YL		 829
830 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 831}
832
833static void __init setup_IO_APIC_irqs(void)
834{
835 int apic, pin, idx, irq, first_notcon = 1;
836
837 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
838
839 for (apic = 0; apic < nr_ioapics; apic++) {
840 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 841
842 idx = find_irq_entry(apic,pin,mp_INT);
843 if (idx == -1) {
844 if (first_notcon) {
845 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
846 first_notcon = 0;
847 } else
848 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
849 continue;
850 }
851
1da177e4
LT		 852 irq = pin_2_irq(idx, apic, pin);
853 add_pin_to_irq(irq, apic, pin);
854
a8c8a367
EB		 855 setup_IO_APIC_irq(apic, pin, irq,
856 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 857 }
858 }
859
860 if (!first_notcon)
861 apic_printk(APIC_VERBOSE," not connected.\n");
862}
863
864/*
865 * Set up the 8259A-master output pin as broadcast to all
866 * CPUs.
867 */
1008fddc 868static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 869{
870 struct IO_APIC_route_entry entry;
871 unsigned long flags;
872
873 memset(&entry,0,sizeof(entry));
874
875 disable_8259A_irq(0);
876
877 /* mask LVT0 */
11a8e778 878 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 879
880 /*
881 * We use logical delivery to get the timer IRQ
882 * to the first CPU.
883 */
884 entry.dest_mode = INT_DEST_MODE;
885 entry.mask = 0; /* unmask IRQ now */
ee4eff6f 886 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 887 entry.delivery_mode = INT_DELIVERY_MODE;
888 entry.polarity = 0;
889 entry.trigger = 0;
890 entry.vector = vector;
891
892 /*
893 * The timer IRQ doesn't have to know that behind the
894 * scene we have a 8259A-master in AEOI mode ...
895 */
a460e745 896 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 897
898 /*
899 * Add it to the IO-APIC irq-routing table:
900 */
901 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 902 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
903 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 904 spin_unlock_irqrestore(&ioapic_lock, flags);
905
906 enable_8259A_irq(0);
907}
908
1da177e4
LT		 909void __apicdebuginit print_IO_APIC(void)
910{
911 int apic, i;
912 union IO_APIC_reg_00 reg_00;
913 union IO_APIC_reg_01 reg_01;
914 union IO_APIC_reg_02 reg_02;
915 unsigned long flags;
916
917 if (apic_verbosity == APIC_QUIET)
918 return;
919
920 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
921 for (i = 0; i < nr_ioapics; i++)
922 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
923 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
924
925 /*
926 * We are a bit conservative about what we expect. We have to
927 * know about every hardware change ASAP.
928 */
929 printk(KERN_INFO "testing the IO APIC.......................\n");
930
931 for (apic = 0; apic < nr_ioapics; apic++) {
932
933 spin_lock_irqsave(&ioapic_lock, flags);
934 reg_00.raw = io_apic_read(apic, 0);
935 reg_01.raw = io_apic_read(apic, 1);
936 if (reg_01.bits.version >= 0x10)
937 reg_02.raw = io_apic_read(apic, 2);
938 spin_unlock_irqrestore(&ioapic_lock, flags);
939
940 printk("\n");
941 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
942 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
943 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 944
945 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
946 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 947
948 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
949 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 950
951 if (reg_01.bits.version >= 0x10) {
952 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
953 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 954 }
955
956 printk(KERN_DEBUG ".... IRQ redirection table:\n");
957
ee4eff6f
BR		 958 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
959 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 960
961 for (i = 0; i <= reg_01.bits.entries; i++) {
962 struct IO_APIC_route_entry entry;
963
eea0e11c 964 entry = ioapic_read_entry(apic, i);
1da177e4 965
ee4eff6f 966 printk(KERN_DEBUG " %02x %03X ",
1da177e4 967 i,
ee4eff6f 968 entry.dest
1da177e4
LT		 969 );
970
971 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
972 entry.mask,
973 entry.trigger,
974 entry.irr,
975 entry.polarity,
976 entry.delivery_status,
977 entry.dest_mode,
978 entry.delivery_mode,
979 entry.vector
980 );
981 }
982 }
1da177e4
LT		 983 printk(KERN_DEBUG "IRQ to pin mappings:\n");
984 for (i = 0; i < NR_IRQS; i++) {
985 struct irq_pin_list *entry = irq_2_pin + i;
986 if (entry->pin < 0)
987 continue;
04b9267b 988 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 989 for (;;) {
990 printk("-> %d:%d", entry->apic, entry->pin);
991 if (!entry->next)
992 break;
993 entry = irq_2_pin + entry->next;
994 }
995 printk("\n");
996 }
997
998 printk(KERN_INFO ".................................... done.\n");
999
1000 return;
1001}
1002
1003#if 0
1004
1005static __apicdebuginit void print_APIC_bitfield (int base)
1006{
1007 unsigned int v;
1008 int i, j;
1009
1010 if (apic_verbosity == APIC_QUIET)
1011 return;
1012
1013 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1014 for (i = 0; i < 8; i++) {
1015 v = apic_read(base + i*0x10);
1016 for (j = 0; j < 32; j++) {
1017 if (v & (1<<j))
1018 printk("1");
1019 else
1020 printk("0");
1021 }
1022 printk("\n");
1023 }
1024}
1025
1026void __apicdebuginit print_local_APIC(void * dummy)
1027{
1028 unsigned int v, ver, maxlvt;
1029
1030 if (apic_verbosity == APIC_QUIET)
1031 return;
1032
1033 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1034 smp_processor_id(), hard_smp_processor_id());
1035 v = apic_read(APIC_ID);
1036 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1037 v = apic_read(APIC_LVR);
1038 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1039 ver = GET_APIC_VERSION(v);
1040 maxlvt = get_maxlvt();
1041
1042 v = apic_read(APIC_TASKPRI);
1043 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1044
5a40b7c2
AK		 1045 v = apic_read(APIC_ARBPRI);
1046 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1047 v & APIC_ARBPRI_MASK);
1048 v = apic_read(APIC_PROCPRI);
1049 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1050
1051 v = apic_read(APIC_EOI);
1052 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1053 v = apic_read(APIC_RRR);
1054 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1055 v = apic_read(APIC_LDR);
1056 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1057 v = apic_read(APIC_DFR);
1058 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1059 v = apic_read(APIC_SPIV);
1060 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1061
1062 printk(KERN_DEBUG "... APIC ISR field:\n");
1063 print_APIC_bitfield(APIC_ISR);
1064 printk(KERN_DEBUG "... APIC TMR field:\n");
1065 print_APIC_bitfield(APIC_TMR);
1066 printk(KERN_DEBUG "... APIC IRR field:\n");
1067 print_APIC_bitfield(APIC_IRR);
1068
5a40b7c2
AK		 1069 v = apic_read(APIC_ESR);
1070 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1071
1072 v = apic_read(APIC_ICR);
1073 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1074 v = apic_read(APIC_ICR2);
1075 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1076
1077 v = apic_read(APIC_LVTT);
1078 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1079
1080 if (maxlvt > 3) { /* PC is LVT#4. */
1081 v = apic_read(APIC_LVTPC);
1082 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1083 }
1084 v = apic_read(APIC_LVT0);
1085 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1086 v = apic_read(APIC_LVT1);
1087 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1088
1089 if (maxlvt > 2) { /* ERR is LVT#3. */
1090 v = apic_read(APIC_LVTERR);
1091 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1092 }
1093
1094 v = apic_read(APIC_TMICT);
1095 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1096 v = apic_read(APIC_TMCCT);
1097 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1098 v = apic_read(APIC_TDCR);
1099 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1100 printk("\n");
1101}
1102
1103void print_all_local_APICs (void)
1104{
1105 on_each_cpu(print_local_APIC, NULL, 1, 1);
1106}
1107
1108void __apicdebuginit print_PIC(void)
1109{
1da177e4
LT		 1110 unsigned int v;
1111 unsigned long flags;
1112
1113 if (apic_verbosity == APIC_QUIET)
1114 return;
1115
1116 printk(KERN_DEBUG "\nprinting PIC contents\n");
1117
1118 spin_lock_irqsave(&i8259A_lock, flags);
1119
1120 v = inb(0xa1) << 8 | inb(0x21);
1121 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1122
1123 v = inb(0xa0) << 8 | inb(0x20);
1124 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1125
1126 outb(0x0b,0xa0);
1127 outb(0x0b,0x20);
1128 v = inb(0xa0) << 8 | inb(0x20);
1129 outb(0x0a,0xa0);
1130 outb(0x0a,0x20);
1131
1132 spin_unlock_irqrestore(&i8259A_lock, flags);
1133
1134 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1135
1136 v = inb(0x4d1) << 8 | inb(0x4d0);
1137 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1138}
1139
1140#endif /* 0 */
1141
1142static void __init enable_IO_APIC(void)
1143{
1144 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1145 int i8259_apic, i8259_pin;
1146 int i, apic;
1da177e4
LT		 1147 unsigned long flags;
1148
1149 for (i = 0; i < PIN_MAP_SIZE; i++) {
1150 irq_2_pin[i].pin = -1;
1151 irq_2_pin[i].next = 0;
1152 }
1da177e4
LT		 1153
1154 /*
1155 * The number of IO-APIC IRQ registers (== #pins):
1156 */
1008fddc 1157 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1158 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1159 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1160 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1161 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1162 }
1163 for(apic = 0; apic < nr_ioapics; apic++) {
1164 int pin;
1165 /* See if any of the pins is in ExtINT mode */
1166 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1167 struct IO_APIC_route_entry entry;
eea0e11c 1168 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1169
1170 /* If the interrupt line is enabled and in ExtInt mode
1171 * I have found the pin where the i8259 is connected.
1172 */
1173 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1174 ioapic_i8259.apic = apic;
1175 ioapic_i8259.pin = pin;
1176 goto found_i8259;
1177 }
1178 }
1179 }
1180 found_i8259:
1181 /* Look to see what if the MP table has reported the ExtINT */
1182 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1183 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1184 /* Trust the MP table if nothing is setup in the hardware */
1185 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1186 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1187 ioapic_i8259.pin = i8259_pin;
1188 ioapic_i8259.apic = i8259_apic;
1189 }
1190 /* Complain if the MP table and the hardware disagree */
1191 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1192 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1193 {
1194 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1195 }
1196
1197 /*
1198 * Do not trust the IO-APIC being empty at bootup
1199 */
1200 clear_IO_APIC();
1201}
1202
1203/*
1204 * Not an __init, needed by the reboot code
1205 */
1206void disable_IO_APIC(void)
1207{
1208 /*
1209 * Clear the IO-APIC before rebooting:
1210 */
1211 clear_IO_APIC();
1212
208fb931 1213 /*
0b968d23 1214 * If the i8259 is routed through an IOAPIC
208fb931 1215 * Put that IOAPIC in virtual wire mode
0b968d23 1216 * so legacy interrupts can be delivered.
208fb931 1217 */
1008fddc 1218 if (ioapic_i8259.pin != -1) {
208fb931 1219 struct IO_APIC_route_entry entry;
208fb931
EB		 1220
1221 memset(&entry, 0, sizeof(entry));
1222 entry.mask = 0; /* Enabled */
1223 entry.trigger = 0; /* Edge */
1224 entry.irr = 0;
1225 entry.polarity = 0; /* High */
1226 entry.delivery_status = 0;
1227 entry.dest_mode = 0; /* Physical */
1008fddc 1228 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1229 entry.vector = 0;
ee4eff6f 1230 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
208fb931 1231
208fb931
EB		 1232 /*
1233 * Add it to the IO-APIC irq-routing table:
1234 */
eea0e11c 1235 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1236 }
1237
1008fddc 1238 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1239}
1240
1da177e4
LT		 1241/*
1242 * There is a nasty bug in some older SMP boards, their mptable lies
1243 * about the timer IRQ. We do the following to work around the situation:
1244 *
1245 * - timer IRQ defaults to IO-APIC IRQ
1246 * - if this function detects that timer IRQs are defunct, then we fall
1247 * back to ISA timer IRQs
1248 */
1249static int __init timer_irq_works(void)
1250{
1251 unsigned long t1 = jiffies;
1252
1253 local_irq_enable();
1254 /* Let ten ticks pass... */
1255 mdelay((10 * 1000) / HZ);
1256
1257 /*
1258 * Expect a few ticks at least, to be sure some possible
1259 * glue logic does not lock up after one or two first
1260 * ticks in a non-ExtINT mode. Also the local APIC
1261 * might have cached one ExtINT interrupt. Finally, at
1262 * least one tick may be lost due to delays.
1263 */
1264
1265 /* jiffies wrap? */
1266 if (jiffies - t1 > 4)
1267 return 1;
1268 return 0;
1269}
1270
1271/*
1272 * In the SMP+IOAPIC case it might happen that there are an unspecified
1273 * number of pending IRQ events unhandled. These cases are very rare,
1274 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1275 * better to do it this way as thus we do not have to be aware of
1276 * 'pending' interrupts in the IRQ path, except at this point.
1277 */
1278/*
1279 * Edge triggered needs to resend any interrupt
1280 * that was delayed but this is now handled in the device
1281 * independent code.
1282 */
1283
1284/*
1285 * Starting up a edge-triggered IO-APIC interrupt is
1286 * nasty - we need to make sure that we get the edge.
1287 * If it is already asserted for some reason, we need
1288 * return 1 to indicate that is was pending.
1289 *
1290 * This is not complete - we should be able to fake
1291 * an edge even if it isn't on the 8259A...
1292 */
1293
f29bd1ba 1294static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1295{
1296 int was_pending = 0;
1297 unsigned long flags;
1298
1299 spin_lock_irqsave(&ioapic_lock, flags);
1300 if (irq < 16) {
1301 disable_8259A_irq(irq);
1302 if (i8259A_irq_pending(irq))
1303 was_pending = 1;
1304 }
1305 __unmask_IO_APIC_irq(irq);
1306 spin_unlock_irqrestore(&ioapic_lock, flags);
1307
1308 return was_pending;
1309}
1310
04b9267b 1311static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1312{
13a79503 1313 struct irq_cfg *cfg = &irq_cfg[irq];
550f2299 1314 cpumask_t mask;
6bf2dafa 1315 unsigned long flags;
550f2299 1316
6bf2dafa 1317 spin_lock_irqsave(&vector_lock, flags);
550f2299 1318 cpus_clear(mask);
13a79503 1319 cpu_set(first_cpu(cfg->domain), mask);
550f2299 1320
13a79503 1321 send_IPI_mask(mask, cfg->vector);
6bf2dafa 1322 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1323
1324 return 1;
1325}
1326
1da177e4
LT		 1327/*
1328 * Level and edge triggered IO-APIC interrupts need different handling,
1329 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1330 * handled with the level-triggered descriptor, but that one has slightly
1331 * more overhead. Level-triggered interrupts cannot be handled with the
1332 * edge-triggered handler, without risking IRQ storms and other ugly
1333 * races.
1334 */
1335
61014292
EB		 1336#ifdef CONFIG_SMP
1337asmlinkage void smp_irq_move_cleanup_interrupt(void)
1338{
1339 unsigned vector, me;
1340 ack_APIC_irq();
1341 exit_idle();
1342 irq_enter();
1343
1344 me = smp_processor_id();
1345 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1346 unsigned int irq;
1347 struct irq_desc *desc;
1348 struct irq_cfg *cfg;
1349 irq = __get_cpu_var(vector_irq)[vector];
1350 if (irq >= NR_IRQS)
1351 continue;
1352
1353 desc = irq_desc + irq;
1354 cfg = irq_cfg + irq;
1355 spin_lock(&desc->lock);
1356 if (!cfg->move_cleanup_count)
1357 goto unlock;
1358
1359 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1360 goto unlock;
1361
1362 __get_cpu_var(vector_irq)[vector] = -1;
1363 cfg->move_cleanup_count--;
1364unlock:
1365 spin_unlock(&desc->lock);
1366 }
1367
1368 irq_exit();
1369}
1370
1371static void irq_complete_move(unsigned int irq)
1372{
1373 struct irq_cfg *cfg = irq_cfg + irq;
1374 unsigned vector, me;
1375
1376 if (likely(!cfg->move_in_progress))
1377 return;
1378
1379 vector = ~get_irq_regs()->orig_rax;
1380 me = smp_processor_id();
f0e13ae7 1381 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1382 cpumask_t cleanup_mask;
1383
1384 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1385 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1386 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1387 cfg->move_in_progress = 0;
1388 }
1389}
1390#else
1391static inline void irq_complete_move(unsigned int irq) {}
1392#endif
1393
0be6652f
EB		 1394static void ack_apic_edge(unsigned int irq)
1395{
61014292 1396 irq_complete_move(irq);
0be6652f
EB		 1397 move_native_irq(irq);
1398 ack_APIC_irq();
1399}
1400
1401static void ack_apic_level(unsigned int irq)
1402{
1403 int do_unmask_irq = 0;
1404
61014292 1405 irq_complete_move(irq);
0be6652f
EB		 1406#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1407 /* If we are moving the irq we need to mask it */
1408 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1409 do_unmask_irq = 1;
1410 mask_IO_APIC_irq(irq);
1411 }
1412#endif
1413
1414 /*
1415 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 1416 * not propagate properly.
0be6652f
EB		 1417 */
1418 ack_APIC_irq();
1419
1420 /* Now we can move and renable the irq */
1421 move_masked_irq(irq);
1422 if (unlikely(do_unmask_irq))
1423 unmask_IO_APIC_irq(irq);
1424}
1425
f29bd1ba
IM		 1426static struct irq_chip ioapic_chip __read_mostly = {
1427 .name = "IO-APIC",
04b9267b
EB		 1428 .startup = startup_ioapic_irq,
1429 .mask = mask_IO_APIC_irq,
1430 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1431 .ack = ack_apic_edge,
1432 .eoi = ack_apic_level,
54d5d424 1433#ifdef CONFIG_SMP
04b9267b 1434 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1435#endif
04b9267b 1436 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1437};
1438
1439static inline void init_IO_APIC_traps(void)
1440{
1441 int irq;
1442
1443 /*
1444 * NOTE! The local APIC isn't very good at handling
1445 * multiple interrupts at the same interrupt level.
1446 * As the interrupt level is determined by taking the
1447 * vector number and shifting that right by 4, we
1448 * want to spread these out a bit so that they don't
1449 * all fall in the same interrupt level.
1450 *
1451 * Also, we've got to be careful not to trash gate
1452 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1453 */
1454 for (irq = 0; irq < NR_IRQS ; irq++) {
1455 int tmp = irq;
13a79503 1456 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1da177e4
LT		 1457 /*
1458 * Hmm.. We don't have an entry for this,
1459 * so default to an old-fashioned 8259
1460 * interrupt if we can..
1461 */
1462 if (irq < 16)
1463 make_8259A_irq(irq);
1464 else
1465 /* Strange. Oh, well.. */
f29bd1ba 1466 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1467 }
1468 }
1469}
1470
1471static void enable_lapic_irq (unsigned int irq)
1472{
1473 unsigned long v;
1474
1475 v = apic_read(APIC_LVT0);
11a8e778 1476 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1477}
1478
1479static void disable_lapic_irq (unsigned int irq)
1480{
1481 unsigned long v;
1482
1483 v = apic_read(APIC_LVT0);
11a8e778 1484 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1485}
1486
1487static void ack_lapic_irq (unsigned int irq)
1488{
1489 ack_APIC_irq();
1490}
1491
1492static void end_lapic_irq (unsigned int i) { /* nothing */ }
1493
6c231b7b 1494static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1da177e4
LT		 1495 .typename = "local-APIC-edge",
1496 .startup = NULL, /* startup_irq() not used for IRQ0 */
1497 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1498 .enable = enable_lapic_irq,
1499 .disable = disable_lapic_irq,
1500 .ack = ack_lapic_irq,
1501 .end = end_lapic_irq,
1502};
1503
1504static void setup_nmi (void)
1505{
1506 /*
1507 * Dirty trick to enable the NMI watchdog ...
1508 * We put the 8259A master into AEOI mode and
1509 * unmask on all local APICs LVT0 as NMI.
1510 *
1511 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1512 * is from Maciej W. Rozycki - so we do not have to EOI from
1513 * the NMI handler or the timer interrupt.
1514 */
1515 printk(KERN_INFO "activating NMI Watchdog ...");
1516
1517 enable_NMI_through_LVT0(NULL);
1518
1519 printk(" done.\n");
1520}
1521
1522/*
1523 * This looks a bit hackish but it's about the only one way of sending
1524 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1525 * not support the ExtINT mode, unfortunately. We need to send these
1526 * cycles as some i82489DX-based boards have glue logic that keeps the
1527 * 8259A interrupt line asserted until INTA. --macro
1528 */
1529static inline void unlock_ExtINT_logic(void)
1530{
1008fddc 1531 int apic, pin, i;
1da177e4
LT		 1532 struct IO_APIC_route_entry entry0, entry1;
1533 unsigned char save_control, save_freq_select;
1534 unsigned long flags;
1535
1008fddc
EB		 1536 pin = find_isa_irq_pin(8, mp_INT);
1537 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1538 if (pin == -1)
1539 return;
1540
1541 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1542 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1543 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1544 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1545 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1546
1547 memset(&entry1, 0, sizeof(entry1));
1548
1549 entry1.dest_mode = 0; /* physical delivery */
1550 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 1551 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 1552 entry1.delivery_mode = dest_ExtINT;
1553 entry1.polarity = entry0.polarity;
1554 entry1.trigger = 0;
1555 entry1.vector = 0;
1556
1557 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1558 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1559 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1560 spin_unlock_irqrestore(&ioapic_lock, flags);
1561
1562 save_control = CMOS_READ(RTC_CONTROL);
1563 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1564 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1565 RTC_FREQ_SELECT);
1566 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1567
1568 i = 100;
1569 while (i-- > 0) {
1570 mdelay(10);
1571 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1572 i -= 10;
1573 }
1574
1575 CMOS_WRITE(save_control, RTC_CONTROL);
1576 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1577 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1578
1579 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1580 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1581 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1582 spin_unlock_irqrestore(&ioapic_lock, flags);
1583}
1584
1585/*
1586 * This code may look a bit paranoid, but it's supposed to cooperate with
1587 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1588 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1589 * fanatically on his truly buggy board.
fea5f1e1
LT		 1590 *
1591 * FIXME: really need to revamp this for modern platforms only.
1da177e4 1592 */
fea5f1e1 1593static inline void check_timer(void)
1da177e4 1594{
dfbffdd8 1595 struct irq_cfg *cfg = irq_cfg + 0;
1008fddc 1596 int apic1, pin1, apic2, pin2;
1da177e4
LT		 1597
1598 /*
1599 * get/set the timer IRQ vector:
1600 */
1601 disable_8259A_irq(0);
dfbffdd8 1602 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 1603
1604 /*
1605 * Subtle, code in do_timer_interrupt() expects an AEOI
1606 * mode for the 8259A whenever interrupts are routed
1607 * through I/O APICs. Also IRQ0 has to be enabled in
1608 * the 8259A which implies the virtual wire has to be
1609 * disabled in the local APIC.
1610 */
11a8e778 1611 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1612 init_8259A(1);
fea5f1e1
LT		 1613 if (timer_over_8254 > 0)
1614 enable_8259A_irq(0);
1da177e4 1615
1008fddc
EB		 1616 pin1 = find_isa_irq_pin(0, mp_INT);
1617 apic1 = find_isa_irq_apic(0, mp_INT);
1618 pin2 = ioapic_i8259.pin;
1619 apic2 = ioapic_i8259.apic;
1da177e4 1620
fea5f1e1 1621 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
dfbffdd8 1622 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 1623
fea5f1e1
LT		 1624 if (pin1 != -1) {
1625 /*
1626 * Ok, does IRQ0 through the IOAPIC work?
1627 */
1628 unmask_IO_APIC_irq(0);
1629 if (!no_timer_check && timer_irq_works()) {
1630 nmi_watchdog_default();
1631 if (nmi_watchdog == NMI_IO_APIC) {
1632 disable_8259A_irq(0);
1633 setup_nmi();
1634 enable_8259A_irq(0);
1635 }
1636 if (disable_timer_pin_1 > 0)
1637 clear_IO_APIC_pin(0, pin1);
1638 return;
1639 }
1640 clear_IO_APIC_pin(apic1, pin1);
1641 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1642 "connected to IO-APIC\n");
1643 }
1da177e4 1644
fea5f1e1
LT		 1645 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1646 "through the 8259A ... ");
1da177e4 1647 if (pin2 != -1) {
fea5f1e1
LT		 1648 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1649 apic2, pin2);
1650 /*
1651 * legacy devices should be connected to IO APIC #0
1652 */
dfbffdd8 1653 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
fea5f1e1
LT		 1654 if (timer_irq_works()) {
1655 apic_printk(APIC_VERBOSE," works.\n");
1656 nmi_watchdog_default();
1657 if (nmi_watchdog == NMI_IO_APIC) {
1658 setup_nmi();
1659 }
1da177e4 1660 return;
fea5f1e1
LT		 1661 }
1662 /*
1663 * Cleanup, just in case ...
1664 */
1665 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1666 }
fea5f1e1 1667 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1668
1f992153 1669 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1670 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1671 nmi_watchdog = 0;
1672 }
1673
1674 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1675
1676 disable_8259A_irq(0);
d1bef4ed 1677 irq_desc[0].chip = &lapic_irq_type;
dfbffdd8 1678 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 1679 enable_8259A_irq(0);
1680
1681 if (timer_irq_works()) {
5b922cd4 1682 apic_printk(APIC_VERBOSE," works.\n");
1da177e4
LT		 1683 return;
1684 }
dfbffdd8 1685 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1da177e4
LT		 1686 apic_printk(APIC_VERBOSE," failed.\n");
1687
1688 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1689
1690 init_8259A(0);
1691 make_8259A_irq(0);
11a8e778 1692 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1693
1694 unlock_ExtINT_logic();
1695
1696 if (timer_irq_works()) {
1697 apic_printk(APIC_VERBOSE," works.\n");
1698 return;
1699 }
1700 apic_printk(APIC_VERBOSE," failed :(.\n");
1701 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1702}
1703
14d98cad
AK		 1704static int __init notimercheck(char *s)
1705{
1706 no_timer_check = 1;
1707 return 1;
1708}
1709__setup("no_timer_check", notimercheck);
1710
1da177e4
LT		 1711/*
1712 *
1713 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1714 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1715 * Linux doesn't really care, as it's not actually used
1716 * for any interrupt handling anyway.
1717 */
1718#define PIC_IRQS (1<<2)
1719
1720void __init setup_IO_APIC(void)
1721{
1722 enable_IO_APIC();
1723
1724 if (acpi_ioapic)
1725 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1726 else
1727 io_apic_irqs = ~PIC_IRQS;
1728
1729 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1730
1da177e4
LT		 1731 sync_Arb_IDs();
1732 setup_IO_APIC_irqs();
1733 init_IO_APIC_traps();
1734 check_timer();
1735 if (!acpi_ioapic)
1736 print_IO_APIC();
1737}
1738
1739struct sysfs_ioapic_data {
1740 struct sys_device dev;
1741 struct IO_APIC_route_entry entry[0];
1742};
1743static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1744
0b9c33a7 1745static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1746{
1747 struct IO_APIC_route_entry *entry;
1748 struct sysfs_ioapic_data *data;
1da177e4
LT		 1749 int i;
1750
1751 data = container_of(dev, struct sysfs_ioapic_data, dev);
1752 entry = data->entry;
eea0e11c
AK		 1753 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1754 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1755
1756 return 0;
1757}
1758
1759static int ioapic_resume(struct sys_device *dev)
1760{
1761 struct IO_APIC_route_entry *entry;
1762 struct sysfs_ioapic_data *data;
1763 unsigned long flags;
1764 union IO_APIC_reg_00 reg_00;
1765 int i;
1766
1767 data = container_of(dev, struct sysfs_ioapic_data, dev);
1768 entry = data->entry;
1769
1770 spin_lock_irqsave(&ioapic_lock, flags);
1771 reg_00.raw = io_apic_read(dev->id, 0);
1772 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1773 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1774 io_apic_write(dev->id, 0, reg_00.raw);
1775 }
1da177e4 1776 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1777 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1778 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1779
1780 return 0;
1781}
1782
1783static struct sysdev_class ioapic_sysdev_class = {
1784 set_kset_name("ioapic"),
1785 .suspend = ioapic_suspend,
1786 .resume = ioapic_resume,
1787};
1788
1789static int __init ioapic_init_sysfs(void)
1790{
1791 struct sys_device * dev;
1792 int i, size, error = 0;
1793
1794 error = sysdev_class_register(&ioapic_sysdev_class);
1795 if (error)
1796 return error;
1797
1798 for (i = 0; i < nr_ioapics; i++ ) {
1799 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1800 * sizeof(struct IO_APIC_route_entry);
1801 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1802 if (!mp_ioapic_data[i]) {
1803 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1804 continue;
1805 }
1806 memset(mp_ioapic_data[i], 0, size);
1807 dev = &mp_ioapic_data[i]->dev;
1808 dev->id = i;
1809 dev->cls = &ioapic_sysdev_class;
1810 error = sysdev_register(dev);
1811 if (error) {
1812 kfree(mp_ioapic_data[i]);
1813 mp_ioapic_data[i] = NULL;
1814 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1815 continue;
1816 }
1817 }
1818
1819 return 0;
1820}
1821
1822device_initcall(ioapic_init_sysfs);
1823
c4fa0bbf 1824/*
04b9267b 1825 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1826 */
1827int create_irq(void)
1828{
04b9267b
EB		 1829 /* Allocate an unused irq */
1830 int irq;
1831 int new;
c4fa0bbf 1832 unsigned long flags;
c4fa0bbf 1833
04b9267b
EB		 1834 irq = -ENOSPC;
1835 spin_lock_irqsave(&vector_lock, flags);
1836 for (new = (NR_IRQS - 1); new >= 0; new--) {
1837 if (platform_legacy_irq(new))
1838 continue;
13a79503 1839 if (irq_cfg[new].vector != 0)
04b9267b 1840 continue;
dfbffdd8 1841 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 1842 irq = new;
1843 break;
1844 }
1845 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1846
04b9267b 1847 if (irq >= 0) {
c4fa0bbf
EB		 1848 dynamic_irq_init(irq);
1849 }
1850 return irq;
1851}
1852
1853void destroy_irq(unsigned int irq)
1854{
1855 unsigned long flags;
c4fa0bbf
EB		 1856
1857 dynamic_irq_cleanup(irq);
1858
1859 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1860 __clear_irq_vector(irq);
c4fa0bbf
EB		 1861 spin_unlock_irqrestore(&vector_lock, flags);
1862}
c4fa0bbf 1863
589e367f
EB		 1864/*
1865 * MSI mesage composition
1866 */
1867#ifdef CONFIG_PCI_MSI
3b7d1921 1868static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1869{
dfbffdd8
EB		 1870 struct irq_cfg *cfg = irq_cfg + irq;
1871 int err;
589e367f 1872 unsigned dest;
c7111c13 1873 cpumask_t tmp;
589e367f 1874
dfbffdd8
EB		 1875 tmp = TARGET_CPUS;
1876 err = assign_irq_vector(irq, tmp);
1877 if (!err) {
1878 cpus_and(tmp, cfg->domain, tmp);
589e367f
EB		 1879 dest = cpu_mask_to_apicid(tmp);
1880
1881 msg->address_hi = MSI_ADDR_BASE_HI;
1882 msg->address_lo =
1883 MSI_ADDR_BASE_LO |
1884 ((INT_DEST_MODE == 0) ?
1885 MSI_ADDR_DEST_MODE_PHYSICAL:
1886 MSI_ADDR_DEST_MODE_LOGICAL) |
1887 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1888 MSI_ADDR_REDIRECTION_CPU:
1889 MSI_ADDR_REDIRECTION_LOWPRI) |
1890 MSI_ADDR_DEST_ID(dest);
1891
1892 msg->data =
1893 MSI_DATA_TRIGGER_EDGE |
1894 MSI_DATA_LEVEL_ASSERT |
1895 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1896 MSI_DATA_DELIVERY_FIXED:
1897 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 1898 MSI_DATA_VECTOR(cfg->vector);
589e367f 1899 }
dfbffdd8 1900 return err;
589e367f
EB		 1901}
1902
3b7d1921
EB		 1903#ifdef CONFIG_SMP
1904static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1905{
dfbffdd8 1906 struct irq_cfg *cfg = irq_cfg + irq;
3b7d1921
EB		 1907 struct msi_msg msg;
1908 unsigned int dest;
1909 cpumask_t tmp;
3b7d1921
EB		 1910
1911 cpus_and(tmp, mask, cpu_online_map);
1912 if (cpus_empty(tmp))
5ff5115e 1913 return;
589e367f 1914
dfbffdd8 1915 if (assign_irq_vector(irq, mask))
3b7d1921 1916 return;
550f2299 1917
dfbffdd8 1918 cpus_and(tmp, cfg->domain, mask);
3b7d1921 1919 dest = cpu_mask_to_apicid(tmp);
589e367f 1920
3b7d1921
EB		 1921 read_msi_msg(irq, &msg);
1922
1923 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 1924 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 1925 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1926 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1927
1928 write_msi_msg(irq, &msg);
9f0a5ba5 1929 irq_desc[irq].affinity = mask;
589e367f 1930}
3b7d1921 1931#endif /* CONFIG_SMP */
589e367f 1932
3b7d1921
EB		 1933/*
1934 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1935 * which implement the MSI or MSI-X Capability Structure.
1936 */
1937static struct irq_chip msi_chip = {
1938 .name = "PCI-MSI",
1939 .unmask = unmask_msi_irq,
1940 .mask = mask_msi_irq,
1941 .ack = ack_apic_edge,
1942#ifdef CONFIG_SMP
1943 .set_affinity = set_msi_irq_affinity,
1944#endif
1945 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 1946};
1947
f7feaca7 1948int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 1949{
1950 struct msi_msg msg;
f7feaca7
EB		 1951 int irq, ret;
1952 irq = create_irq();
1953 if (irq < 0)
1954 return irq;
1955
3b7d1921 1956 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 1957 if (ret < 0) {
1958 destroy_irq(irq);
3b7d1921 1959 return ret;
f7feaca7 1960 }
3b7d1921 1961
7fe3730d 1962 set_irq_msi(irq, desc);
3b7d1921
EB		 1963 write_msi_msg(irq, &msg);
1964
a460e745 1965 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921 1966
7fe3730d 1967 return 0;
3b7d1921
EB		 1968}
1969
1970void arch_teardown_msi_irq(unsigned int irq)
1971{
f7feaca7 1972 destroy_irq(irq);
3b7d1921
EB		 1973}
1974
1975#endif /* CONFIG_PCI_MSI */
589e367f 1976
8b955b0d
EB		 1977/*
1978 * Hypertransport interrupt support
1979 */
1980#ifdef CONFIG_HT_IRQ
1981
1982#ifdef CONFIG_SMP
1983
1984static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1985{
ec68307c
EB		 1986 struct ht_irq_msg msg;
1987 fetch_ht_irq_msg(irq, &msg);
8b955b0d 1988
ec68307c
EB		 1989 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1990 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 1991
ec68307c
EB		 1992 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1993 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 1994
ec68307c 1995 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 1996}
1997
1998static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1999{
dfbffdd8 2000 struct irq_cfg *cfg = irq_cfg + irq;
8b955b0d
EB		 2001 unsigned int dest;
2002 cpumask_t tmp;
8b955b0d
EB		 2003
2004 cpus_and(tmp, mask, cpu_online_map);
2005 if (cpus_empty(tmp))
5ff5115e 2006 return;
8b955b0d 2007
dfbffdd8 2008 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 2009 return;
2010
dfbffdd8 2011 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 2012 dest = cpu_mask_to_apicid(tmp);
2013
dfbffdd8 2014 target_ht_irq(irq, dest, cfg->vector);
9f0a5ba5 2015 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2016}
2017#endif
2018
c37e108d 2019static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2020 .name = "PCI-HT",
2021 .mask = mask_ht_irq,
2022 .unmask = unmask_ht_irq,
2023 .ack = ack_apic_edge,
2024#ifdef CONFIG_SMP
2025 .set_affinity = set_ht_irq_affinity,
2026#endif
2027 .retrigger = ioapic_retrigger_irq,
2028};
2029
2030int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2031{
dfbffdd8
EB		 2032 struct irq_cfg *cfg = irq_cfg + irq;
2033 int err;
c7111c13 2034 cpumask_t tmp;
8b955b0d 2035
dfbffdd8
EB		 2036 tmp = TARGET_CPUS;
2037 err = assign_irq_vector(irq, tmp);
2038 if (!err) {
ec68307c 2039 struct ht_irq_msg msg;
8b955b0d 2040 unsigned dest;
8b955b0d 2041
dfbffdd8 2042 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2043 dest = cpu_mask_to_apicid(tmp);
2044
ec68307c 2045 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2046
ec68307c
EB		 2047 msg.address_lo =
2048 HT_IRQ_LOW_BASE |
8b955b0d 2049 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 2050 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2051 ((INT_DEST_MODE == 0) ?
2052 HT_IRQ_LOW_DM_PHYSICAL :
2053 HT_IRQ_LOW_DM_LOGICAL) |
2054 HT_IRQ_LOW_RQEOI_EDGE |
2055 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2056 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2057 HT_IRQ_LOW_MT_ARBITRATED) |
2058 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2059
ec68307c 2060 write_ht_irq_msg(irq, &msg);
8b955b0d 2061
a460e745
IM		 2062 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2063 handle_edge_irq, "edge");
8b955b0d 2064 }
dfbffdd8 2065 return err;
8b955b0d
EB		 2066}
2067#endif /* CONFIG_HT_IRQ */
2068
1da177e4
LT		 2069/* --------------------------------------------------------------------------
2070 ACPI-based IOAPIC Configuration
2071 -------------------------------------------------------------------------- */
2072
888ba6c6 2073#ifdef CONFIG_ACPI
1da177e4
LT		 2074
2075#define IO_APIC_MAX_ID 0xFE
2076
1da177e4
LT		 2077int __init io_apic_get_redir_entries (int ioapic)
2078{
2079 union IO_APIC_reg_01 reg_01;
2080 unsigned long flags;
2081
2082 spin_lock_irqsave(&ioapic_lock, flags);
2083 reg_01.raw = io_apic_read(ioapic, 1);
2084 spin_unlock_irqrestore(&ioapic_lock, flags);
2085
2086 return reg_01.bits.entries;
2087}
2088
2089
50eca3eb 2090int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 2091{
1da177e4
LT		 2092 if (!IO_APIC_IRQ(irq)) {
2093 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2094 ioapic);
2095 return -EINVAL;
2096 }
2097
550f2299
EB		 2098 /*
2099 * IRQs < 16 are already in the irq_2_pin[] map
2100 */
2101 if (irq >= 16)
2102 add_pin_to_irq(irq, ioapic, pin);
2103
a8c8a367 2104 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 2105
2106 return 0;
2107}
2108
888ba6c6 2109#endif /* CONFIG_ACPI */
1da177e4
LT		 2110
2111
2112/*
2113 * This function currently is only a helper for the i386 smp boot process where
2114 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2115 * so mask in all cases should simply be TARGET_CPUS
2116 */
54d5d424 2117#ifdef CONFIG_SMP
1da177e4
LT		 2118void __init setup_ioapic_dest(void)
2119{
2120 int pin, ioapic, irq, irq_entry;
2121
2122 if (skip_ioapic_setup == 1)
2123 return;
2124
2125 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2126 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2127 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2128 if (irq_entry == -1)
2129 continue;
2130 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 2131
2132 /* setup_IO_APIC_irqs could fail to get vector for some device
2133 * when you have too many devices, because at that time only boot
2134 * cpu is online.
2135 */
13a79503 2136 if (!irq_cfg[irq].vector)
a8c8a367
EB		 2137 setup_IO_APIC_irq(ioapic, pin, irq,
2138 irq_trigger(irq_entry),
2139 irq_polarity(irq_entry));
ad892f5e
YL		 2140 else
2141 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 2142 }
2143
2144 }
2145}
54d5d424 2146#endif
Linux 6.x block layer and io_uring tree(s)