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1da177e4 | 1 | #include <linux/linkage.h> |
1da177e4 LT |
2 | #include <linux/errno.h> |
3 | #include <linux/signal.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/ioport.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/timex.h> | |
8 | #include <linux/slab.h> | |
9 | #include <linux/random.h> | |
10 | #include <linux/smp_lock.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/sysdev.h> | |
14 | #include <linux/bitops.h> | |
15 | ||
16 | #include <asm/acpi.h> | |
17 | #include <asm/atomic.h> | |
18 | #include <asm/system.h> | |
19 | #include <asm/io.h> | |
1da177e4 LT |
20 | #include <asm/hw_irq.h> |
21 | #include <asm/pgtable.h> | |
22 | #include <asm/delay.h> | |
23 | #include <asm/desc.h> | |
24 | #include <asm/apic.h> | |
25 | ||
1da177e4 LT |
26 | /* |
27 | * Common place to define all x86 IRQ vectors | |
28 | * | |
29 | * This builds up the IRQ handler stubs using some ugly macros in irq.h | |
30 | * | |
31 | * These macros create the low-level assembly IRQ routines that save | |
32 | * register context and call do_IRQ(). do_IRQ() then does all the | |
33 | * operations that are needed to keep the AT (or SMP IOAPIC) | |
34 | * interrupt-controller happy. | |
35 | */ | |
36 | ||
37 | #define BI(x,y) \ | |
38 | BUILD_IRQ(x##y) | |
39 | ||
40 | #define BUILD_16_IRQS(x) \ | |
41 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ | |
42 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ | |
43 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | |
44 | BI(x,c) BI(x,d) BI(x,e) BI(x,f) | |
45 | ||
1da177e4 LT |
46 | /* |
47 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | |
48 | * (these are usually mapped to vectors 0x20-0x2f) | |
49 | */ | |
1da177e4 | 50 | |
1da177e4 LT |
51 | /* |
52 | * The IO-APIC gives us many more interrupt sources. Most of these | |
53 | * are unused but an SMP system is supposed to have enough memory ... | |
54 | * sometimes (mostly wrt. hw bugs) we get corrupted vectors all | |
55 | * across the spectrum, so we really want to be prepared to get all | |
56 | * of these. Plus, more powerful systems might have more than 64 | |
57 | * IO-APIC registers. | |
58 | * | |
59 | * (these are usually mapped into the 0x30-0xff vector range) | |
60 | */ | |
e500f574 | 61 | BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) |
1da177e4 LT |
62 | BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) |
63 | BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) | |
e500f574 | 64 | BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf) |
1da177e4 | 65 | |
1da177e4 | 66 | #undef BUILD_16_IRQS |
1da177e4 LT |
67 | #undef BI |
68 | ||
69 | ||
70 | #define IRQ(x,y) \ | |
71 | IRQ##x##y##_interrupt | |
72 | ||
73 | #define IRQLIST_16(x) \ | |
74 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ | |
75 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ | |
76 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | |
77 | IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) | |
78 | ||
1da177e4 | 79 | void (*interrupt[NR_IRQS])(void) = { |
e500f574 | 80 | IRQLIST_16(0x2), IRQLIST_16(0x3), |
1da177e4 LT |
81 | IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), |
82 | IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), | |
e500f574 | 83 | IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf) |
1da177e4 LT |
84 | }; |
85 | ||
86 | #undef IRQ | |
87 | #undef IRQLIST_16 | |
1da177e4 LT |
88 | |
89 | /* | |
90 | * This is the 'legacy' 8259A Programmable Interrupt Controller, | |
91 | * present in the majority of PC/AT boxes. | |
92 | * plus some generic x86 specific things if generic specifics makes | |
93 | * any sense at all. | |
94 | * this file should become arch/i386/kernel/irq.c when the old irq.c | |
95 | * moves to arch independent land | |
96 | */ | |
97 | ||
35d534a3 | 98 | static int i8259A_auto_eoi; |
f29bd1ba | 99 | DEFINE_SPINLOCK(i8259A_lock); |
1da177e4 LT |
100 | static void mask_and_ack_8259A(unsigned int); |
101 | ||
f29bd1ba IM |
102 | static struct irq_chip i8259A_chip = { |
103 | .name = "XT-PIC", | |
104 | .mask = disable_8259A_irq, | |
105 | .unmask = enable_8259A_irq, | |
106 | .mask_ack = mask_and_ack_8259A, | |
1da177e4 LT |
107 | }; |
108 | ||
109 | /* | |
110 | * 8259A PIC functions to handle ISA devices: | |
111 | */ | |
112 | ||
113 | /* | |
114 | * This contains the irq mask for both 8259A irq controllers, | |
115 | */ | |
116 | static unsigned int cached_irq_mask = 0xffff; | |
117 | ||
118 | #define __byte(x,y) (((unsigned char *)&(y))[x]) | |
119 | #define cached_21 (__byte(0,cached_irq_mask)) | |
120 | #define cached_A1 (__byte(1,cached_irq_mask)) | |
121 | ||
122 | /* | |
123 | * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) | |
124 | * boards the timer interrupt is not really connected to any IO-APIC pin, | |
125 | * it's fed to the master 8259A's IR0 line only. | |
126 | * | |
127 | * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. | |
128 | * this 'mixed mode' IRQ handling costs nothing because it's only used | |
129 | * at IRQ setup time. | |
130 | */ | |
131 | unsigned long io_apic_irqs; | |
132 | ||
133 | void disable_8259A_irq(unsigned int irq) | |
134 | { | |
135 | unsigned int mask = 1 << irq; | |
136 | unsigned long flags; | |
137 | ||
138 | spin_lock_irqsave(&i8259A_lock, flags); | |
139 | cached_irq_mask |= mask; | |
140 | if (irq & 8) | |
141 | outb(cached_A1,0xA1); | |
142 | else | |
143 | outb(cached_21,0x21); | |
144 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
145 | } | |
146 | ||
147 | void enable_8259A_irq(unsigned int irq) | |
148 | { | |
149 | unsigned int mask = ~(1 << irq); | |
150 | unsigned long flags; | |
151 | ||
152 | spin_lock_irqsave(&i8259A_lock, flags); | |
153 | cached_irq_mask &= mask; | |
154 | if (irq & 8) | |
155 | outb(cached_A1,0xA1); | |
156 | else | |
157 | outb(cached_21,0x21); | |
158 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
159 | } | |
160 | ||
161 | int i8259A_irq_pending(unsigned int irq) | |
162 | { | |
163 | unsigned int mask = 1<<irq; | |
164 | unsigned long flags; | |
165 | int ret; | |
166 | ||
167 | spin_lock_irqsave(&i8259A_lock, flags); | |
168 | if (irq < 8) | |
169 | ret = inb(0x20) & mask; | |
170 | else | |
171 | ret = inb(0xA0) & (mask >> 8); | |
172 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
177 | void make_8259A_irq(unsigned int irq) | |
178 | { | |
179 | disable_irq_nosync(irq); | |
180 | io_apic_irqs &= ~(1<<irq); | |
f29bd1ba | 181 | set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); |
1da177e4 LT |
182 | enable_irq(irq); |
183 | } | |
184 | ||
185 | /* | |
186 | * This function assumes to be called rarely. Switching between | |
187 | * 8259A registers is slow. | |
188 | * This has to be protected by the irq controller spinlock | |
189 | * before being called. | |
190 | */ | |
191 | static inline int i8259A_irq_real(unsigned int irq) | |
192 | { | |
193 | int value; | |
194 | int irqmask = 1<<irq; | |
195 | ||
196 | if (irq < 8) { | |
197 | outb(0x0B,0x20); /* ISR register */ | |
198 | value = inb(0x20) & irqmask; | |
199 | outb(0x0A,0x20); /* back to the IRR register */ | |
200 | return value; | |
201 | } | |
202 | outb(0x0B,0xA0); /* ISR register */ | |
203 | value = inb(0xA0) & (irqmask >> 8); | |
204 | outb(0x0A,0xA0); /* back to the IRR register */ | |
205 | return value; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Careful! The 8259A is a fragile beast, it pretty | |
210 | * much _has_ to be done exactly like this (mask it | |
211 | * first, _then_ send the EOI, and the order of EOI | |
212 | * to the two 8259s is important! | |
213 | */ | |
214 | static void mask_and_ack_8259A(unsigned int irq) | |
215 | { | |
216 | unsigned int irqmask = 1 << irq; | |
217 | unsigned long flags; | |
218 | ||
219 | spin_lock_irqsave(&i8259A_lock, flags); | |
220 | /* | |
221 | * Lightweight spurious IRQ detection. We do not want | |
222 | * to overdo spurious IRQ handling - it's usually a sign | |
223 | * of hardware problems, so we only do the checks we can | |
d6e05edc | 224 | * do without slowing down good hardware unnecessarily. |
1da177e4 LT |
225 | * |
226 | * Note that IRQ7 and IRQ15 (the two spurious IRQs | |
227 | * usually resulting from the 8259A-1|2 PICs) occur | |
228 | * even if the IRQ is masked in the 8259A. Thus we | |
229 | * can check spurious 8259A IRQs without doing the | |
230 | * quite slow i8259A_irq_real() call for every IRQ. | |
231 | * This does not cover 100% of spurious interrupts, | |
232 | * but should be enough to warn the user that there | |
233 | * is something bad going on ... | |
234 | */ | |
235 | if (cached_irq_mask & irqmask) | |
236 | goto spurious_8259A_irq; | |
237 | cached_irq_mask |= irqmask; | |
238 | ||
239 | handle_real_irq: | |
240 | if (irq & 8) { | |
241 | inb(0xA1); /* DUMMY - (do we need this?) */ | |
242 | outb(cached_A1,0xA1); | |
243 | outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ | |
244 | outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ | |
245 | } else { | |
246 | inb(0x21); /* DUMMY - (do we need this?) */ | |
247 | outb(cached_21,0x21); | |
248 | outb(0x60+irq,0x20); /* 'Specific EOI' to master */ | |
249 | } | |
250 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
251 | return; | |
252 | ||
253 | spurious_8259A_irq: | |
254 | /* | |
255 | * this is the slow path - should happen rarely. | |
256 | */ | |
257 | if (i8259A_irq_real(irq)) | |
258 | /* | |
259 | * oops, the IRQ _is_ in service according to the | |
260 | * 8259A - not spurious, go handle it. | |
261 | */ | |
262 | goto handle_real_irq; | |
263 | ||
264 | { | |
265 | static int spurious_irq_mask; | |
266 | /* | |
267 | * At this point we can be sure the IRQ is spurious, | |
268 | * lets ACK and report it. [once per IRQ] | |
269 | */ | |
270 | if (!(spurious_irq_mask & irqmask)) { | |
271 | printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq); | |
272 | spurious_irq_mask |= irqmask; | |
273 | } | |
274 | atomic_inc(&irq_err_count); | |
275 | /* | |
276 | * Theoretically we do not have to handle this IRQ, | |
277 | * but in Linux this does not cause problems and is | |
278 | * simpler for us. | |
279 | */ | |
280 | goto handle_real_irq; | |
281 | } | |
282 | } | |
283 | ||
284 | void init_8259A(int auto_eoi) | |
285 | { | |
286 | unsigned long flags; | |
287 | ||
35d534a3 MG |
288 | i8259A_auto_eoi = auto_eoi; |
289 | ||
1da177e4 LT |
290 | spin_lock_irqsave(&i8259A_lock, flags); |
291 | ||
292 | outb(0xff, 0x21); /* mask all of 8259A-1 */ | |
293 | outb(0xff, 0xA1); /* mask all of 8259A-2 */ | |
294 | ||
295 | /* | |
296 | * outb_p - this has to work on a wide range of PC hardware. | |
297 | */ | |
298 | outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ | |
299 | outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ | |
300 | outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ | |
301 | if (auto_eoi) | |
302 | outb_p(0x03, 0x21); /* master does Auto EOI */ | |
303 | else | |
304 | outb_p(0x01, 0x21); /* master expects normal EOI */ | |
305 | ||
306 | outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ | |
307 | outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ | |
308 | outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ | |
309 | outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode | |
310 | is to be investigated) */ | |
311 | ||
312 | if (auto_eoi) | |
313 | /* | |
314 | * in AEOI mode we just have to mask the interrupt | |
315 | * when acking. | |
316 | */ | |
f29bd1ba | 317 | i8259A_chip.mask_ack = disable_8259A_irq; |
1da177e4 | 318 | else |
f29bd1ba | 319 | i8259A_chip.mask_ack = mask_and_ack_8259A; |
1da177e4 LT |
320 | |
321 | udelay(100); /* wait for 8259A to initialize */ | |
322 | ||
323 | outb(cached_21, 0x21); /* restore master IRQ mask */ | |
324 | outb(cached_A1, 0xA1); /* restore slave IRQ mask */ | |
325 | ||
326 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
327 | } | |
328 | ||
329 | static char irq_trigger[2]; | |
330 | /** | |
331 | * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ | |
332 | */ | |
333 | static void restore_ELCR(char *trigger) | |
334 | { | |
335 | outb(trigger[0], 0x4d0); | |
336 | outb(trigger[1], 0x4d1); | |
337 | } | |
338 | ||
339 | static void save_ELCR(char *trigger) | |
340 | { | |
341 | /* IRQ 0,1,2,8,13 are marked as reserved */ | |
342 | trigger[0] = inb(0x4d0) & 0xF8; | |
343 | trigger[1] = inb(0x4d1) & 0xDE; | |
344 | } | |
345 | ||
346 | static int i8259A_resume(struct sys_device *dev) | |
347 | { | |
35d534a3 | 348 | init_8259A(i8259A_auto_eoi); |
1da177e4 LT |
349 | restore_ELCR(irq_trigger); |
350 | return 0; | |
351 | } | |
352 | ||
0b9c33a7 | 353 | static int i8259A_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
354 | { |
355 | save_ELCR(irq_trigger); | |
356 | return 0; | |
357 | } | |
358 | ||
719e7110 EB |
359 | static int i8259A_shutdown(struct sys_device *dev) |
360 | { | |
361 | /* Put the i8259A into a quiescent state that | |
362 | * the kernel initialization code can get it | |
363 | * out of. | |
364 | */ | |
365 | outb(0xff, 0x21); /* mask all of 8259A-1 */ | |
366 | outb(0xff, 0xA1); /* mask all of 8259A-1 */ | |
367 | return 0; | |
368 | } | |
369 | ||
1da177e4 LT |
370 | static struct sysdev_class i8259_sysdev_class = { |
371 | set_kset_name("i8259"), | |
372 | .suspend = i8259A_suspend, | |
373 | .resume = i8259A_resume, | |
719e7110 | 374 | .shutdown = i8259A_shutdown, |
1da177e4 LT |
375 | }; |
376 | ||
377 | static struct sys_device device_i8259A = { | |
378 | .id = 0, | |
379 | .cls = &i8259_sysdev_class, | |
380 | }; | |
381 | ||
382 | static int __init i8259A_init_sysfs(void) | |
383 | { | |
384 | int error = sysdev_class_register(&i8259_sysdev_class); | |
385 | if (!error) | |
386 | error = sysdev_register(&device_i8259A); | |
387 | return error; | |
388 | } | |
389 | ||
390 | device_initcall(i8259A_init_sysfs); | |
391 | ||
392 | /* | |
393 | * IRQ2 is cascade interrupt to second interrupt controller | |
394 | */ | |
395 | ||
396 | static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL}; | |
e500f574 EB |
397 | int vector_irq[NR_VECTORS] __read_mostly = { |
398 | [0 ... FIRST_EXTERNAL_VECTOR - 1] = -1, | |
399 | [FIRST_EXTERNAL_VECTOR + 0] = 0, | |
400 | [FIRST_EXTERNAL_VECTOR + 1] = 1, | |
401 | [FIRST_EXTERNAL_VECTOR + 2] = 2, | |
402 | [FIRST_EXTERNAL_VECTOR + 3] = 3, | |
403 | [FIRST_EXTERNAL_VECTOR + 4] = 4, | |
404 | [FIRST_EXTERNAL_VECTOR + 5] = 5, | |
405 | [FIRST_EXTERNAL_VECTOR + 6] = 6, | |
406 | [FIRST_EXTERNAL_VECTOR + 7] = 7, | |
407 | [FIRST_EXTERNAL_VECTOR + 8] = 8, | |
408 | [FIRST_EXTERNAL_VECTOR + 9] = 9, | |
409 | [FIRST_EXTERNAL_VECTOR + 10] = 10, | |
410 | [FIRST_EXTERNAL_VECTOR + 11] = 11, | |
411 | [FIRST_EXTERNAL_VECTOR + 12] = 12, | |
412 | [FIRST_EXTERNAL_VECTOR + 13] = 13, | |
413 | [FIRST_EXTERNAL_VECTOR + 14] = 14, | |
414 | [FIRST_EXTERNAL_VECTOR + 15] = 15, | |
415 | [FIRST_EXTERNAL_VECTOR + 16 ... NR_VECTORS - 1] = -1 | |
416 | }; | |
1da177e4 LT |
417 | |
418 | void __init init_ISA_irqs (void) | |
419 | { | |
420 | int i; | |
421 | ||
1da177e4 | 422 | init_bsp_APIC(); |
1da177e4 LT |
423 | init_8259A(0); |
424 | ||
425 | for (i = 0; i < NR_IRQS; i++) { | |
426 | irq_desc[i].status = IRQ_DISABLED; | |
427 | irq_desc[i].action = NULL; | |
428 | irq_desc[i].depth = 1; | |
429 | ||
430 | if (i < 16) { | |
431 | /* | |
432 | * 16 old-style INTA-cycle interrupts: | |
433 | */ | |
f29bd1ba IM |
434 | set_irq_chip_and_handler(i, &i8259A_chip, |
435 | handle_level_irq); | |
1da177e4 LT |
436 | } else { |
437 | /* | |
438 | * 'high' PCI IRQs filled in on demand | |
439 | */ | |
f29bd1ba | 440 | irq_desc[i].chip = &no_irq_chip; |
1da177e4 LT |
441 | } |
442 | } | |
443 | } | |
444 | ||
445 | void apic_timer_interrupt(void); | |
446 | void spurious_interrupt(void); | |
447 | void error_interrupt(void); | |
448 | void reschedule_interrupt(void); | |
449 | void call_function_interrupt(void); | |
e5bc8b6b AK |
450 | void invalidate_interrupt0(void); |
451 | void invalidate_interrupt1(void); | |
452 | void invalidate_interrupt2(void); | |
453 | void invalidate_interrupt3(void); | |
454 | void invalidate_interrupt4(void); | |
455 | void invalidate_interrupt5(void); | |
456 | void invalidate_interrupt6(void); | |
457 | void invalidate_interrupt7(void); | |
1da177e4 | 458 | void thermal_interrupt(void); |
89b831ef | 459 | void threshold_interrupt(void); |
1da177e4 LT |
460 | void i8254_timer_resume(void); |
461 | ||
a8db2db1 | 462 | static void setup_timer_hardware(void) |
1da177e4 LT |
463 | { |
464 | outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ | |
465 | udelay(10); | |
466 | outb_p(LATCH & 0xff , 0x40); /* LSB */ | |
467 | udelay(10); | |
468 | outb(LATCH >> 8 , 0x40); /* MSB */ | |
469 | } | |
470 | ||
471 | static int timer_resume(struct sys_device *dev) | |
472 | { | |
a8db2db1 | 473 | setup_timer_hardware(); |
1da177e4 LT |
474 | return 0; |
475 | } | |
476 | ||
477 | void i8254_timer_resume(void) | |
478 | { | |
a8db2db1 | 479 | setup_timer_hardware(); |
1da177e4 LT |
480 | } |
481 | ||
482 | static struct sysdev_class timer_sysclass = { | |
d6c7ac08 | 483 | set_kset_name("timer_pit"), |
1da177e4 LT |
484 | .resume = timer_resume, |
485 | }; | |
486 | ||
487 | static struct sys_device device_timer = { | |
488 | .id = 0, | |
489 | .cls = &timer_sysclass, | |
490 | }; | |
491 | ||
492 | static int __init init_timer_sysfs(void) | |
493 | { | |
494 | int error = sysdev_class_register(&timer_sysclass); | |
495 | if (!error) | |
496 | error = sysdev_register(&device_timer); | |
497 | return error; | |
498 | } | |
499 | ||
500 | device_initcall(init_timer_sysfs); | |
501 | ||
502 | void __init init_IRQ(void) | |
503 | { | |
504 | int i; | |
505 | ||
506 | init_ISA_irqs(); | |
507 | /* | |
508 | * Cover the whole vector space, no vector can escape | |
509 | * us. (some of these will be overridden and become | |
510 | * 'special' SMP interrupts) | |
511 | */ | |
512 | for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) { | |
513 | int vector = FIRST_EXTERNAL_VECTOR + i; | |
915f34e2 | 514 | if (vector != IA32_SYSCALL_VECTOR) |
1da177e4 LT |
515 | set_intr_gate(vector, interrupt[i]); |
516 | } | |
1da177e4 LT |
517 | |
518 | #ifdef CONFIG_SMP | |
519 | /* | |
520 | * IRQ0 must be given a fixed assignment and initialized, | |
521 | * because it's used before the IO-APIC is set up. | |
522 | */ | |
e500f574 | 523 | vector_irq[FIRST_DEVICE_VECTOR] = 0; |
1da177e4 LT |
524 | |
525 | /* | |
526 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
527 | * IPI, driven by wakeup. | |
528 | */ | |
529 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
530 | ||
e5bc8b6b AK |
531 | /* IPIs for invalidation */ |
532 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); | |
533 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); | |
534 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); | |
535 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); | |
536 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); | |
537 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); | |
538 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); | |
539 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); | |
1da177e4 LT |
540 | |
541 | /* IPI for generic function call */ | |
542 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
543 | #endif | |
544 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
89b831ef | 545 | set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); |
1da177e4 | 546 | |
1da177e4 LT |
547 | /* self generated IPI for local APIC timer */ |
548 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
549 | ||
550 | /* IPI vectors for APIC spurious and error interrupts */ | |
551 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
552 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 LT |
553 | |
554 | /* | |
555 | * Set the clock to HZ Hz, we already have a valid | |
556 | * vector now: | |
557 | */ | |
a8db2db1 | 558 | setup_timer_hardware(); |
1da177e4 LT |
559 | |
560 | if (!acpi_ioapic) | |
561 | setup_irq(2, &irq2); | |
562 | } |