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1da177e4 LT |
1 | /* |
2 | * Copyright 2004 James Cleverdon, IBM. | |
3 | * Subject to the GNU Public License, v.2 | |
4 | * | |
5 | * Flat APIC subarch code. Maximum 8 CPUs, logical delivery. | |
6 | * | |
7 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
8 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
9 | * James Cleverdon. | |
10 | */ | |
11 | #include <linux/config.h> | |
12 | #include <linux/threads.h> | |
13 | #include <linux/cpumask.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ctype.h> | |
17 | #include <linux/init.h> | |
18 | #include <asm/smp.h> | |
19 | #include <asm/ipi.h> | |
20 | ||
21 | ||
22 | static cpumask_t flat_target_cpus(void) | |
23 | { | |
24 | return cpu_online_map; | |
25 | } | |
26 | ||
27 | /* | |
28 | * Set up the logical destination ID. | |
29 | * | |
30 | * Intel recommends to set DFR, LDR and TPR before enabling | |
31 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
32 | * document number 292116). So here it goes... | |
33 | */ | |
34 | static void flat_init_apic_ldr(void) | |
35 | { | |
36 | unsigned long val; | |
37 | unsigned long num, id; | |
38 | ||
39 | num = smp_processor_id(); | |
40 | id = 1UL << num; | |
41 | x86_cpu_to_log_apicid[num] = id; | |
42 | apic_write_around(APIC_DFR, APIC_DFR_FLAT); | |
43 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
44 | val |= SET_APIC_LOGICAL_ID(id); | |
45 | apic_write_around(APIC_LDR, val); | |
46 | } | |
47 | ||
48 | static void flat_send_IPI_allbutself(int vector) | |
49 | { | |
50 | /* | |
51 | * if there are no other CPUs in the system then | |
52 | * we get an APIC send error if we try to broadcast. | |
53 | * thus we have to avoid sending IPIs in this case. | |
54 | */ | |
55 | if (num_online_cpus() > 1) | |
56 | __send_IPI_shortcut(APIC_DEST_ALLBUT, vector, APIC_DEST_LOGICAL); | |
57 | } | |
58 | ||
59 | static void flat_send_IPI_all(int vector) | |
60 | { | |
61 | __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL); | |
62 | } | |
63 | ||
64 | static void flat_send_IPI_mask(cpumask_t cpumask, int vector) | |
65 | { | |
66 | unsigned long mask = cpus_addr(cpumask)[0]; | |
67 | unsigned long cfg; | |
68 | unsigned long flags; | |
69 | ||
70 | local_save_flags(flags); | |
71 | local_irq_disable(); | |
72 | ||
73 | /* | |
74 | * Wait for idle. | |
75 | */ | |
76 | apic_wait_icr_idle(); | |
77 | ||
78 | /* | |
79 | * prepare target chip field | |
80 | */ | |
81 | cfg = __prepare_ICR2(mask); | |
82 | apic_write_around(APIC_ICR2, cfg); | |
83 | ||
84 | /* | |
85 | * program the ICR | |
86 | */ | |
87 | cfg = __prepare_ICR(0, vector, APIC_DEST_LOGICAL); | |
88 | ||
89 | /* | |
90 | * Send the IPI. The write to APIC_ICR fires this off. | |
91 | */ | |
92 | apic_write_around(APIC_ICR, cfg); | |
93 | local_irq_restore(flags); | |
94 | } | |
95 | ||
96 | static int flat_apic_id_registered(void) | |
97 | { | |
98 | return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map); | |
99 | } | |
100 | ||
101 | static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask) | |
102 | { | |
103 | return cpus_addr(cpumask)[0] & APIC_ALL_CPUS; | |
104 | } | |
105 | ||
106 | static unsigned int phys_pkg_id(int index_msb) | |
107 | { | |
108 | u32 ebx; | |
109 | ||
110 | ebx = cpuid_ebx(1); | |
111 | return ((ebx >> 24) & 0xFF) >> index_msb; | |
112 | } | |
113 | ||
114 | struct genapic apic_flat = { | |
115 | .name = "flat", | |
116 | .int_delivery_mode = dest_LowestPrio, | |
117 | .int_dest_mode = (APIC_DEST_LOGICAL != 0), | |
118 | .int_delivery_dest = APIC_DEST_LOGICAL | APIC_DM_LOWEST, | |
119 | .target_cpus = flat_target_cpus, | |
120 | .apic_id_registered = flat_apic_id_registered, | |
121 | .init_apic_ldr = flat_init_apic_ldr, | |
122 | .send_IPI_all = flat_send_IPI_all, | |
123 | .send_IPI_allbutself = flat_send_IPI_allbutself, | |
124 | .send_IPI_mask = flat_send_IPI_mask, | |
125 | .cpu_mask_to_apicid = flat_cpu_mask_to_apicid, | |
126 | .phys_pkg_id = phys_pkg_id, | |
127 | }; |