Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/mc146818rtc.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sysdev.h> | |
d25bf7e5 | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
95833c83 | 37 | #include <asm/idle.h> |
73dea47f AK |
38 | #include <asm/proto.h> |
39 | #include <asm/timex.h> | |
1da177e4 LT |
40 | |
41 | int apic_verbosity; | |
73dea47f | 42 | int apic_runs_main_timer; |
0c3749c4 | 43 | int apic_calibrate_pmtmr __initdata; |
1da177e4 LT |
44 | |
45 | int disable_apic_timer __initdata; | |
46 | ||
d25bf7e5 VP |
47 | /* |
48 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
49 | * IPIs in place of local APIC timers | |
50 | */ | |
51 | static cpumask_t timer_interrupt_broadcast_ipi_mask; | |
52 | ||
1da177e4 LT |
53 | /* Using APIC to generate smp_local_timer_interrupt? */ |
54 | int using_apic_timer = 0; | |
55 | ||
1da177e4 LT |
56 | static void apic_pm_activate(void); |
57 | ||
58 | void enable_NMI_through_LVT0 (void * dummy) | |
59 | { | |
11a8e778 | 60 | unsigned int v; |
1da177e4 | 61 | |
1da177e4 | 62 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
11a8e778 | 63 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
64 | } |
65 | ||
66 | int get_maxlvt(void) | |
67 | { | |
11a8e778 | 68 | unsigned int v, maxlvt; |
1da177e4 LT |
69 | |
70 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
71 | maxlvt = GET_APIC_MAXLVT(v); |
72 | return maxlvt; | |
73 | } | |
74 | ||
3777a959 AK |
75 | /* |
76 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
77 | * each architecture has to answer this themselves. | |
78 | */ | |
79 | void ack_bad_irq(unsigned int irq) | |
80 | { | |
81 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
82 | /* | |
83 | * Currently unexpected vectors happen only on SMP and APIC. | |
84 | * We _must_ ack these because every local APIC has only N | |
85 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
86 | * holds up an irq slot - in excessive cases (when multiple | |
87 | * unexpected vectors occur) that might lock up the APIC | |
88 | * completely. | |
89 | * But don't ack when the APIC is disabled. -AK | |
90 | */ | |
91 | if (!disable_apic) | |
92 | ack_APIC_irq(); | |
93 | } | |
94 | ||
1da177e4 LT |
95 | void clear_local_APIC(void) |
96 | { | |
97 | int maxlvt; | |
98 | unsigned int v; | |
99 | ||
100 | maxlvt = get_maxlvt(); | |
101 | ||
102 | /* | |
103 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
104 | * if the vector is zero. Mask LVTERR first to prevent this. | |
105 | */ | |
106 | if (maxlvt >= 3) { | |
107 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 108 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
109 | } |
110 | /* | |
111 | * Careful: we have to set masks only first to deassert | |
112 | * any level-triggered sources. | |
113 | */ | |
114 | v = apic_read(APIC_LVTT); | |
11a8e778 | 115 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 116 | v = apic_read(APIC_LVT0); |
11a8e778 | 117 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 118 | v = apic_read(APIC_LVT1); |
11a8e778 | 119 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
120 | if (maxlvt >= 4) { |
121 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 122 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
123 | } |
124 | ||
125 | /* | |
126 | * Clean APIC state for other OSs: | |
127 | */ | |
11a8e778 AK |
128 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
129 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
130 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 131 | if (maxlvt >= 3) |
11a8e778 | 132 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 133 | if (maxlvt >= 4) |
11a8e778 | 134 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 135 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
5a40b7c2 AK |
136 | apic_write(APIC_ESR, 0); |
137 | apic_read(APIC_ESR); | |
1da177e4 LT |
138 | } |
139 | ||
140 | void __init connect_bsp_APIC(void) | |
141 | { | |
142 | if (pic_mode) { | |
143 | /* | |
144 | * Do not trust the local APIC being empty at bootup. | |
145 | */ | |
146 | clear_local_APIC(); | |
147 | /* | |
148 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
149 | * connect BSP's local APIC to INT and NMI lines. | |
150 | */ | |
151 | apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n"); | |
152 | outb(0x70, 0x22); | |
153 | outb(0x01, 0x23); | |
154 | } | |
155 | } | |
156 | ||
208fb931 | 157 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
158 | { |
159 | if (pic_mode) { | |
160 | /* | |
161 | * Put the board back into PIC mode (has an effect | |
162 | * only on certain older boards). Note that APIC | |
163 | * interrupts, including IPIs, won't work beyond | |
164 | * this point! The only exception are INIT IPIs. | |
165 | */ | |
166 | apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n"); | |
167 | outb(0x70, 0x22); | |
168 | outb(0x00, 0x23); | |
169 | } | |
208fb931 EB |
170 | else { |
171 | /* Go back to Virtual Wire compatibility mode */ | |
172 | unsigned long value; | |
173 | ||
174 | /* For the spurious interrupt use vector F, and enable it */ | |
175 | value = apic_read(APIC_SPIV); | |
176 | value &= ~APIC_VECTOR_MASK; | |
177 | value |= APIC_SPIV_APIC_ENABLED; | |
178 | value |= 0xf; | |
11a8e778 | 179 | apic_write(APIC_SPIV, value); |
208fb931 EB |
180 | |
181 | if (!virt_wire_setup) { | |
182 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
183 | value = apic_read(APIC_LVT0); | |
184 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
185 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
186 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
187 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
188 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
11a8e778 | 189 | apic_write(APIC_LVT0, value); |
208fb931 EB |
190 | } |
191 | else { | |
192 | /* Disable LVT0 */ | |
11a8e778 | 193 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
208fb931 EB |
194 | } |
195 | ||
196 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
197 | value = apic_read(APIC_LVT1); | |
198 | value &= ~( | |
199 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
200 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
201 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
202 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
203 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
11a8e778 | 204 | apic_write(APIC_LVT1, value); |
208fb931 | 205 | } |
1da177e4 LT |
206 | } |
207 | ||
208 | void disable_local_APIC(void) | |
209 | { | |
210 | unsigned int value; | |
211 | ||
212 | clear_local_APIC(); | |
213 | ||
214 | /* | |
215 | * Disable APIC (implies clearing of registers | |
216 | * for 82489DX!). | |
217 | */ | |
218 | value = apic_read(APIC_SPIV); | |
219 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 220 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
221 | } |
222 | ||
223 | /* | |
224 | * This is to verify that we're looking at a real local APIC. | |
225 | * Check these against your board if the CPUs aren't getting | |
226 | * started for no apparent reason. | |
227 | */ | |
228 | int __init verify_local_APIC(void) | |
229 | { | |
230 | unsigned int reg0, reg1; | |
231 | ||
232 | /* | |
233 | * The version register is read-only in a real APIC. | |
234 | */ | |
235 | reg0 = apic_read(APIC_LVR); | |
236 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
237 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
238 | reg1 = apic_read(APIC_LVR); | |
239 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
240 | ||
241 | /* | |
242 | * The two version reads above should print the same | |
243 | * numbers. If the second one is different, then we | |
244 | * poke at a non-APIC. | |
245 | */ | |
246 | if (reg1 != reg0) | |
247 | return 0; | |
248 | ||
249 | /* | |
250 | * Check if the version looks reasonably. | |
251 | */ | |
252 | reg1 = GET_APIC_VERSION(reg0); | |
253 | if (reg1 == 0x00 || reg1 == 0xff) | |
254 | return 0; | |
255 | reg1 = get_maxlvt(); | |
256 | if (reg1 < 0x02 || reg1 == 0xff) | |
257 | return 0; | |
258 | ||
259 | /* | |
260 | * The ID register is read/write in a real APIC. | |
261 | */ | |
262 | reg0 = apic_read(APIC_ID); | |
263 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
264 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
265 | reg1 = apic_read(APIC_ID); | |
266 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
267 | apic_write(APIC_ID, reg0); | |
268 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
269 | return 0; | |
270 | ||
271 | /* | |
272 | * The next two are just to see if we have sane values. | |
273 | * They're only really relevant if we're in Virtual Wire | |
274 | * compatibility mode, but most boxes are anymore. | |
275 | */ | |
276 | reg0 = apic_read(APIC_LVT0); | |
277 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
278 | reg1 = apic_read(APIC_LVT1); | |
279 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
280 | ||
281 | return 1; | |
282 | } | |
283 | ||
284 | void __init sync_Arb_IDs(void) | |
285 | { | |
286 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
287 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
288 | if (ver >= 0x14) /* P4 or higher */ | |
289 | return; | |
290 | ||
291 | /* | |
292 | * Wait for idle. | |
293 | */ | |
294 | apic_wait_icr_idle(); | |
295 | ||
296 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 297 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
298 | | APIC_DM_INIT); |
299 | } | |
300 | ||
301 | extern void __error_in_apic_c (void); | |
302 | ||
303 | /* | |
304 | * An initial setup of the virtual wire mode. | |
305 | */ | |
306 | void __init init_bsp_APIC(void) | |
307 | { | |
11a8e778 | 308 | unsigned int value; |
1da177e4 LT |
309 | |
310 | /* | |
311 | * Don't do the setup now if we have a SMP BIOS as the | |
312 | * through-I/O-APIC virtual wire mode might be active. | |
313 | */ | |
314 | if (smp_found_config || !cpu_has_apic) | |
315 | return; | |
316 | ||
317 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
318 | |
319 | /* | |
320 | * Do not trust the local APIC being empty at bootup. | |
321 | */ | |
322 | clear_local_APIC(); | |
323 | ||
324 | /* | |
325 | * Enable APIC. | |
326 | */ | |
327 | value = apic_read(APIC_SPIV); | |
328 | value &= ~APIC_VECTOR_MASK; | |
329 | value |= APIC_SPIV_APIC_ENABLED; | |
330 | value |= APIC_SPIV_FOCUS_DISABLED; | |
331 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 332 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
333 | |
334 | /* | |
335 | * Set up the virtual wire mode. | |
336 | */ | |
11a8e778 | 337 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 338 | value = APIC_DM_NMI; |
11a8e778 | 339 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
340 | } |
341 | ||
e6982c67 | 342 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 343 | { |
11a8e778 | 344 | unsigned int value, maxlvt; |
1da177e4 | 345 | |
1da177e4 | 346 | value = apic_read(APIC_LVR); |
1da177e4 LT |
347 | |
348 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
349 | __error_in_apic_c(); | |
350 | ||
351 | /* | |
352 | * Double-check whether this APIC is really registered. | |
353 | * This is meaningless in clustered apic mode, so we skip it. | |
354 | */ | |
355 | if (!apic_id_registered()) | |
356 | BUG(); | |
357 | ||
358 | /* | |
359 | * Intel recommends to set DFR, LDR and TPR before enabling | |
360 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
361 | * document number 292116). So here it goes... | |
362 | */ | |
363 | init_apic_ldr(); | |
364 | ||
365 | /* | |
366 | * Set Task Priority to 'accept all'. We never change this | |
367 | * later on. | |
368 | */ | |
369 | value = apic_read(APIC_TASKPRI); | |
370 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 371 | apic_write(APIC_TASKPRI, value); |
1da177e4 LT |
372 | |
373 | /* | |
374 | * Now that we are all set up, enable the APIC | |
375 | */ | |
376 | value = apic_read(APIC_SPIV); | |
377 | value &= ~APIC_VECTOR_MASK; | |
378 | /* | |
379 | * Enable APIC | |
380 | */ | |
381 | value |= APIC_SPIV_APIC_ENABLED; | |
382 | ||
383 | /* | |
384 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
385 | * certain networking cards. If high frequency interrupts are | |
386 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
387 | * entry is masked/unmasked at a high rate as well then sooner or | |
388 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
389 | * from the device. If focus CPU is disabled then the hang goes | |
390 | * away, oh well :-( | |
391 | * | |
392 | * [ This bug can be reproduced easily with a level-triggered | |
393 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
394 | * BX chipset. ] | |
395 | */ | |
396 | /* | |
397 | * Actually disabling the focus CPU check just makes the hang less | |
398 | * frequent as it makes the interrupt distributon model be more | |
399 | * like LRU than MRU (the short-term load is more even across CPUs). | |
400 | * See also the comment in end_level_ioapic_irq(). --macro | |
401 | */ | |
402 | #if 1 | |
403 | /* Enable focus processor (bit==0) */ | |
404 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
405 | #else | |
406 | /* Disable focus processor (bit==1) */ | |
407 | value |= APIC_SPIV_FOCUS_DISABLED; | |
408 | #endif | |
409 | /* | |
410 | * Set spurious IRQ vector | |
411 | */ | |
412 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 413 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
414 | |
415 | /* | |
416 | * Set up LVT0, LVT1: | |
417 | * | |
418 | * set up through-local-APIC on the BP's LINT0. This is not | |
419 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
420 | * we delegate interrupts to the 8259A. | |
421 | */ | |
422 | /* | |
423 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
424 | */ | |
425 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
426 | if (!smp_processor_id() && (pic_mode || !value)) { | |
427 | value = APIC_DM_EXTINT; | |
428 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
429 | } else { | |
430 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
431 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
432 | } | |
11a8e778 | 433 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
434 | |
435 | /* | |
436 | * only the BP should see the LINT1 NMI signal, obviously. | |
437 | */ | |
438 | if (!smp_processor_id()) | |
439 | value = APIC_DM_NMI; | |
440 | else | |
441 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 442 | apic_write(APIC_LVT1, value); |
1da177e4 | 443 | |
61c11341 | 444 | { |
1da177e4 LT |
445 | unsigned oldvalue; |
446 | maxlvt = get_maxlvt(); | |
1da177e4 LT |
447 | oldvalue = apic_read(APIC_ESR); |
448 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 449 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
450 | /* |
451 | * spec says clear errors after enabling vector. | |
452 | */ | |
453 | if (maxlvt > 3) | |
454 | apic_write(APIC_ESR, 0); | |
455 | value = apic_read(APIC_ESR); | |
456 | if (value != oldvalue) | |
457 | apic_printk(APIC_VERBOSE, | |
458 | "ESR value after enabling vector: %08x, after %08x\n", | |
459 | oldvalue, value); | |
1da177e4 LT |
460 | } |
461 | ||
462 | nmi_watchdog_default(); | |
463 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
464 | setup_apic_nmi_watchdog(); | |
465 | apic_pm_activate(); | |
466 | } | |
467 | ||
468 | #ifdef CONFIG_PM | |
469 | ||
470 | static struct { | |
471 | /* 'active' is true if the local APIC was enabled by us and | |
472 | not the BIOS; this signifies that we are also responsible | |
473 | for disabling it before entering apm/acpi suspend */ | |
474 | int active; | |
475 | /* r/w apic fields */ | |
476 | unsigned int apic_id; | |
477 | unsigned int apic_taskpri; | |
478 | unsigned int apic_ldr; | |
479 | unsigned int apic_dfr; | |
480 | unsigned int apic_spiv; | |
481 | unsigned int apic_lvtt; | |
482 | unsigned int apic_lvtpc; | |
483 | unsigned int apic_lvt0; | |
484 | unsigned int apic_lvt1; | |
485 | unsigned int apic_lvterr; | |
486 | unsigned int apic_tmict; | |
487 | unsigned int apic_tdcr; | |
488 | unsigned int apic_thmr; | |
489 | } apic_pm_state; | |
490 | ||
0b9c33a7 | 491 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
492 | { |
493 | unsigned long flags; | |
494 | ||
495 | if (!apic_pm_state.active) | |
496 | return 0; | |
497 | ||
498 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
499 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
500 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
501 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
502 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
503 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
504 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
505 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
506 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
507 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
508 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
509 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
510 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
511 | local_save_flags(flags); | |
512 | local_irq_disable(); | |
513 | disable_local_APIC(); | |
514 | local_irq_restore(flags); | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int lapic_resume(struct sys_device *dev) | |
519 | { | |
520 | unsigned int l, h; | |
521 | unsigned long flags; | |
522 | ||
523 | if (!apic_pm_state.active) | |
524 | return 0; | |
525 | ||
1da177e4 LT |
526 | local_irq_save(flags); |
527 | rdmsr(MSR_IA32_APICBASE, l, h); | |
528 | l &= ~MSR_IA32_APICBASE_BASE; | |
5b743573 | 529 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
1da177e4 LT |
530 | wrmsr(MSR_IA32_APICBASE, l, h); |
531 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
532 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
533 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
534 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
535 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
536 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
537 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
538 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
539 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
540 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
541 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
542 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
543 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
544 | apic_write(APIC_ESR, 0); | |
545 | apic_read(APIC_ESR); | |
546 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
547 | apic_write(APIC_ESR, 0); | |
548 | apic_read(APIC_ESR); | |
549 | local_irq_restore(flags); | |
550 | return 0; | |
551 | } | |
552 | ||
553 | static struct sysdev_class lapic_sysclass = { | |
554 | set_kset_name("lapic"), | |
555 | .resume = lapic_resume, | |
556 | .suspend = lapic_suspend, | |
557 | }; | |
558 | ||
559 | static struct sys_device device_lapic = { | |
560 | .id = 0, | |
561 | .cls = &lapic_sysclass, | |
562 | }; | |
563 | ||
e6982c67 | 564 | static void __cpuinit apic_pm_activate(void) |
1da177e4 LT |
565 | { |
566 | apic_pm_state.active = 1; | |
567 | } | |
568 | ||
569 | static int __init init_lapic_sysfs(void) | |
570 | { | |
571 | int error; | |
572 | if (!cpu_has_apic) | |
573 | return 0; | |
574 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
575 | error = sysdev_class_register(&lapic_sysclass); | |
576 | if (!error) | |
577 | error = sysdev_register(&device_lapic); | |
578 | return error; | |
579 | } | |
580 | device_initcall(init_lapic_sysfs); | |
581 | ||
582 | #else /* CONFIG_PM */ | |
583 | ||
584 | static void apic_pm_activate(void) { } | |
585 | ||
586 | #endif /* CONFIG_PM */ | |
587 | ||
588 | static int __init apic_set_verbosity(char *str) | |
589 | { | |
590 | if (strcmp("debug", str) == 0) | |
591 | apic_verbosity = APIC_DEBUG; | |
592 | else if (strcmp("verbose", str) == 0) | |
593 | apic_verbosity = APIC_VERBOSE; | |
594 | else | |
595 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
596 | " use apic=verbose or apic=debug", str); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | __setup("apic=", apic_set_verbosity); | |
602 | ||
603 | /* | |
604 | * Detect and enable local APICs on non-SMP boards. | |
605 | * Original code written by Keir Fraser. | |
606 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
607 | * not correctly set up (usually the APIC timer won't work etc.) | |
608 | */ | |
609 | ||
610 | static int __init detect_init_APIC (void) | |
611 | { | |
612 | if (!cpu_has_apic) { | |
613 | printk(KERN_INFO "No local APIC present\n"); | |
614 | return -1; | |
615 | } | |
616 | ||
617 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
618 | boot_cpu_id = 0; | |
619 | return 0; | |
620 | } | |
621 | ||
622 | void __init init_apic_mappings(void) | |
623 | { | |
624 | unsigned long apic_phys; | |
625 | ||
626 | /* | |
627 | * If no local APIC can be found then set up a fake all | |
628 | * zeroes page to simulate the local APIC and another | |
629 | * one for the IO-APIC. | |
630 | */ | |
631 | if (!smp_found_config && detect_init_APIC()) { | |
632 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
633 | apic_phys = __pa(apic_phys); | |
634 | } else | |
635 | apic_phys = mp_lapic_addr; | |
636 | ||
637 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
638 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); | |
639 | ||
640 | /* | |
641 | * Fetch the APIC ID of the BSP in case we have a | |
642 | * default configuration (or the MP table is broken). | |
643 | */ | |
1d3fbbf9 | 644 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
645 | |
646 | #ifdef CONFIG_X86_IO_APIC | |
647 | { | |
648 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
649 | int i; | |
650 | ||
651 | for (i = 0; i < nr_ioapics; i++) { | |
652 | if (smp_found_config) { | |
653 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
654 | } else { | |
655 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
656 | ioapic_phys = __pa(ioapic_phys); | |
657 | } | |
658 | set_fixmap_nocache(idx, ioapic_phys); | |
659 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", | |
660 | __fix_to_virt(idx), ioapic_phys); | |
661 | idx++; | |
662 | } | |
663 | } | |
664 | #endif | |
665 | } | |
666 | ||
667 | /* | |
668 | * This function sets up the local APIC timer, with a timeout of | |
669 | * 'clocks' APIC bus clock. During calibration we actually call | |
670 | * this function twice on the boot CPU, once with a bogus timeout | |
671 | * value, second time for real. The other (noncalibrating) CPUs | |
672 | * call this function only once, with the real, calibrated value. | |
673 | * | |
674 | * We do reads before writes even if unnecessary, to get around the | |
675 | * P5 APIC double write bug. | |
676 | */ | |
677 | ||
678 | #define APIC_DIVISOR 16 | |
679 | ||
680 | static void __setup_APIC_LVTT(unsigned int clocks) | |
681 | { | |
682 | unsigned int lvtt_value, tmp_value, ver; | |
d25bf7e5 | 683 | int cpu = smp_processor_id(); |
1da177e4 LT |
684 | |
685 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
686 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
d25bf7e5 VP |
687 | |
688 | if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) | |
689 | lvtt_value |= APIC_LVT_MASKED; | |
690 | ||
11a8e778 | 691 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
692 | |
693 | /* | |
694 | * Divide PICLK by 16 | |
695 | */ | |
696 | tmp_value = apic_read(APIC_TDCR); | |
11a8e778 | 697 | apic_write(APIC_TDCR, (tmp_value |
1da177e4 LT |
698 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
699 | | APIC_TDR_DIV_16); | |
700 | ||
11a8e778 | 701 | apic_write(APIC_TMICT, clocks/APIC_DIVISOR); |
1da177e4 LT |
702 | } |
703 | ||
704 | static void setup_APIC_timer(unsigned int clocks) | |
705 | { | |
706 | unsigned long flags; | |
707 | ||
708 | local_irq_save(flags); | |
709 | ||
1da177e4 | 710 | /* wait for irq slice */ |
33042a9f | 711 | if (vxtime.hpet_address && hpet_use_timer) { |
1da177e4 LT |
712 | int trigger = hpet_readl(HPET_T0_CMP); |
713 | while (hpet_readl(HPET_COUNTER) >= trigger) | |
714 | /* do nothing */ ; | |
715 | while (hpet_readl(HPET_COUNTER) < trigger) | |
716 | /* do nothing */ ; | |
717 | } else { | |
718 | int c1, c2; | |
719 | outb_p(0x00, 0x43); | |
720 | c2 = inb_p(0x40); | |
721 | c2 |= inb_p(0x40) << 8; | |
11a8e778 | 722 | do { |
1da177e4 LT |
723 | c1 = c2; |
724 | outb_p(0x00, 0x43); | |
725 | c2 = inb_p(0x40); | |
726 | c2 |= inb_p(0x40) << 8; | |
727 | } while (c2 - c1 < 300); | |
728 | } | |
1da177e4 | 729 | __setup_APIC_LVTT(clocks); |
73dea47f AK |
730 | /* Turn off PIT interrupt if we use APIC timer as main timer. |
731 | Only works with the PM timer right now | |
732 | TBD fix it for HPET too. */ | |
733 | if (vxtime.mode == VXTIME_PMTMR && | |
734 | smp_processor_id() == boot_cpu_id && | |
735 | apic_runs_main_timer == 1 && | |
736 | !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) { | |
737 | stop_timer_interrupt(); | |
738 | apic_runs_main_timer++; | |
739 | } | |
1da177e4 LT |
740 | local_irq_restore(flags); |
741 | } | |
742 | ||
743 | /* | |
744 | * In this function we calibrate APIC bus clocks to the external | |
745 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
746 | * to calibrate, since some later bootup code depends on getting | |
747 | * the first irq? Ugh. | |
748 | * | |
749 | * We want to do the calibration only once since we | |
750 | * want to have local timer irqs syncron. CPUs connected | |
751 | * by the same APIC bus have the very same bus frequency. | |
752 | * And we want to have irqs off anyways, no accidental | |
753 | * APIC irq that way. | |
754 | */ | |
755 | ||
756 | #define TICK_COUNT 100000000 | |
757 | ||
758 | static int __init calibrate_APIC_clock(void) | |
759 | { | |
760 | int apic, apic_start, tsc, tsc_start; | |
761 | int result; | |
762 | /* | |
763 | * Put whatever arbitrary (but long enough) timeout | |
764 | * value into the APIC clock, we just want to get the | |
765 | * counter running for calibration. | |
766 | */ | |
767 | __setup_APIC_LVTT(1000000000); | |
768 | ||
769 | apic_start = apic_read(APIC_TMCCT); | |
0c3749c4 AK |
770 | #ifdef CONFIG_X86_PM_TIMER |
771 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
772 | pmtimer_wait(5000); /* 5ms wait */ | |
1da177e4 | 773 | apic = apic_read(APIC_TMCCT); |
0c3749c4 AK |
774 | result = (apic_start - apic) * 1000L / 5; |
775 | } else | |
776 | #endif | |
777 | { | |
778 | rdtscl(tsc_start); | |
779 | ||
780 | do { | |
781 | apic = apic_read(APIC_TMCCT); | |
782 | rdtscl(tsc); | |
783 | } while ((tsc - tsc_start) < TICK_COUNT && | |
784 | (apic - apic_start) < TICK_COUNT); | |
785 | ||
786 | result = (apic_start - apic) * 1000L * cpu_khz / | |
787 | (tsc - tsc_start); | |
788 | } | |
789 | printk("result %d\n", result); | |
1da177e4 | 790 | |
1da177e4 LT |
791 | |
792 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
793 | result / 1000 / 1000, result / 1000 % 1000); | |
794 | ||
795 | return result * APIC_DIVISOR / HZ; | |
796 | } | |
797 | ||
798 | static unsigned int calibration_result; | |
799 | ||
800 | void __init setup_boot_APIC_clock (void) | |
801 | { | |
802 | if (disable_apic_timer) { | |
803 | printk(KERN_INFO "Disabling APIC timer\n"); | |
804 | return; | |
805 | } | |
806 | ||
807 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
808 | using_apic_timer = 1; | |
809 | ||
810 | local_irq_disable(); | |
811 | ||
812 | calibration_result = calibrate_APIC_clock(); | |
813 | /* | |
814 | * Now set up the timer for real. | |
815 | */ | |
816 | setup_APIC_timer(calibration_result); | |
817 | ||
818 | local_irq_enable(); | |
819 | } | |
820 | ||
e6982c67 | 821 | void __cpuinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
822 | { |
823 | local_irq_disable(); /* FIXME: Do we need this? --RR */ | |
824 | setup_APIC_timer(calibration_result); | |
825 | local_irq_enable(); | |
826 | } | |
827 | ||
d25bf7e5 | 828 | void disable_APIC_timer(void) |
1da177e4 LT |
829 | { |
830 | if (using_apic_timer) { | |
831 | unsigned long v; | |
832 | ||
833 | v = apic_read(APIC_LVTT); | |
11a8e778 | 834 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 LT |
835 | } |
836 | } | |
837 | ||
838 | void enable_APIC_timer(void) | |
839 | { | |
d25bf7e5 VP |
840 | int cpu = smp_processor_id(); |
841 | ||
842 | if (using_apic_timer && | |
843 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
1da177e4 LT |
844 | unsigned long v; |
845 | ||
846 | v = apic_read(APIC_LVTT); | |
11a8e778 | 847 | apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
848 | } |
849 | } | |
850 | ||
d25bf7e5 VP |
851 | void switch_APIC_timer_to_ipi(void *cpumask) |
852 | { | |
853 | cpumask_t mask = *(cpumask_t *)cpumask; | |
854 | int cpu = smp_processor_id(); | |
855 | ||
856 | if (cpu_isset(cpu, mask) && | |
857 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
858 | disable_APIC_timer(); | |
859 | cpu_set(cpu, timer_interrupt_broadcast_ipi_mask); | |
860 | } | |
861 | } | |
862 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
863 | ||
864 | void smp_send_timer_broadcast_ipi(void) | |
865 | { | |
866 | cpumask_t mask; | |
867 | ||
868 | cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask); | |
869 | if (!cpus_empty(mask)) { | |
870 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
871 | } | |
872 | } | |
873 | ||
874 | void switch_ipi_to_APIC_timer(void *cpumask) | |
875 | { | |
876 | cpumask_t mask = *(cpumask_t *)cpumask; | |
877 | int cpu = smp_processor_id(); | |
878 | ||
879 | if (cpu_isset(cpu, mask) && | |
880 | cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
881 | cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask); | |
882 | enable_APIC_timer(); | |
883 | } | |
884 | } | |
885 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
886 | ||
1da177e4 LT |
887 | int setup_profiling_timer(unsigned int multiplier) |
888 | { | |
5a07a30c | 889 | return -EINVAL; |
1da177e4 LT |
890 | } |
891 | ||
89b831ef JS |
892 | #ifdef CONFIG_X86_MCE_AMD |
893 | void setup_threshold_lvt(unsigned long lvt_off) | |
894 | { | |
895 | unsigned int v = 0; | |
896 | unsigned long reg = (lvt_off << 4) + 0x500; | |
897 | v |= THRESHOLD_APIC_VECTOR; | |
898 | apic_write(reg, v); | |
899 | } | |
900 | #endif /* CONFIG_X86_MCE_AMD */ | |
901 | ||
1da177e4 LT |
902 | #undef APIC_DIVISOR |
903 | ||
904 | /* | |
905 | * Local timer interrupt handler. It does both profiling and | |
906 | * process statistics/rescheduling. | |
907 | * | |
908 | * We do profiling in every local tick, statistics/rescheduling | |
909 | * happen only every 'profiling multiplier' ticks. The default | |
910 | * multiplier is 1 and it can be changed by writing the new multiplier | |
911 | * value into /proc/profile. | |
912 | */ | |
913 | ||
914 | void smp_local_timer_interrupt(struct pt_regs *regs) | |
915 | { | |
1da177e4 | 916 | profile_tick(CPU_PROFILING, regs); |
1da177e4 | 917 | #ifdef CONFIG_SMP |
5a07a30c | 918 | update_process_times(user_mode(regs)); |
1da177e4 | 919 | #endif |
73dea47f AK |
920 | if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id) |
921 | main_timer_handler(regs); | |
1da177e4 LT |
922 | /* |
923 | * We take the 'long' return path, and there every subsystem | |
924 | * grabs the appropriate locks (kernel lock/ irq lock). | |
925 | * | |
926 | * we might want to decouple profiling from the 'long path', | |
927 | * and do the profiling totally in assembly. | |
928 | * | |
929 | * Currently this isn't too much of an issue (performance wise), | |
930 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
931 | */ | |
932 | } | |
933 | ||
934 | /* | |
935 | * Local APIC timer interrupt. This is the most natural way for doing | |
936 | * local interrupts, but local timer interrupts can be emulated by | |
937 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
938 | * | |
939 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
940 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
941 | */ | |
942 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
943 | { | |
944 | /* | |
945 | * the NMI deadlock-detector uses this. | |
946 | */ | |
947 | add_pda(apic_timer_irqs, 1); | |
948 | ||
949 | /* | |
950 | * NOTE! We'd better ACK the irq immediately, | |
951 | * because timer handling can be slow. | |
952 | */ | |
953 | ack_APIC_irq(); | |
954 | /* | |
955 | * update_process_times() expects us to have done irq_enter(). | |
956 | * Besides, if we don't timer interrupts ignore the global | |
957 | * interrupt lock, which is the WrongThing (tm) to do. | |
958 | */ | |
95833c83 | 959 | exit_idle(); |
1da177e4 LT |
960 | irq_enter(); |
961 | smp_local_timer_interrupt(regs); | |
962 | irq_exit(); | |
963 | } | |
964 | ||
965 | /* | |
966 | * oem_force_hpet_timer -- force HPET mode for some boxes. | |
967 | * | |
968 | * Thus far, the major user of this is IBM's Summit2 series: | |
969 | * | |
637029c6 | 970 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
971 | * multi-chassis. Use available data to take a good guess. |
972 | * If in doubt, go HPET. | |
973 | */ | |
396bd50f | 974 | __cpuinit int oem_force_hpet_timer(void) |
1da177e4 LT |
975 | { |
976 | int i, clusters, zeros; | |
977 | unsigned id; | |
978 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
979 | ||
376ec33f | 980 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
981 | |
982 | for (i = 0; i < NR_CPUS; i++) { | |
983 | id = bios_cpu_apicid[i]; | |
984 | if (id != BAD_APICID) | |
985 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
986 | } | |
987 | ||
988 | /* Problem: Partially populated chassis may not have CPUs in some of | |
989 | * the APIC clusters they have been allocated. Only present CPUs have | |
990 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
991 | * clusters are allocated sequentially, count zeros only if they are | |
992 | * bounded by ones. | |
993 | */ | |
994 | clusters = 0; | |
995 | zeros = 0; | |
996 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
997 | if (test_bit(i, clustermap)) { | |
998 | clusters += 1 + zeros; | |
999 | zeros = 0; | |
1000 | } else | |
1001 | ++zeros; | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * If clusters > 2, then should be multi-chassis. Return 1 for HPET. | |
1006 | * Else return 0 to use TSC. | |
1007 | * May have to revisit this when multi-core + hyperthreaded CPUs come | |
1008 | * out, but AFAIK this will work even for them. | |
1009 | */ | |
1010 | return (clusters > 2); | |
1011 | } | |
1012 | ||
1013 | /* | |
1014 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1015 | */ | |
1016 | asmlinkage void smp_spurious_interrupt(void) | |
1017 | { | |
1018 | unsigned int v; | |
95833c83 | 1019 | exit_idle(); |
1da177e4 LT |
1020 | irq_enter(); |
1021 | /* | |
1022 | * Check if this really is a spurious interrupt and ACK it | |
1023 | * if it is a vectored one. Just in case... | |
1024 | * Spurious interrupts should not be ACKed. | |
1025 | */ | |
1026 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1027 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1028 | ack_APIC_irq(); | |
1029 | ||
1030 | #if 0 | |
1031 | static unsigned long last_warning; | |
1032 | static unsigned long skipped; | |
1033 | ||
1034 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1035 | if (time_before(last_warning+30*HZ,jiffies)) { | |
1036 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", | |
1037 | smp_processor_id(), skipped); | |
1038 | last_warning = jiffies; | |
1039 | skipped = 0; | |
1040 | } else { | |
1041 | skipped++; | |
1042 | } | |
1043 | #endif | |
1044 | irq_exit(); | |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | * This interrupt should never happen with our APIC/SMP architecture | |
1049 | */ | |
1050 | ||
1051 | asmlinkage void smp_error_interrupt(void) | |
1052 | { | |
1053 | unsigned int v, v1; | |
1054 | ||
95833c83 | 1055 | exit_idle(); |
1da177e4 LT |
1056 | irq_enter(); |
1057 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1058 | v = apic_read(APIC_ESR); | |
1059 | apic_write(APIC_ESR, 0); | |
1060 | v1 = apic_read(APIC_ESR); | |
1061 | ack_APIC_irq(); | |
1062 | atomic_inc(&irq_err_count); | |
1063 | ||
1064 | /* Here is what the APIC error bits mean: | |
1065 | 0: Send CS error | |
1066 | 1: Receive CS error | |
1067 | 2: Send accept error | |
1068 | 3: Receive accept error | |
1069 | 4: Reserved | |
1070 | 5: Send illegal vector | |
1071 | 6: Received illegal vector | |
1072 | 7: Illegal register address | |
1073 | */ | |
1074 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1075 | smp_processor_id(), v , v1); | |
1076 | irq_exit(); | |
1077 | } | |
1078 | ||
1079 | int disable_apic; | |
1080 | ||
1081 | /* | |
1082 | * This initializes the IO-APIC and APIC hardware if this is | |
1083 | * a UP kernel. | |
1084 | */ | |
1085 | int __init APIC_init_uniprocessor (void) | |
1086 | { | |
1087 | if (disable_apic) { | |
1088 | printk(KERN_INFO "Apic disabled\n"); | |
1089 | return -1; | |
1090 | } | |
1091 | if (!cpu_has_apic) { | |
1092 | disable_apic = 1; | |
1093 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1094 | return -1; | |
1095 | } | |
1096 | ||
1097 | verify_local_APIC(); | |
1098 | ||
1099 | connect_bsp_APIC(); | |
1100 | ||
357e11d4 | 1101 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
11a8e778 | 1102 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); |
1da177e4 LT |
1103 | |
1104 | setup_local_APIC(); | |
1105 | ||
1106 | #ifdef CONFIG_X86_IO_APIC | |
1107 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) | |
1108 | setup_IO_APIC(); | |
1109 | else | |
1110 | nr_ioapics = 0; | |
1111 | #endif | |
1112 | setup_boot_APIC_clock(); | |
75152114 | 1113 | check_nmi_watchdog(); |
1da177e4 LT |
1114 | return 0; |
1115 | } | |
1116 | ||
1117 | static __init int setup_disableapic(char *str) | |
1118 | { | |
1119 | disable_apic = 1; | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static __init int setup_nolapic(char *str) | |
1124 | { | |
1125 | disable_apic = 1; | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static __init int setup_noapictimer(char *str) | |
1130 | { | |
73dea47f AK |
1131 | if (str[0] != ' ' && str[0] != 0) |
1132 | return -1; | |
1da177e4 LT |
1133 | disable_apic_timer = 1; |
1134 | return 0; | |
1135 | } | |
1136 | ||
73dea47f AK |
1137 | static __init int setup_apicmaintimer(char *str) |
1138 | { | |
1139 | apic_runs_main_timer = 1; | |
1140 | nohpet = 1; | |
1141 | return 0; | |
1142 | } | |
1143 | __setup("apicmaintimer", setup_apicmaintimer); | |
1144 | ||
1145 | static __init int setup_noapicmaintimer(char *str) | |
1146 | { | |
1147 | apic_runs_main_timer = -1; | |
1148 | return 0; | |
1149 | } | |
1150 | __setup("noapicmaintimer", setup_noapicmaintimer); | |
1151 | ||
0c3749c4 AK |
1152 | static __init int setup_apicpmtimer(char *s) |
1153 | { | |
1154 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1155 | notsc_setup(NULL); |
0c3749c4 AK |
1156 | return setup_apicmaintimer(NULL); |
1157 | } | |
1158 | __setup("apicpmtimer", setup_apicpmtimer); | |
1159 | ||
1da177e4 LT |
1160 | /* dummy parsing: see setup.c */ |
1161 | ||
1162 | __setup("disableapic", setup_disableapic); | |
1163 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ | |
1164 | ||
1165 | __setup("noapictimer", setup_noapictimer); | |
1166 | ||
1167 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |