[linux-2.6-block.git] / arch / x86_64 / kernel / apic.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/hpet.h>
#include <asm/apic.h>

int apic_mapped;
int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

/* Local APIC timer works in C2? */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

static struct resource *ioapic_resources;
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;
	
	v = APIC_DM_NMI;                        /* unmask and set to NMI */
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
  	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = get_maxlvt();

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
	21	#include <linux/bootmem.h>
	22	#include <linux/smp_lock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/mc146818rtc.h>
	25	#include <linux/kernel_stat.h>
	26	#include <linux/sysdev.h>
d25bf7e5	27	#include <linux/module.h>
39928722	28	#include <linux/ioport.h>
1da177e4 LT	29
	30	#include <asm/atomic.h>
	31	#include <asm/smp.h>
	32	#include <asm/mtrr.h>
	33	#include <asm/mpspec.h>
	34	#include <asm/pgalloc.h>
	35	#include <asm/mach_apic.h>
75152114	36	#include <asm/nmi.h>
95833c83	37	#include <asm/idle.h>
73dea47f AK	38	#include <asm/proto.h>
73dea47f AK	39	#include <asm/timex.h>
2d0c87c3	40	#include <asm/hpet.h>
2c8c0e6b	41	#include <asm/apic.h>
1da177e4	42
b7f5e3c7	43	int apic_mapped;
1da177e4	44	int apic_verbosity;
73dea47f	45	int apic_runs_main_timer;
0c3749c4	46	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	47
	48	int disable_apic_timer __initdata;
	49
2e7c2838 LT	50	/* Local APIC timer works in C2? */
	51	int local_apic_timer_c2_ok;
	52	EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
	53
39928722 AD	54	static struct resource *ioapic_resources;
	55	static struct resource lapic_resource = {
	56	.name = "Local APIC",
	57	.flags = IORESOURCE_MEM \| IORESOURCE_BUSY,
	58	};
	59
d25bf7e5 VP	60	/*
	61	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	62	* IPIs in place of local APIC timers
	63	*/
	64	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	65
1da177e4	66	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	67	int using_apic_timer __read_mostly = 0;
1da177e4	68
1da177e4 LT	69	static void apic_pm_activate(void);
	70
	71	void enable_NMI_through_LVT0 (void * dummy)
	72	{
11a8e778	73	unsigned int v;
1da177e4	74
1da177e4	75	v = APIC_DM_NMI; /* unmask and set to NMI */
11a8e778	76	apic_write(APIC_LVT0, v);
1da177e4 LT	77	}
	78
	79	int get_maxlvt(void)
	80	{
11a8e778	81	unsigned int v, maxlvt;
1da177e4 LT	82
1da177e4 LT	83	v = apic_read(APIC_LVR);
1da177e4 LT	84	maxlvt = GET_APIC_MAXLVT(v);
	85	return maxlvt;
	86	}
	87
3777a959 AK	88	/*
	89	* 'what should we do if we get a hw irq event on an illegal vector'.
	90	* each architecture has to answer this themselves.
	91	*/
	92	void ack_bad_irq(unsigned int irq)
	93	{
	94	printk("unexpected IRQ trap at vector %02x\n", irq);
	95	/*
	96	* Currently unexpected vectors happen only on SMP and APIC.
	97	* We _must_ ack these because every local APIC has only N
	98	* irq slots per priority level, and a 'hanging, unacked' IRQ
	99	* holds up an irq slot - in excessive cases (when multiple
	100	* unexpected vectors occur) that might lock up the APIC
	101	* completely.
	102	* But don't ack when the APIC is disabled. -AK
	103	*/
	104	if (!disable_apic)
	105	ack_APIC_irq();
	106	}
	107
1da177e4 LT	108	void clear_local_APIC(void)
	109	{
	110	int maxlvt;
	111	unsigned int v;
	112
	113	maxlvt = get_maxlvt();
	114
	115	/*
704fc59e	116	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	117	* if the vector is zero. Mask LVTERR first to prevent this.
	118	*/
	119	if (maxlvt >= 3) {
	120	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	121	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	122	}
	123	/*
	124	* Careful: we have to set masks only first to deassert
	125	* any level-triggered sources.
	126	*/
	127	v = apic_read(APIC_LVTT);
11a8e778	128	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	129	v = apic_read(APIC_LVT0);
11a8e778	130	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	131	v = apic_read(APIC_LVT1);
11a8e778	132	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	133	if (maxlvt >= 4) {
1da177e4 LT	134	v = apic_read(APIC_LVTPC);
11a8e778	135	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	136	}
	137
	138	/*
	139	* Clean APIC state for other OSs:
	140	*/
11a8e778 AK	141	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	142	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	143	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	144	if (maxlvt >= 3)
11a8e778	145	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	146	if (maxlvt >= 4)
11a8e778	147	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
5a40b7c2 AK	148	apic_write(APIC_ESR, 0);
5a40b7c2 AK	149	apic_read(APIC_ESR);
1da177e4 LT	150	}
1da177e4 LT	151
208fb931	152	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	153	{
a8fcf1a2 AK	154	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	155	unsigned long value;
208fb931	156
a8fcf1a2 AK	157	/* For the spurious interrupt use vector F, and enable it */
	158	value = apic_read(APIC_SPIV);
	159	value &= ~APIC_VECTOR_MASK;
	160	value \|= APIC_SPIV_APIC_ENABLED;
	161	value \|= 0xf;
	162	apic_write(APIC_SPIV, value);
	163
	164	if (!virt_wire_setup) {
	165	/* For LVT0 make it edge triggered, active high, external and enabled */
	166	value = apic_read(APIC_LVT0);
	167	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	168	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	169	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	170	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	171	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	172	apic_write(APIC_LVT0, value);
	173	} else {
	174	/* Disable LVT0 */
	175	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	176	}
a8fcf1a2 AK	177
	178	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	179	value = apic_read(APIC_LVT1);
	180	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	181	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	182	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	183	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	184	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	185	apic_write(APIC_LVT1, value);
1da177e4 LT	186	}
	187
	188	void disable_local_APIC(void)
	189	{
	190	unsigned int value;
	191
	192	clear_local_APIC();
	193
	194	/*
	195	* Disable APIC (implies clearing of registers
	196	* for 82489DX!).
	197	*/
	198	value = apic_read(APIC_SPIV);
	199	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	200	apic_write(APIC_SPIV, value);
1da177e4 LT	201	}
	202
	203	/*
	204	* This is to verify that we're looking at a real local APIC.
	205	* Check these against your board if the CPUs aren't getting
	206	* started for no apparent reason.
	207	*/
	208	int __init verify_local_APIC(void)
	209	{
	210	unsigned int reg0, reg1;
	211
	212	/*
	213	* The version register is read-only in a real APIC.
	214	*/
	215	reg0 = apic_read(APIC_LVR);
	216	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	217	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	218	reg1 = apic_read(APIC_LVR);
	219	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	220
	221	/*
	222	* The two version reads above should print the same
	223	* numbers. If the second one is different, then we
	224	* poke at a non-APIC.
	225	*/
	226	if (reg1 != reg0)
	227	return 0;
	228
	229	/*
	230	* Check if the version looks reasonably.
	231	*/
	232	reg1 = GET_APIC_VERSION(reg0);
	233	if (reg1 == 0x00 \|\| reg1 == 0xff)
	234	return 0;
	235	reg1 = get_maxlvt();
	236	if (reg1 < 0x02 \|\| reg1 == 0xff)
	237	return 0;
	238
	239	/*
	240	* The ID register is read/write in a real APIC.
	241	*/
	242	reg0 = apic_read(APIC_ID);
	243	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	244	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	245	reg1 = apic_read(APIC_ID);
	246	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	247	apic_write(APIC_ID, reg0);
	248	if (reg1 != (reg0 ^ APIC_ID_MASK))
	249	return 0;
	250
	251	/*
	252	* The next two are just to see if we have sane values.
	253	* They're only really relevant if we're in Virtual Wire
	254	* compatibility mode, but most boxes are anymore.
	255	*/
	256	reg0 = apic_read(APIC_LVT0);
	257	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	258	reg1 = apic_read(APIC_LVT1);
	259	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	260
	261	return 1;
	262	}
	263
	264	void __init sync_Arb_IDs(void)
265	{
266	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
267	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
268	if (ver >= 0x14) /* P4 or higher */
269	return;
270
271	/*
272	* Wait for idle.
273	*/
274	apic_wait_icr_idle();
275
276	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	277	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	278	\| APIC_DM_INIT);
	279	}
	280
1da177e4 LT	281	/*
	282	* An initial setup of the virtual wire mode.
	283	*/
	284	void __init init_bsp_APIC(void)
	285	{
11a8e778	286	unsigned int value;
1da177e4 LT	287
	288	/*
	289	* Don't do the setup now if we have a SMP BIOS as the
	290	* through-I/O-APIC virtual wire mode might be active.
	291	*/
	292	if (smp_found_config \|\| !cpu_has_apic)
	293	return;
	294
	295	value = apic_read(APIC_LVR);
1da177e4 LT	296
	297	/*
	298	* Do not trust the local APIC being empty at bootup.
	299	*/
	300	clear_local_APIC();
	301
	302	/*
	303	* Enable APIC.
	304	*/
	305	value = apic_read(APIC_SPIV);
	306	value &= ~APIC_VECTOR_MASK;
	307	value \|= APIC_SPIV_APIC_ENABLED;
	308	value \|= APIC_SPIV_FOCUS_DISABLED;
	309	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	310	apic_write(APIC_SPIV, value);
1da177e4 LT	311
	312	/*
	313	* Set up the virtual wire mode.
	314	*/
11a8e778	315	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	316	value = APIC_DM_NMI;
11a8e778	317	apic_write(APIC_LVT1, value);
1da177e4 LT	318	}
1da177e4 LT	319
e6982c67	320	void __cpuinit setup_local_APIC (void)
1da177e4	321	{
11a8e778	322	unsigned int value, maxlvt;
da7ed9f9	323	int i, j;
1da177e4	324
1da177e4	325	value = apic_read(APIC_LVR);
1da177e4	326
fe7414a2	327	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	328
	329	/*
	330	* Double-check whether this APIC is really registered.
	331	* This is meaningless in clustered apic mode, so we skip it.
	332	*/
	333	if (!apic_id_registered())
	334	BUG();
	335
	336	/*
	337	* Intel recommends to set DFR, LDR and TPR before enabling
	338	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	339	* document number 292116). So here it goes...
	340	*/
	341	init_apic_ldr();
	342
	343	/*
	344	* Set Task Priority to 'accept all'. We never change this
	345	* later on.
	346	*/
	347	value = apic_read(APIC_TASKPRI);
	348	value &= ~APIC_TPRI_MASK;
11a8e778	349	apic_write(APIC_TASKPRI, value);
1da177e4	350
da7ed9f9 VG	351	/*
	352	* After a crash, we no longer service the interrupts and a pending
	353	* interrupt from previous kernel might still have ISR bit set.
	354	*
	355	* Most probably by now CPU has serviced that pending interrupt and
	356	* it might not have done the ack_APIC_irq() because it thought,
	357	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	358	* does not clear the ISR bit and cpu thinks it has already serivced
	359	* the interrupt. Hence a vector might get locked. It was noticed
	360	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	361	*/
	362	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	363	value = apic_read(APIC_ISR + i*0x10);
	364	for (j = 31; j >= 0; j--) {
	365	if (value & (1<<j))
	366	ack_APIC_irq();
	367	}
	368	}
	369
1da177e4 LT	370	/*
	371	* Now that we are all set up, enable the APIC
	372	*/
	373	value = apic_read(APIC_SPIV);
	374	value &= ~APIC_VECTOR_MASK;
	375	/*
	376	* Enable APIC
	377	*/
	378	value \|= APIC_SPIV_APIC_ENABLED;
	379
3f14c746 AK	380	/* We always use processor focus */
3f14c746 AK	381
1da177e4 LT	382	/*
	383	* Set spurious IRQ vector
	384	*/
	385	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	386	apic_write(APIC_SPIV, value);
1da177e4 LT	387
	388	/*
	389	* Set up LVT0, LVT1:
	390	*
	391	* set up through-local-APIC on the BP's LINT0. This is not
	392	* strictly necessary in pure symmetric-IO mode, but sometimes
	393	* we delegate interrupts to the 8259A.
	394	*/
	395	/*
	396	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	397	*/
	398	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	399	if (!smp_processor_id() && !value) {
1da177e4 LT	400	value = APIC_DM_EXTINT;
	401	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	402	} else {
	403	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	404	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	405	}
11a8e778	406	apic_write(APIC_LVT0, value);
1da177e4 LT	407
	408	/*
	409	* only the BP should see the LINT1 NMI signal, obviously.
	410	*/
	411	if (!smp_processor_id())
	412	value = APIC_DM_NMI;
	413	else
	414	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	415	apic_write(APIC_LVT1, value);
1da177e4	416
61c11341	417	{
1da177e4 LT	418	unsigned oldvalue;
1da177e4 LT	419	maxlvt = get_maxlvt();
1da177e4 LT	420	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	421	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	422	apic_write(APIC_LVTERR, value);
1da177e4 LT	423	/*
	424	* spec says clear errors after enabling vector.
	425	*/
	426	if (maxlvt > 3)
	427	apic_write(APIC_ESR, 0);
	428	value = apic_read(APIC_ESR);
	429	if (value != oldvalue)
	430	apic_printk(APIC_VERBOSE,
	431	"ESR value after enabling vector: %08x, after %08x\n",
	432	oldvalue, value);
1da177e4 LT	433	}
	434
	435	nmi_watchdog_default();
f2802e7f	436	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	437	apic_pm_activate();
	438	}
	439
	440	#ifdef CONFIG_PM
	441
	442	static struct {
	443	/* 'active' is true if the local APIC was enabled by us and
	444	not the BIOS; this signifies that we are also responsible
	445	for disabling it before entering apm/acpi suspend */
	446	int active;
	447	/* r/w apic fields */
	448	unsigned int apic_id;
	449	unsigned int apic_taskpri;
	450	unsigned int apic_ldr;
	451	unsigned int apic_dfr;
	452	unsigned int apic_spiv;
	453	unsigned int apic_lvtt;
	454	unsigned int apic_lvtpc;
	455	unsigned int apic_lvt0;
	456	unsigned int apic_lvt1;
	457	unsigned int apic_lvterr;
	458	unsigned int apic_tmict;
	459	unsigned int apic_tdcr;
	460	unsigned int apic_thmr;
	461	} apic_pm_state;
	462
0b9c33a7	463	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	464	{
1da177e4 LT	465	unsigned long flags;
f990fff4	466	int maxlvt;
1da177e4 LT	467
	468	if (!apic_pm_state.active)
	469	return 0;
	470
f990fff4 KW	471	maxlvt = get_maxlvt();
f990fff4 KW	472
1da177e4 LT	473	apic_pm_state.apic_id = apic_read(APIC_ID);
	474	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	475	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	476	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	477	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	478	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
f990fff4 KW	479	if (maxlvt >= 4)
f990fff4 KW	480	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1da177e4 LT	481	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	482	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	483	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	484	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	485	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
f990fff4 KW	486	#ifdef CONFIG_X86_MCE_INTEL
	487	if (maxlvt >= 5)
	488	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
	489	#endif