[linux-2.6-block.git] / arch / x86_64 / kernel / apic.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/hpet.h>
#include <asm/apic.h>

int apic_mapped;
int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

/* Local APIC timer works in C2? */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

static struct resource *ioapic_resources;
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void apic_wait_icr_idle(void)
{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

unsigned int safe_apic_wait_icr_idle(void)
{
	unsigned int send_status;
	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;
	
	v = APIC_DM_NMI;                        /* unmask and set to NMI */
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
  	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = get_maxlvt();

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
1da177e4 LT	21	#include <linux/bootmem.h>
1da177e4 LT	22	#include <linux/interrupt.h>
	23	#include <linux/mc146818rtc.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/sysdev.h>
d25bf7e5	26	#include <linux/module.h>
39928722	27	#include <linux/ioport.h>
1da177e4 LT	28
	29	#include <asm/atomic.h>
	30	#include <asm/smp.h>
	31	#include <asm/mtrr.h>
	32	#include <asm/mpspec.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/mach_apic.h>
75152114	35	#include <asm/nmi.h>
95833c83	36	#include <asm/idle.h>
73dea47f AK	37	#include <asm/proto.h>
73dea47f AK	38	#include <asm/timex.h>
2d0c87c3	39	#include <asm/hpet.h>
2c8c0e6b	40	#include <asm/apic.h>
1da177e4	41
b7f5e3c7	42	int apic_mapped;
1da177e4	43	int apic_verbosity;
73dea47f	44	int apic_runs_main_timer;
0c3749c4	45	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	46
	47	int disable_apic_timer __initdata;
	48
2e7c2838 LT	49	/* Local APIC timer works in C2? */
	50	int local_apic_timer_c2_ok;
	51	EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
	52
39928722 AD	53	static struct resource *ioapic_resources;
	54	static struct resource lapic_resource = {
	55	.name = "Local APIC",
	56	.flags = IORESOURCE_MEM \| IORESOURCE_BUSY,
	57	};
	58
d25bf7e5 VP	59	/*
	60	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	61	* IPIs in place of local APIC timers
	62	*/
	63	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	64
1da177e4	65	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	66	int using_apic_timer __read_mostly = 0;
1da177e4	67
1da177e4 LT	68	static void apic_pm_activate(void);
1da177e4 LT	69
8339e9fb FLV	70	void apic_wait_icr_idle(void)
	71	{
	72	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
	73	cpu_relax();
	74	}
	75
	76	unsigned int safe_apic_wait_icr_idle(void)
	77	{
	78	unsigned int send_status;
	79	int timeout;
	80
	81	timeout = 0;
	82	do {
	83	send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
	84	if (!send_status)
	85	break;
	86	udelay(100);
	87	} while (timeout++ < 1000);
	88
	89	return send_status;
	90	}
	91
1da177e4 LT	92	void enable_NMI_through_LVT0 (void * dummy)
1da177e4 LT	93	{
11a8e778	94	unsigned int v;
1da177e4	95
1da177e4	96	v = APIC_DM_NMI; /* unmask and set to NMI */
11a8e778	97	apic_write(APIC_LVT0, v);
1da177e4 LT	98	}
	99
	100	int get_maxlvt(void)
	101	{
11a8e778	102	unsigned int v, maxlvt;
1da177e4 LT	103
1da177e4 LT	104	v = apic_read(APIC_LVR);
1da177e4 LT	105	maxlvt = GET_APIC_MAXLVT(v);
	106	return maxlvt;
	107	}
	108
3777a959 AK	109	/*
	110	* 'what should we do if we get a hw irq event on an illegal vector'.
	111	* each architecture has to answer this themselves.
	112	*/
	113	void ack_bad_irq(unsigned int irq)
	114	{
	115	printk("unexpected IRQ trap at vector %02x\n", irq);
	116	/*
	117	* Currently unexpected vectors happen only on SMP and APIC.
	118	* We _must_ ack these because every local APIC has only N
	119	* irq slots per priority level, and a 'hanging, unacked' IRQ
	120	* holds up an irq slot - in excessive cases (when multiple
	121	* unexpected vectors occur) that might lock up the APIC
	122	* completely.
	123	* But don't ack when the APIC is disabled. -AK
	124	*/
	125	if (!disable_apic)
	126	ack_APIC_irq();
	127	}
	128
1da177e4 LT	129	void clear_local_APIC(void)
	130	{
	131	int maxlvt;
	132	unsigned int v;
	133
	134	maxlvt = get_maxlvt();
	135
	136	/*
704fc59e	137	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	138	* if the vector is zero. Mask LVTERR first to prevent this.
	139	*/
	140	if (maxlvt >= 3) {
	141	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	142	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	143	}
	144	/*
	145	* Careful: we have to set masks only first to deassert
	146	* any level-triggered sources.
	147	*/
	148	v = apic_read(APIC_LVTT);
11a8e778	149	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	150	v = apic_read(APIC_LVT0);
11a8e778	151	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	152	v = apic_read(APIC_LVT1);
11a8e778	153	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	154	if (maxlvt >= 4) {
1da177e4 LT	155	v = apic_read(APIC_LVTPC);
11a8e778	156	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	157	}
	158
	159	/*
	160	* Clean APIC state for other OSs:
	161	*/
11a8e778 AK	162	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	163	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	164	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	165	if (maxlvt >= 3)
11a8e778	166	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	167	if (maxlvt >= 4)
11a8e778	168	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
5a40b7c2 AK	169	apic_write(APIC_ESR, 0);
5a40b7c2 AK	170	apic_read(APIC_ESR);
1da177e4 LT	171	}
1da177e4 LT	172
208fb931	173	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	174	{
a8fcf1a2 AK	175	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	176	unsigned long value;
208fb931	177
a8fcf1a2 AK	178	/* For the spurious interrupt use vector F, and enable it */
	179	value = apic_read(APIC_SPIV);
	180	value &= ~APIC_VECTOR_MASK;
	181	value \|= APIC_SPIV_APIC_ENABLED;
	182	value \|= 0xf;
	183	apic_write(APIC_SPIV, value);
	184
	185	if (!virt_wire_setup) {
	186	/* For LVT0 make it edge triggered, active high, external and enabled */
	187	value = apic_read(APIC_LVT0);
	188	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	189	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	190	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	191	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	192	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	193	apic_write(APIC_LVT0, value);
	194	} else {
	195	/* Disable LVT0 */
	196	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	197	}
a8fcf1a2 AK	198
	199	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	200	value = apic_read(APIC_LVT1);
	201	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	202	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	203	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	204	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	205	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	206	apic_write(APIC_LVT1, value);
1da177e4 LT	207	}
	208
	209	void disable_local_APIC(void)
	210	{
	211	unsigned int value;
	212
	213	clear_local_APIC();
	214
	215	/*
	216	* Disable APIC (implies clearing of registers
	217	* for 82489DX!).
	218	*/
	219	value = apic_read(APIC_SPIV);
	220	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	221	apic_write(APIC_SPIV, value);
1da177e4 LT	222	}
	223
	224	/*
	225	* This is to verify that we're looking at a real local APIC.
	226	* Check these against your board if the CPUs aren't getting
	227	* started for no apparent reason.
	228	*/
	229	int __init verify_local_APIC(void)
	230	{
	231	unsigned int reg0, reg1;
	232
	233	/*
	234	* The version register is read-only in a real APIC.
	235	*/
	236	reg0 = apic_read(APIC_LVR);
	237	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	238	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	239	reg1 = apic_read(APIC_LVR);
	240	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	241
	242	/*
	243	* The two version reads above should print the same
	244	* numbers. If the second one is different, then we
	245	* poke at a non-APIC.
	246	*/
	247	if (reg1 != reg0)
	248	return 0;
	249
	250	/*
	251	* Check if the version looks reasonably.
	252	*/
	253	reg1 = GET_APIC_VERSION(reg0);
	254	if (reg1 == 0x00 \|\| reg1 == 0xff)
	255	return 0;
	256	reg1 = get_maxlvt();
	257	if (reg1 < 0x02 \|\| reg1 == 0xff)
	258	return 0;
	259
	260	/*
	261	* The ID register is read/write in a real APIC.
	262	*/
	263	reg0 = apic_read(APIC_ID);
	264	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	265	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	266	reg1 = apic_read(APIC_ID);
	267	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	268	apic_write(APIC_ID, reg0);
	269	if (reg1 != (reg0 ^ APIC_ID_MASK))
	270	return 0;
	271
	272	/*
	273	* The next two are just to see if we have sane values.
	274	* They're only really relevant if we're in Virtual Wire
	275	* compatibility mode, but most boxes are anymore.
	276	*/
	277	reg0 = apic_read(APIC_LVT0);
	278	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	279	reg1 = apic_read(APIC_LVT1);
	280	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	281
	282	return 1;
	283	}
	284
	285	void __init sync_Arb_IDs(void)
286	{
287	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
288	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
289	if (ver >= 0x14) /* P4 or higher */
290	return;
291
292	/*
293	* Wait for idle.
294	*/
295	apic_wait_icr_idle();
296
297	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	298	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	299	\| APIC_DM_INIT);
	300	}
	301
1da177e4 LT	302	/*
	303	* An initial setup of the virtual wire mode.
	304	*/
	305	void __init init_bsp_APIC(void)
	306	{
11a8e778	307	unsigned int value;
1da177e4 LT	308
	309	/*
	310	* Don't do the setup now if we have a SMP BIOS as the
	311	* through-I/O-APIC virtual wire mode might be active.
	312	*/
	313	if (smp_found_config \|\| !cpu_has_apic)
	314	return;
	315
	316	value = apic_read(APIC_LVR);
1da177e4 LT	317
	318	/*
	319	* Do not trust the local APIC being empty at bootup.
	320	*/
	321	clear_local_APIC();
	322
	323	/*
	324	* Enable APIC.
	325	*/
	326	value = apic_read(APIC_SPIV);
	327	value &= ~APIC_VECTOR_MASK;
	328	value \|= APIC_SPIV_APIC_ENABLED;
	329	value \|= APIC_SPIV_FOCUS_DISABLED;
	330	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	331	apic_write(APIC_SPIV, value);
1da177e4 LT	332
	333	/*
	334	* Set up the virtual wire mode.
	335	*/
11a8e778	336	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	337	value = APIC_DM_NMI;
11a8e778	338	apic_write(APIC_LVT1, value);
1da177e4 LT	339	}
1da177e4 LT	340
e6982c67	341	void __cpuinit setup_local_APIC (void)
1da177e4	342	{
11a8e778	343	unsigned int value, maxlvt;
da7ed9f9	344	int i, j;
1da177e4	345
1da177e4	346	value = apic_read(APIC_LVR);
1da177e4	347
fe7414a2	348	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	349
	350	/*
	351	* Double-check whether this APIC is really registered.
	352	* This is meaningless in clustered apic mode, so we skip it.
	353	*/
	354	if (!apic_id_registered())
	355	BUG();
	356
	357	/*
	358	* Intel recommends to set DFR, LDR and TPR before enabling
	359	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	360	* document number 292116). So here it goes...
	361	*/
	362	init_apic_ldr();
	363
	364	/*
	365	* Set Task Priority to 'accept all'. We never change this
	366	* later on.
	367	*/
	368	value = apic_read(APIC_TASKPRI);
	369	value &= ~APIC_TPRI_MASK;
11a8e778	370	apic_write(APIC_TASKPRI, value);
1da177e4	371
da7ed9f9 VG	372	/*
	373	* After a crash, we no longer service the interrupts and a pending
	374	* interrupt from previous kernel might still have ISR bit set.
	375	*
	376	* Most probably by now CPU has serviced that pending interrupt and
	377	* it might not have done the ack_APIC_irq() because it thought,
	378	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	379	* does not clear the ISR bit and cpu thinks it has already serivced
	380	* the interrupt. Hence a vector might get locked. It was noticed
	381	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	382	*/
	383	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	384	value = apic_read(APIC_ISR + i*0x10);
	385	for (j = 31; j >= 0; j--) {
	386	if (value & (1<<j))
	387	ack_APIC_irq();
	388	}
	389	}
	390
1da177e4 LT	391	/*
	392	* Now that we are all set up, enable the APIC
	393	*/
	394	value = apic_read(APIC_SPIV);
	395	value &= ~APIC_VECTOR_MASK;
	396	/*
	397	* Enable APIC
	398	*/
	399	value \|= APIC_SPIV_APIC_ENABLED;
	400
3f14c746 AK	401	/* We always use processor focus */
3f14c746 AK	402
1da177e4 LT	403	/*
	404	* Set spurious IRQ vector
	405	*/
	406	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	407	apic_write(APIC_SPIV, value);
1da177e4 LT	408
	409	/*
	410	* Set up LVT0, LVT1:
	411	*
	412	* set up through-local-APIC on the BP's LINT0. This is not
	413	* strictly necessary in pure symmetric-IO mode, but sometimes
	414	* we delegate interrupts to the 8259A.
	415	*/
	416	/*
	417	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	418	*/
	419	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	420	if (!smp_processor_id() && !value) {
1da177e4 LT	421	value = APIC_DM_EXTINT;
	422	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	423	} else {
	424	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	425	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	426	}
11a8e778	427	apic_write(APIC_LVT0, value);
1da177e4 LT	428
	429	/*
	430	* only the BP should see the LINT1 NMI signal, obviously.
	431	*/
	432	if (!smp_processor_id())
	433	value = APIC_DM_NMI;
	434	else
	435	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	436	apic_write(APIC_LVT1, value);
1da177e4	437
61c11341	438	{
1da177e4 LT	439	unsigned oldvalue;
1da177e4 LT	440	maxlvt = get_maxlvt();
1da177e4 LT	441	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	442	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	443	apic_write(APIC_LVTERR, value);
1da177e4 LT	444	/*
	445	* spec says clear errors after enabling vector.
	446	*/
	447	if (maxlvt > 3)
	448	apic_write(APIC_ESR, 0);
	449	value = apic_read(APIC_ESR);
	450	if (value != oldvalue)
	451	apic_printk(APIC_VERBOSE,
	452	"ESR value after enabling vector: %08x, after %08x\n",
	453	oldvalue, value);
1da177e4 LT	454	}
	455
	456	nmi_watchdog_default();
f2802e7f	457	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	458	apic_pm_activate();
	459	}
	460
	461	#ifdef CONFIG_PM
	462
	463	static struct {
	464	/* 'active' is true if the local APIC was enabled by us and
	465	not the BIOS; this signifies that we are also responsible
	466	for disabling it before entering apm/acpi suspend */
	467	int active;
	468	/* r/w apic fields */
	469	unsigned int apic_id;
	470	unsigned int apic_taskpri;
	471	unsigned int apic_ldr;
	472	unsigned int apic_dfr;
	473	unsigned int apic_spiv;
	474	unsigned int apic_lvtt;
	475	unsigned int apic_lvtpc;
	476	unsigned int apic_lvt0;
	477	unsigned int apic_lvt1;
	478	unsigned int apic_lvterr;
	479	unsigned int apic_tmict;
	480	unsigned int apic_tdcr;
	481	unsigned int apic_thmr;
	482	} apic_pm_state;
	483
0b9c33a7	484	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	485	{
1da177e4 LT	486	unsigned long flags;
f990fff4	487	int maxlvt;
1da177e4 LT	488
	489	if (!apic_pm_state.active)
	490	return 0;
	491
f990fff4 KW	492	maxlvt = get_maxlvt();
f990fff4 KW	493
1da177e4 LT	494	apic_pm_state.apic_id = apic_read(APIC_ID);
	495	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	496	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	497	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	498	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	499	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
f990fff4 KW	500	if (maxlvt >= 4)
f990fff4 KW	501	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1da177e4 LT	502	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	503	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	504	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	505	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	506	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
f990fff4 KW	507	#ifdef CONFIG_X86_MCE_INTEL
	508	if (maxlvt >= 5)
	509	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
	510	#endif