Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
5393744b | 2 | /* |
edcb5cf8 | 3 | * Asm versions of Xen pv-ops, suitable for direct use. |
130ace11 TH |
4 | * |
5 | * We only bother with direct forms (ie, vcpu in percpu data) of the | |
edcb5cf8 | 6 | * operations here; the indirect forms are better handled in C. |
5393744b JF |
7 | */ |
8 | ||
9 | #include <asm/asm-offsets.h> | |
10 | #include <asm/percpu.h> | |
11 | #include <asm/processor-flags.h> | |
8be0eb7e | 12 | #include <asm/frame.h> |
5393744b | 13 | |
edcb5cf8 | 14 | #include <linux/linkage.h> |
5393744b JF |
15 | |
16 | /* | |
130ace11 TH |
17 | * Enable events. This clears the event mask and tests the pending |
18 | * event status with one and operation. If there are pending events, | |
19 | * then enter the hypervisor to get them handled. | |
5393744b JF |
20 | */ |
21 | ENTRY(xen_irq_enable_direct) | |
8be0eb7e | 22 | FRAME_BEGIN |
5393744b JF |
23 | /* Unmask events */ |
24 | movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask | |
25 | ||
130ace11 TH |
26 | /* |
27 | * Preempt here doesn't matter because that will deal with any | |
28 | * pending interrupts. The pending check may end up being run | |
29 | * on the wrong CPU, but that doesn't hurt. | |
30 | */ | |
5393744b JF |
31 | |
32 | /* Test for pending */ | |
33 | testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending | |
34 | jz 1f | |
35 | ||
edcb5cf8 | 36 | call check_events |
5393744b | 37 | 1: |
8be0eb7e | 38 | FRAME_END |
5393744b JF |
39 | ret |
40 | ENDPROC(xen_irq_enable_direct) | |
5393744b JF |
41 | |
42 | ||
43 | /* | |
130ace11 TH |
44 | * Disabling events is simply a matter of making the event mask |
45 | * non-zero. | |
5393744b JF |
46 | */ |
47 | ENTRY(xen_irq_disable_direct) | |
48 | movb $1, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask | |
5393744b | 49 | ret |
edcb5cf8 | 50 | ENDPROC(xen_irq_disable_direct) |
5393744b JF |
51 | |
52 | /* | |
130ace11 TH |
53 | * (xen_)save_fl is used to get the current interrupt enable status. |
54 | * Callers expect the status to be in X86_EFLAGS_IF, and other bits | |
55 | * may be set in the return value. We take advantage of this by | |
56 | * making sure that X86_EFLAGS_IF has the right value (and other bits | |
57 | * in that byte are 0), but other bits in the return value are | |
58 | * undefined. We need to toggle the state of the bit, because Xen and | |
59 | * x86 use opposite senses (mask vs enable). | |
5393744b JF |
60 | */ |
61 | ENTRY(xen_save_fl_direct) | |
62 | testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask | |
63 | setz %ah | |
130ace11 | 64 | addb %ah, %ah |
5393744b JF |
65 | ret |
66 | ENDPROC(xen_save_fl_direct) | |
5393744b JF |
67 | |
68 | ||
69 | /* | |
130ace11 TH |
70 | * In principle the caller should be passing us a value return from |
71 | * xen_save_fl_direct, but for robustness sake we test only the | |
72 | * X86_EFLAGS_IF flag rather than the whole byte. After setting the | |
73 | * interrupt mask state, it checks for unmasked pending events and | |
74 | * enters the hypervisor to get them delivered if so. | |
5393744b JF |
75 | */ |
76 | ENTRY(xen_restore_fl_direct) | |
8be0eb7e | 77 | FRAME_BEGIN |
5393744b JF |
78 | #ifdef CONFIG_X86_64 |
79 | testw $X86_EFLAGS_IF, %di | |
80 | #else | |
81 | testb $X86_EFLAGS_IF>>8, %ah | |
82 | #endif | |
83 | setz PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask | |
130ace11 TH |
84 | /* |
85 | * Preempt here doesn't matter because that will deal with any | |
86 | * pending interrupts. The pending check may end up being run | |
87 | * on the wrong CPU, but that doesn't hurt. | |
88 | */ | |
5393744b JF |
89 | |
90 | /* check for unmasked and pending */ | |
91 | cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending | |
7eb7ce4d | 92 | jnz 1f |
edcb5cf8 | 93 | call check_events |
5393744b | 94 | 1: |
8be0eb7e | 95 | FRAME_END |
5393744b JF |
96 | ret |
97 | ENDPROC(xen_restore_fl_direct) | |
5393744b JF |
98 | |
99 | ||
100 | /* | |
130ace11 TH |
101 | * Force an event check by making a hypercall, but preserve regs |
102 | * before making the call. | |
5393744b | 103 | */ |
8be0eb7e JP |
104 | ENTRY(check_events) |
105 | FRAME_BEGIN | |
5393744b JF |
106 | #ifdef CONFIG_X86_32 |
107 | push %eax | |
108 | push %ecx | |
109 | push %edx | |
110 | call xen_force_evtchn_callback | |
111 | pop %edx | |
112 | pop %ecx | |
113 | pop %eax | |
114 | #else | |
115 | push %rax | |
116 | push %rcx | |
117 | push %rdx | |
118 | push %rsi | |
119 | push %rdi | |
120 | push %r8 | |
121 | push %r9 | |
122 | push %r10 | |
123 | push %r11 | |
124 | call xen_force_evtchn_callback | |
125 | pop %r11 | |
126 | pop %r10 | |
127 | pop %r9 | |
128 | pop %r8 | |
129 | pop %rdi | |
130 | pop %rsi | |
131 | pop %rdx | |
132 | pop %rcx | |
133 | pop %rax | |
134 | #endif | |
8be0eb7e | 135 | FRAME_END |
5393744b | 136 | ret |
8be0eb7e | 137 | ENDPROC(check_events) |